head	1.1;
branch	1.1.1;
access;
symbols
	netbsd-11-0-RC6:1.1.1.1
	netbsd-11-0-RC5:1.1.1.1
	netbsd-11-0-RC4:1.1.1.1
	netbsd-11-0-RC3:1.1.1.1
	netbsd-11-0-RC2:1.1.1.1
	netbsd-11-0-RC1:1.1.1.1
	netbsd-11:1.1.1.1.0.6
	netbsd-11-base:1.1.1.1
	netbsd-10-1-RELEASE:1.1.1.1
	netbsd-9-4-RELEASE:1.1.1.1
	netbsd-10-0-RELEASE:1.1.1.1
	netbsd-10-0-RC6:1.1.1.1
	netbsd-10-0-RC5:1.1.1.1
	netbsd-10-0-RC4:1.1.1.1
	netbsd-10-0-RC3:1.1.1.1
	netbsd-10-0-RC2:1.1.1.1
	netbsd-10-0-RC1:1.1.1.1
	netbsd-10:1.1.1.1.0.4
	netbsd-10-base:1.1.1.1
	netbsd-9-3-RELEASE:1.1.1.1
	netbsd-9-2-RELEASE:1.1.1.1
	netbsd-9-1-RELEASE:1.1.1.1
	netbsd-9-0-RELEASE:1.1.1.1
	netbsd-9-0-RC2:1.1.1.1
	netbsd-9-0-RC1:1.1.1.1
	netbsd-9:1.1.1.1.0.2
	netbsd-9-base:1.1.1.1
	src-current-2019-03-18:1.1.1.1
	NetBSD:1.1.1;
locks; strict;
comment	@# @;


1.1
date	2019.05.10.06.22.24;	author mrg;	state Exp;
branches
	1.1.1.1;
next	;
commitid	NVvVabT92hhUGCmB;

1.1.1.1
date	2019.05.10.06.22.24;	author mrg;	state Exp;
branches;
next	;
commitid	NVvVabT92hhUGCmB;


desc
@@



1.1
log
@Initial revision
@
text
@/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Author:
 *    Zou Nan hai <nanhai.zou@@intel.com>
 *    Zhang Hua jun <huajun.zhang@@intel.com>
 *    Xing Dong sheng <dongsheng.xing@@intel.com>
 *
 */
mov (1) g2.8<1>UD 0x007001FUD {align1};
send (16) 0 g98.0<1>UW g2<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1};

and (1) g2.24<1>UD g2.0<1,1,1>UD 3UD {align1};
mul(1) g2.24<1>UD g2.24<1,1,1>UD 49UD {align1};
add (1) g2.4<1>UD g2.4<1,1,1>UD 8UD {align1};
send (16) 0 g106.0<1>UW g2<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1};
add (1) g2.4<1>UD g2.4<1,1,1>UD 8UD {align1};
mov (1) g2.8<1>UD 0x1FUD {align1};
send (16) 0 g120.0<1>UW g2<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 1 {align1};

jmpi g2.24<1,1,1>D;

add (16) g28.0<1>UW g98.0<16,16,1>UB g98.1<16,16,1>UB {align1};
add (16) g29.0<1>UW g99.0<16,16,1>UB g99.1<16,16,1>UB {align1};
add (16) g30.0<1>UW g100.0<16,16,1>UB g100.1<16,16,1>UB {align1};
add (16) g31.0<1>UW g101.0<16,16,1>UB g101.1<16,16,1>UB {align1};
add (16) g32.0<1>UW g102.0<16,16,1>UB g102.1<16,16,1>UB {align1};
add (16) g33.0<1>UW g103.0<16,16,1>UB g103.1<16,16,1>UB {align1};
add (16) g34.0<1>UW g104.0<16,16,1>UB g104.1<16,16,1>UB {align1};
add (16) g35.0<1>UW g105.0<16,16,1>UB g105.1<16,16,1>UB {align1};
add (16) g36.0<1>UW g106.0<16,16,1>UB g106.1<16,16,1>UB {align1};
add (16) g37.0<1>UW g107.0<16,16,1>UB g107.1<16,16,1>UB {align1};
add (16) g38.0<1>UW g108.0<16,16,1>UB g108.1<16,16,1>UB {align1};
add (16) g39.0<1>UW g109.0<16,16,1>UB g109.1<16,16,1>UB {align1};
add (16) g40.0<1>UW g110.0<16,16,1>UB g110.1<16,16,1>UB {align1};
add (16) g41.0<1>UW g111.0<16,16,1>UB g111.1<16,16,1>UB {align1};
add (16) g42.0<1>UW g112.0<16,16,1>UB g112.1<16,16,1>UB {align1};
add (16) g43.0<1>UW g113.0<16,16,1>UB g113.1<16,16,1>UB {align1};

add (16) g28.0<1>UW g28.0<16,16,1>UW g99.0<16,16,1>UB {align1};
add (16) g29.0<1>UW g29.0<16,16,1>UW g100.0<16,16,1>UB {align1};
add (16) g30.0<1>UW g30.0<16,16,1>UW g101.0<16,16,1>UB {align1};
add (16) g31.0<1>UW g31.0<16,16,1>UW g102.0<16,16,1>UB {align1};
add (16) g32.0<1>UW g32.0<16,16,1>UW g103.0<16,16,1>UB {align1};
add (16) g33.0<1>UW g33.0<16,16,1>UW g104.0<16,16,1>UB {align1};
add (16) g34.0<1>UW g34.0<16,16,1>UW g105.0<16,16,1>UB {align1};
add (16) g35.0<1>UW g35.0<16,16,1>UW g106.0<16,16,1>UB {align1};
add (16) g36.0<1>UW g36.0<16,16,1>UW g107.0<16,16,1>UB {align1};
add (16) g37.0<1>UW g37.0<16,16,1>UW g108.0<16,16,1>UB {align1};
add (16) g38.0<1>UW g38.0<16,16,1>UW g109.0<16,16,1>UB {align1};
add (16) g39.0<1>UW g39.0<16,16,1>UW g110.0<16,16,1>UB {align1};
add (16) g40.0<1>UW g40.0<16,16,1>UW g111.0<16,16,1>UB {align1};
add (16) g41.0<1>UW g41.0<16,16,1>UW g112.0<16,16,1>UB {align1};
add (16) g42.0<1>UW g42.0<16,16,1>UW g113.0<16,16,1>UB {align1};
add (16) g43.0<1>UW g43.0<16,16,1>UW g120.0<16,16,1>UB {align1};

add (16) g28.0<1>UW g28.0<16,16,1>UW g99.1<16,16,1>UB {align1};
add (16) g29.0<1>UW g29.0<16,16,1>UW g100.1<16,16,1>UB {align1};
add (16) g30.0<1>UW g30.0<16,16,1>UW g101.1<16,16,1>UB {align1};
add (16) g31.0<1>UW g31.0<16,16,1>UW g102.1<16,16,1>UB {align1};
add (16) g32.0<1>UW g32.0<16,16,1>UW g103.1<16,16,1>UB {align1};
add (16) g33.0<1>UW g33.0<16,16,1>UW g104.1<16,16,1>UB {align1};
add (16) g34.0<1>UW g34.0<16,16,1>UW g105.1<16,16,1>UB {align1};
add (16) g35.0<1>UW g35.0<16,16,1>UW g106.1<16,16,1>UB {align1};
add (16) g36.0<1>UW g36.0<16,16,1>UW g107.1<16,16,1>UB {align1};
add (16) g37.0<1>UW g37.0<16,16,1>UW g108.1<16,16,1>UB {align1};
add (16) g38.0<1>UW g38.0<16,16,1>UW g109.1<16,16,1>UB {align1};
add (16) g39.0<1>UW g39.0<16,16,1>UW g110.1<16,16,1>UB {align1};
add (16) g40.0<1>UW g40.0<16,16,1>UW g111.1<16,16,1>UB {align1};
add (16) g41.0<1>UW g41.0<16,16,1>UW g112.1<16,16,1>UB {align1};
add (16) g42.0<1>UW g42.0<16,16,1>UW g113.1<16,16,1>UB {align1};
add (16) g43.0<1>UW g43.0<16,16,1>UW g120.1<16,16,1>UB {align1};
jmpi out;

add (16) g28.0<1>UW g98.1<16,16,1>UB g98.2<16,16,1>UB {align1};
add (16) g29.0<1>UW g99.1<16,16,1>UB g99.2<16,16,1>UB {align1};
add (16) g30.0<1>UW g100.1<16,16,1>UB g100.2<16,16,1>UB {align1};
add (16) g31.0<1>UW g101.1<16,16,1>UB g101.2<16,16,1>UB {align1};
add (16) g32.0<1>UW g102.1<16,16,1>UB g102.2<16,16,1>UB {align1};
add (16) g33.0<1>UW g103.1<16,16,1>UB g103.2<16,16,1>UB {align1};
add (16) g34.0<1>UW g104.1<16,16,1>UB g104.2<16,16,1>UB {align1};
add (16) g35.0<1>UW g105.1<16,16,1>UB g105.2<16,16,1>UB {align1};
add (16) g36.0<1>UW g106.1<16,16,1>UB g106.2<16,16,1>UB {align1};
add (16) g37.0<1>UW g107.1<16,16,1>UB g107.2<16,16,1>UB {align1};
add (16) g38.0<1>UW g108.1<16,16,1>UB g108.2<16,16,1>UB {align1};
add (16) g39.0<1>UW g109.1<16,16,1>UB g109.2<16,16,1>UB {align1};
add (16) g40.0<1>UW g110.1<16,16,1>UB g110.2<16,16,1>UB {align1};
add (16) g41.0<1>UW g111.1<16,16,1>UB g111.2<16,16,1>UB {align1};
add (16) g42.0<1>UW g112.1<16,16,1>UB g112.2<16,16,1>UB {align1};
add (16) g43.0<1>UW g113.1<16,16,1>UB g113.2<16,16,1>UB {align1};

add (16) g28.0<1>UW g28.0<16,16,1>UW g99.1<16,16,1>UB {align1};
add (16) g29.0<1>UW g29.0<16,16,1>UW g100.1<16,16,1>UB {align1};
add (16) g30.0<1>UW g30.0<16,16,1>UW g101.1<16,16,1>UB {align1};
add (16) g31.0<1>UW g31.0<16,16,1>UW g102.1<16,16,1>UB {align1};
add (16) g32.0<1>UW g32.0<16,16,1>UW g103.1<16,16,1>UB {align1};
add (16) g33.0<1>UW g33.0<16,16,1>UW g104.1<16,16,1>UB {align1};
add (16) g34.0<1>UW g34.0<16,16,1>UW g105.1<16,16,1>UB {align1};
add (16) g35.0<1>UW g35.0<16,16,1>UW g106.1<16,16,1>UB {align1};
add (16) g36.0<1>UW g36.0<16,16,1>UW g107.1<16,16,1>UB {align1};
add (16) g37.0<1>UW g37.0<16,16,1>UW g108.1<16,16,1>UB {align1};
add (16) g38.0<1>UW g38.0<16,16,1>UW g109.1<16,16,1>UB {align1};
add (16) g39.0<1>UW g39.0<16,16,1>UW g110.1<16,16,1>UB {align1};
add (16) g40.0<1>UW g40.0<16,16,1>UW g111.1<16,16,1>UB {align1};
add (16) g41.0<1>UW g41.0<16,16,1>UW g112.1<16,16,1>UB {align1};
add (16) g42.0<1>UW g42.0<16,16,1>UW g113.1<16,16,1>UB {align1};
add (16) g43.0<1>UW g43.0<16,16,1>UW g120.1<16,16,1>UB {align1};

add (16) g28.0<1>UW g28.0<16,16,1>UW g99.2<16,16,1>UB {align1};
add (16) g29.0<1>UW g29.0<16,16,1>UW g100.2<16,16,1>UB {align1};
add (16) g30.0<1>UW g30.0<16,16,1>UW g101.2<16,16,1>UB {align1};
add (16) g31.0<1>UW g31.0<16,16,1>UW g102.2<16,16,1>UB {align1};
add (16) g32.0<1>UW g32.0<16,16,1>UW g103.2<16,16,1>UB {align1};
add (16) g33.0<1>UW g33.0<16,16,1>UW g104.2<16,16,1>UB {align1};
add (16) g34.0<1>UW g34.0<16,16,1>UW g105.2<16,16,1>UB {align1};
add (16) g35.0<1>UW g35.0<16,16,1>UW g106.2<16,16,1>UB {align1};
add (16) g36.0<1>UW g36.0<16,16,1>UW g107.2<16,16,1>UB {align1};
add (16) g37.0<1>UW g37.0<16,16,1>UW g108.2<16,16,1>UB {align1};
add (16) g38.0<1>UW g38.0<16,16,1>UW g109.2<16,16,1>UB {align1};
add (16) g39.0<1>UW g39.0<16,16,1>UW g110.2<16,16,1>UB {align1};
add (16) g40.0<1>UW g40.0<16,16,1>UW g111.2<16,16,1>UB {align1};
add (16) g41.0<1>UW g41.0<16,16,1>UW g112.2<16,16,1>UB {align1};
add (16) g42.0<1>UW g42.0<16,16,1>UW g113.2<16,16,1>UB {align1};
add (16) g43.0<1>UW g43.0<16,16,1>UW g120.2<16,16,1>UB {align1};
jmpi out;

add (16) g28.0<1>UW g98.2<16,16,1>UB g98.3<16,16,1>UB {align1};
add (16) g29.0<1>UW g99.2<16,16,1>UB g99.3<16,16,1>UB {align1};
add (16) g30.0<1>UW g100.2<16,16,1>UB g100.3<16,16,1>UB {align1};
add (16) g31.0<1>UW g101.2<16,16,1>UB g101.3<16,16,1>UB {align1};
add (16) g32.0<1>UW g102.2<16,16,1>UB g102.3<16,16,1>UB {align1};
add (16) g33.0<1>UW g103.2<16,16,1>UB g103.3<16,16,1>UB {align1};
add (16) g34.0<1>UW g104.2<16,16,1>UB g104.3<16,16,1>UB {align1};
add (16) g35.0<1>UW g105.2<16,16,1>UB g105.3<16,16,1>UB {align1};
add (16) g36.0<1>UW g106.2<16,16,1>UB g106.3<16,16,1>UB {align1};
add (16) g37.0<1>UW g107.2<16,16,1>UB g107.3<16,16,1>UB {align1};
add (16) g38.0<1>UW g108.2<16,16,1>UB g108.3<16,16,1>UB {align1};
add (16) g39.0<1>UW g109.2<16,16,1>UB g109.3<16,16,1>UB {align1};
add (16) g40.0<1>UW g110.2<16,16,1>UB g110.3<16,16,1>UB {align1};
add (16) g41.0<1>UW g111.2<16,16,1>UB g111.3<16,16,1>UB {align1};
add (16) g42.0<1>UW g112.2<16,16,1>UB g112.3<16,16,1>UB {align1};
add (16) g43.0<1>UW g113.2<16,16,1>UB g113.3<16,16,1>UB {align1};

add (16) g28.0<1>UW g28.0<16,16,1>UW g99.2<16,16,1>UB {align1};
add (16) g29.0<1>UW g29.0<16,16,1>UW g100.2<16,16,1>UB {align1};
add (16) g30.0<1>UW g30.0<16,16,1>UW g101.2<16,16,1>UB {align1};
add (16) g31.0<1>UW g31.0<16,16,1>UW g102.2<16,16,1>UB {align1};
add (16) g32.0<1>UW g32.0<16,16,1>UW g103.2<16,16,1>UB {align1};
add (16) g33.0<1>UW g33.0<16,16,1>UW g104.2<16,16,1>UB {align1};
add (16) g34.0<1>UW g34.0<16,16,1>UW g105.2<16,16,1>UB {align1};
add (16) g35.0<1>UW g35.0<16,16,1>UW g106.2<16,16,1>UB {align1};
add (16) g36.0<1>UW g36.0<16,16,1>UW g107.2<16,16,1>UB {align1};
add (16) g37.0<1>UW g37.0<16,16,1>UW g108.2<16,16,1>UB {align1};
add (16) g38.0<1>UW g38.0<16,16,1>UW g109.2<16,16,1>UB {align1};
add (16) g39.0<1>UW g39.0<16,16,1>UW g110.2<16,16,1>UB {align1};
add (16) g40.0<1>UW g40.0<16,16,1>UW g111.2<16,16,1>UB {align1};
add (16) g41.0<1>UW g41.0<16,16,1>UW g112.2<16,16,1>UB {align1};
add (16) g42.0<1>UW g42.0<16,16,1>UW g113.2<16,16,1>UB {align1};
add (16) g43.0<1>UW g43.0<16,16,1>UW g120.2<16,16,1>UB {align1};

add (16) g28.0<1>UW g28.0<16,16,1>UW g99.3<16,16,1>UB {align1};
add (16) g29.0<1>UW g29.0<16,16,1>UW g100.3<16,16,1>UB {align1};
add (16) g30.0<1>UW g30.0<16,16,1>UW g101.3<16,16,1>UB {align1};
add (16) g31.0<1>UW g31.0<16,16,1>UW g102.3<16,16,1>UB {align1};
add (16) g32.0<1>UW g32.0<16,16,1>UW g103.3<16,16,1>UB {align1};
add (16) g33.0<1>UW g33.0<16,16,1>UW g104.3<16,16,1>UB {align1};
add (16) g34.0<1>UW g34.0<16,16,1>UW g105.3<16,16,1>UB {align1};
add (16) g35.0<1>UW g35.0<16,16,1>UW g106.3<16,16,1>UB {align1};
add (16) g36.0<1>UW g36.0<16,16,1>UW g107.3<16,16,1>UB {align1};
add (16) g37.0<1>UW g37.0<16,16,1>UW g108.3<16,16,1>UB {align1};
add (16) g38.0<1>UW g38.0<16,16,1>UW g109.3<16,16,1>UB {align1};
add (16) g39.0<1>UW g39.0<16,16,1>UW g110.3<16,16,1>UB {align1};
add (16) g40.0<1>UW g40.0<16,16,1>UW g111.3<16,16,1>UB {align1};
add (16) g41.0<1>UW g41.0<16,16,1>UW g112.3<16,16,1>UB {align1};
add (16) g42.0<1>UW g42.0<16,16,1>UW g113.3<16,16,1>UB {align1};
add (16) g43.0<1>UW g43.0<16,16,1>UW g120.3<16,16,1>UB {align1};
jmpi out;
add (16) g28.0<1>UW g98.3<16,16,1>UB g98.4<16,16,1>UB {align1};
add (16) g29.0<1>UW g99.3<16,16,1>UB g99.4<16,16,1>UB {align1};
add (16) g30.0<1>UW g100.3<16,16,1>UB g100.4<16,16,1>UB {align1};
add (16) g31.0<1>UW g101.3<16,16,1>UB g101.4<16,16,1>UB {align1};
add (16) g32.0<1>UW g102.3<16,16,1>UB g102.4<16,16,1>UB {align1};
add (16) g33.0<1>UW g103.3<16,16,1>UB g103.4<16,16,1>UB {align1};
add (16) g34.0<1>UW g104.3<16,16,1>UB g104.4<16,16,1>UB {align1};
add (16) g35.0<1>UW g105.3<16,16,1>UB g105.4<16,16,1>UB {align1};
add (16) g36.0<1>UW g106.3<16,16,1>UB g106.4<16,16,1>UB {align1};
add (16) g37.0<1>UW g107.3<16,16,1>UB g107.4<16,16,1>UB {align1};
add (16) g38.0<1>UW g108.3<16,16,1>UB g108.4<16,16,1>UB {align1};
add (16) g39.0<1>UW g109.3<16,16,1>UB g109.4<16,16,1>UB {align1};
add (16) g40.0<1>UW g110.3<16,16,1>UB g110.4<16,16,1>UB {align1};
add (16) g41.0<1>UW g111.3<16,16,1>UB g111.4<16,16,1>UB {align1};
add (16) g42.0<1>UW g112.3<16,16,1>UB g112.4<16,16,1>UB {align1};
add (16) g43.0<1>UW g113.3<16,16,1>UB g113.4<16,16,1>UB {align1};

add (16) g28.0<1>UW g28.0<16,16,1>UW g99.3<16,16,1>UB {align1};
add (16) g29.0<1>UW g29.0<16,16,1>UW g100.3<16,16,1>UB {align1};
add (16) g30.0<1>UW g30.0<16,16,1>UW g101.3<16,16,1>UB {align1};
add (16) g31.0<1>UW g31.0<16,16,1>UW g102.3<16,16,1>UB {align1};
add (16) g32.0<1>UW g32.0<16,16,1>UW g103.3<16,16,1>UB {align1};
add (16) g33.0<1>UW g33.0<16,16,1>UW g104.3<16,16,1>UB {align1};
add (16) g34.0<1>UW g34.0<16,16,1>UW g105.3<16,16,1>UB {align1};
add (16) g35.0<1>UW g35.0<16,16,1>UW g106.3<16,16,1>UB {align1};
add (16) g36.0<1>UW g36.0<16,16,1>UW g107.3<16,16,1>UB {align1};
add (16) g37.0<1>UW g37.0<16,16,1>UW g108.3<16,16,1>UB {align1};
add (16) g38.0<1>UW g38.0<16,16,1>UW g109.3<16,16,1>UB {align1};
add (16) g39.0<1>UW g39.0<16,16,1>UW g110.3<16,16,1>UB {align1};
add (16) g40.0<1>UW g40.0<16,16,1>UW g111.3<16,16,1>UB {align1};
add (16) g41.0<1>UW g41.0<16,16,1>UW g112.3<16,16,1>UB {align1};
add (16) g42.0<1>UW g42.0<16,16,1>UW g113.3<16,16,1>UB {align1};
add (16) g43.0<1>UW g43.0<16,16,1>UW g120.3<16,16,1>UB {align1};

add (16) g28.0<1>UW g28.0<16,16,1>UW g99.4<16,16,1>UB {align1};
add (16) g29.0<1>UW g29.0<16,16,1>UW g100.4<16,16,1>UB {align1};
add (16) g30.0<1>UW g30.0<16,16,1>UW g101.4<16,16,1>UB {align1};
add (16) g31.0<1>UW g31.0<16,16,1>UW g102.4<16,16,1>UB {align1};
add (16) g32.0<1>UW g32.0<16,16,1>UW g103.4<16,16,1>UB {align1};
add (16) g33.0<1>UW g33.0<16,16,1>UW g104.4<16,16,1>UB {align1};
add (16) g34.0<1>UW g34.0<16,16,1>UW g105.4<16,16,1>UB {align1};
add (16) g35.0<1>UW g35.0<16,16,1>UW g106.4<16,16,1>UB {align1};
add (16) g36.0<1>UW g36.0<16,16,1>UW g107.4<16,16,1>UB {align1};
add (16) g37.0<1>UW g37.0<16,16,1>UW g108.4<16,16,1>UB {align1};
add (16) g38.0<1>UW g38.0<16,16,1>UW g109.4<16,16,1>UB {align1};
add (16) g39.0<1>UW g39.0<16,16,1>UW g110.4<16,16,1>UB {align1};
add (16) g40.0<1>UW g40.0<16,16,1>UW g111.4<16,16,1>UB {align1};
add (16) g41.0<1>UW g41.0<16,16,1>UW g112.4<16,16,1>UB {align1};
add (16) g42.0<1>UW g42.0<16,16,1>UW g113.4<16,16,1>UB {align1};
add (16) g43.0<1>UW g43.0<16,16,1>UW g120.4<16,16,1>UB {align1};

out:
shr.sat (16) g28.0<1>UW g28.0<16,16,1>UW 2UW {align1};
shr.sat (16) g29.0<1>UW g29.0<16,16,1>UW 2UW {align1};
shr.sat (16) g30.0<1>UW g30.0<16,16,1>UW 2UW {align1};
shr.sat (16) g31.0<1>UW g31.0<16,16,1>UW 2UW {align1};
shr.sat (16) g32.0<1>UW g32.0<16,16,1>UW 2UW {align1};
shr.sat (16) g33.0<1>UW g33.0<16,16,1>UW 2UW {align1};
shr.sat (16) g34.0<1>UW g34.0<16,16,1>UW 2UW {align1};
shr.sat (16) g35.0<1>UW g35.0<16,16,1>UW 2UW {align1};
shr.sat (16) g36.0<1>UW g36.0<16,16,1>UW 2UW {align1};
shr.sat (16) g37.0<1>UW g37.0<16,16,1>UW 2UW {align1};
shr.sat (16) g38.0<1>UW g38.0<16,16,1>UW 2UW {align1};
shr.sat (16) g39.0<1>UW g39.0<16,16,1>UW 2UW {align1};
shr.sat (16) g40.0<1>UW g40.0<16,16,1>UW 2UW {align1};
shr.sat (16) g41.0<1>UW g41.0<16,16,1>UW 2UW {align1};
shr.sat (16) g42.0<1>UW g42.0<16,16,1>UW 2UW {align1};
shr.sat (16) g43.0<1>UW g43.0<16,16,1>UW 2UW {align1};
@


1.1.1.1
log
@import our slightly older intel xf86 driver as "intel-2014".
this driver works better on older systems, but doesn't support
gen9 as well.
@
text
@@
