head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC5:1.1.1.2 netbsd-11-0-RC4:1.1.1.2 netbsd-11-0-RC3:1.1.1.2 netbsd-11-0-RC2:1.1.1.2 netbsd-11-0-RC1:1.1.1.2 netbsd-11:1.1.1.2.0.4 netbsd-11-base:1.1.1.2 netbsd-10-1-RELEASE:1.1.1.2 netbsd-10-0-RELEASE:1.1.1.2 netbsd-10-0-RC6:1.1.1.2 netbsd-10-0-RC5:1.1.1.2 netbsd-10-0-RC4:1.1.1.2 netbsd-10-0-RC3:1.1.1.2 netbsd-10-0-RC2:1.1.1.2 netbsd-10-0-RC1:1.1.1.2 netbsd-10:1.1.1.2.0.2 netbsd-10-base:1.1.1.2 mesa-21-3-7:1.1.1.2 mesalib-19-1-7:1.1.1.1 xorg:1.1.1; locks; strict; comment @// @; 1.1 date 2019.09.24.16.46.36; author maya; state Exp; branches 1.1.1.1; next ; commitid KJXusGl8fi9AAhEB; 1.1.1.1 date 2019.09.24.16.46.36; author maya; state Exp; branches; next 1.1.1.2; commitid KJXusGl8fi9AAhEB; 1.1.1.2 date 2022.05.09.01.23.28; author mrg; state Exp; branches; next ; commitid UEBs6hNk81DdQjDD; desc @@ 1.1 log @Initial revision @ text @/* * Copyright © 2019 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include #include "nir.h" #include "nir_builder.h" class comparison_pre_test : public ::testing::Test { protected: comparison_pre_test() { static const nir_shader_compiler_options options = { }; nir_builder_init_simple_shader(&bld, NULL, MESA_SHADER_VERTEX, &options); v1 = nir_imm_vec4(&bld, -2.0, -1.0, 1.0, 2.0); v2 = nir_imm_vec4(&bld, 2.0, 1.0, -1.0, -2.0); v3 = nir_imm_vec4(&bld, 3.0, 4.0, 5.0, 6.0); } ~comparison_pre_test() { ralloc_free(bld.shader); } struct nir_builder bld; nir_ssa_def *v1; nir_ssa_def *v2; nir_ssa_def *v3; const uint8_t xxxx[4] = { 0, 0, 0, 0 }; const uint8_t wwww[4] = { 3, 3, 3, 3 }; }; TEST_F(comparison_pre_test, a_lt_b_vs_neg_a_plus_b) { /* Before: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec4 32 ssa_4 = fadd ssa_0, ssa_2 * vec1 32 ssa_5 = mov ssa_4.x * vec1 1 ssa_6 = flt ssa_5, ssa_3 * * if ssa_6 { * vec1 32 ssa_7 = fneg ssa_5 * vec1 32 ssa_8 = fadd ssa_7, ssa_3 * } else { * } * * After: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec4 32 ssa_4 = fadd ssa_0, ssa_2 * vec1 32 ssa_5 = mov ssa_4.x * vec1 32 ssa_9 = fneg ssa_5 * vec1 32 ssa_10 = fadd ssa_3, ssa_9 * vec1 32 ssa_11 = load_const (0.0) * vec1 1 ssa_12 = flt ssa_11, ssa_10 * vec1 32 ssa_13 = mov ssa_10 * vec1 1 ssa_14 = mov ssa_12 * * if ssa_14 { * vec1 32 ssa_7 = fneg ssa_5 * } else { * } */ nir_ssa_def *one = nir_imm_float(&bld, 1.0f); nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0); nir_ssa_def *flt = nir_flt(&bld, a, one); nir_if *nif = nir_push_if(&bld, flt); nir_fadd(&bld, nir_fneg(&bld, a), one); nir_pop_if(&bld, nif); EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl)); } TEST_F(comparison_pre_test, a_lt_b_vs_a_minus_b) { /* Before: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec4 32 ssa_4 = fadd ssa_0, ssa_2 * vec1 32 ssa_5 = mov ssa_4.x * vec1 1 ssa_6 = flt ssa_3, ssa_5 * * if ssa_6 { * vec1 32 ssa_7 = fneg ssa_5 * vec1 32 ssa_8 = fadd ssa_3, ssa_7 * } else { * } * * After: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec4 32 ssa_4 = fadd ssa_0, ssa_2 * vec1 32 ssa_5 = mov ssa_4.x * vec1 32 ssa_9 = fneg ssa_5 * vec1 32 ssa_10 = fadd ssa_3, ssa_9 * vec1 32 ssa_11 = load_const (0.0) * vec1 1 ssa_12 = flt ssa_10, ssa_11 * vec1 32 ssa_13 = mov ssa_10 * vec1 1 ssa_14 = mov ssa_12 * * if ssa_14 { * vec1 32 ssa_7 = fneg ssa_5 * } else { * } */ nir_ssa_def *one = nir_imm_float(&bld, 1.0f); nir_ssa_def *b = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0); nir_ssa_def *flt = nir_flt(&bld, one, b); nir_if *nif = nir_push_if(&bld, flt); nir_fadd(&bld, one, nir_fneg(&bld, b)); nir_pop_if(&bld, nif); EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl)); } TEST_F(comparison_pre_test, neg_a_lt_b_vs_a_plus_b) { /* Before: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec4 32 ssa_4 = fadd ssa_0, ssa_2 * vec1 32 ssa_5 = mov ssa_4.x * vec1 32 ssa_6 = fneg ssa_5 * vec1 1 ssa_7 = flt ssa_6, ssa_3 * * if ssa_7 { * vec1 32 ssa_8 = fadd ssa_5, ssa_3 * } else { * } * * After: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec4 32 ssa_4 = fadd ssa_0, ssa_2 * vec1 32 ssa_5 = mov ssa_4.x * vec1 32 ssa_9 = fneg ssa_5 * vec1 32 ssa_9 = fneg ssa_6 * vec1 32 ssa_10 = fadd ssa_3, ssa_9 * vec1 32 ssa_11 = load_const ( 0.0) * vec1 1 ssa_12 = flt ssa_11, ssa_10 * vec1 32 ssa_13 = mov ssa_10 * vec1 1 ssa_14 = mov ssa_12 * * if ssa_14 { * } else { * } */ nir_ssa_def *one = nir_imm_float(&bld, 1.0f); nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0); nir_ssa_def *flt = nir_flt(&bld, nir_fneg(&bld, a), one); nir_if *nif = nir_push_if(&bld, flt); nir_fadd(&bld, a, one); nir_pop_if(&bld, nif); EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl)); } TEST_F(comparison_pre_test, a_lt_neg_b_vs_a_plus_b) { /* Before: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec4 32 ssa_4 = fadd ssa_0, ssa_2 * vec1 32 ssa_5 = mov ssa_4.x * vec1 32 ssa_6 = fneg ssa_5 * vec1 1 ssa_7 = flt ssa_3, ssa_6 * * if ssa_7 { * vec1 32 ssa_8 = fadd ssa_3, ssa_5 * } else { * } * * After: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec4 32 ssa_4 = fadd ssa_0, ssa_2 * vec1 32 ssa_5 = mov ssa_4.x * vec1 32 ssa_9 = fneg ssa_5 * vec1 32 ssa_9 = fneg ssa_6 * vec1 32 ssa_10 = fadd ssa_3, ssa_9 * vec1 32 ssa_11 = load_const ( 0.0) * vec1 1 ssa_12 = flt ssa_10, ssa_11 * vec1 32 ssa_13 = mov ssa_10 * vec1 1 ssa_14 = mov ssa_12 * * if ssa_14 { * } else { * } */ nir_ssa_def *one = nir_imm_float(&bld, 1.0f); nir_ssa_def *b = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0); nir_ssa_def *flt = nir_flt(&bld, one, nir_fneg(&bld, b)); nir_if *nif = nir_push_if(&bld, flt); nir_fadd(&bld, one, b); nir_pop_if(&bld, nif); EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl)); } TEST_F(comparison_pre_test, imm_lt_b_vs_neg_imm_plus_b) { /* Before: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec1 32 ssa_4 = load_const (-1.0) * vec4 32 ssa_5 = fadd ssa_0, ssa_2 * vec1 32 ssa_6 = mov ssa_5.x * vec1 1 ssa_7 = flt ssa_3, ssa_6 * * if ssa_7 { * vec1 32 ssa_8 = fadd ssa_4, ssa_6 * } else { * } * * After: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec1 32 ssa_4 = load_const (-1.0) * vec4 32 ssa_5 = fadd ssa_0, ssa_2 * vec1 32 ssa_6 = mov ssa_5.x * vec1 32 ssa_9 = fneg ssa_3 * vec1 32 ssa_10 = fadd ssa_6, ssa_9 * vec1 32 ssa_11 = load_const ( 0.0) * vec1 1 ssa_12 = flt ssa_11, ssa_10 * vec1 32 ssa_13 = mov ssa_10 * vec1 1 ssa_14 = mov ssa_12 * * if ssa_14 { * } else { * } */ nir_ssa_def *one = nir_imm_float(&bld, 1.0f); nir_ssa_def *neg_one = nir_imm_float(&bld, -1.0f); nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0); nir_ssa_def *flt = nir_flt(&bld, one, a); nir_if *nif = nir_push_if(&bld, flt); nir_fadd(&bld, neg_one, a); nir_pop_if(&bld, nif); EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl)); } TEST_F(comparison_pre_test, a_lt_imm_vs_a_minus_imm) { /* Before: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec1 32 ssa_4 = load_const (-1.0) * vec4 32 ssa_5 = fadd ssa_0, ssa_2 * vec1 32 ssa_6 = mov ssa_5.x * vec1 1 ssa_7 = flt ssa_6, ssa_3 * * if ssa_6 { * vec1 32 ssa_8 = fadd ssa_6, ssa_4 * } else { * } * * After: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec1 32 ssa_4 = load_const (-1.0) * vec4 32 ssa_5 = fadd ssa_0, ssa_2 * vec1 32 ssa_6 = mov ssa_5.x * vec1 32 ssa_9 = fneg ssa_3 * vec1 32 ssa_10 = fadd ssa_6, ssa_9 * vec1 32 ssa_11 = load_const ( 0.0) * vec1 1 ssa_12 = flt ssa_10, ssa_11 * vec1 32 ssa_13 = mov ssa_10 * vec1 1 ssa_14 = mov ssa_12 * * if ssa_14 { * } else { * } */ nir_ssa_def *one = nir_imm_float(&bld, 1.0f); nir_ssa_def *neg_one = nir_imm_float(&bld, -1.0f); nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0); nir_ssa_def *flt = nir_flt(&bld, a, one); nir_if *nif = nir_push_if(&bld, flt); nir_fadd(&bld, a, neg_one); nir_pop_if(&bld, nif); EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl)); } TEST_F(comparison_pre_test, neg_imm_lt_a_vs_a_plus_imm) { /* Before: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec1 32 ssa_4 = load_const (-1.0) * vec4 32 ssa_5 = fadd ssa_0, ssa_2 * vec1 32 ssa_6 = mov ssa_5.x * vec1 1 ssa_7 = flt ssa_4, ssa_6 * * if ssa_7 { * vec1 32 ssa_8 = fadd ssa_6, ssa_3 * } else { * } * * After: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec1 32 ssa_4 = load_const (-1.0) * vec4 32 ssa_5 = fadd ssa_0, ssa_2 * vec1 32 ssa_6 = mov ssa_5.x * vec1 32 ssa_9 = fneg ssa_4 * vec1 32 ssa_10 = fadd ssa_6, ssa_9 * vec1 32 ssa_11 = load_const ( 0.0) * vec1 1 ssa_12 = flt ssa_11, ssa_10 * vec1 32 ssa_13 = mov ssa_10 * vec1 1 ssa_14 = mov ssa_12 * * if ssa_14 { * } else { * } */ nir_ssa_def *one = nir_imm_float(&bld, 1.0f); nir_ssa_def *neg_one = nir_imm_float(&bld, -1.0f); nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0); nir_ssa_def *flt = nir_flt(&bld, neg_one, a); nir_if *nif = nir_push_if(&bld, flt); nir_fadd(&bld, a, one); nir_pop_if(&bld, nif); EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl)); } TEST_F(comparison_pre_test, a_lt_neg_imm_vs_a_plus_imm) { /* Before: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec1 32 ssa_4 = load_const (-1.0) * vec4 32 ssa_5 = fadd ssa_0, ssa_2 * vec1 32 ssa_6 = mov ssa_5.x * vec1 1 ssa_7 = flt ssa_6, ssa_4 * * if ssa_7 { * vec1 32 ssa_8 = fadd ssa_6, ssa_3 * } else { * } * * After: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec1 32 ssa_3 = load_const ( 1.0) * vec1 32 ssa_4 = load_const (-1.0) * vec4 32 ssa_5 = fadd ssa_0, ssa_2 * vec1 32 ssa_6 = mov ssa_5.x * vec1 32 ssa_9 = fneg ssa_4 * vec1 32 ssa_10 = fadd ssa_6, ssa_9 * vec1 32 ssa_11 = load_const ( 0.0) * vec1 1 ssa_12 = flt ssa_10, ssa_11 * vec1 32 ssa_13 = mov ssa_10 * vec1 1 ssa_14 = mov ssa_12 * * if ssa_14 { * } else { * } */ nir_ssa_def *one = nir_imm_float(&bld, 1.0f); nir_ssa_def *neg_one = nir_imm_float(&bld, -1.0f); nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0); nir_ssa_def *flt = nir_flt(&bld, a, neg_one); nir_if *nif = nir_push_if(&bld, flt); nir_fadd(&bld, a, one); nir_pop_if(&bld, nif); EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl)); } TEST_F(comparison_pre_test, non_scalar_add_result) { /* The optimization pass should not do anything because the result of the * fadd is not a scalar. * * Before: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec4 32 ssa_3 = fadd ssa_0, ssa_2 * vec1 1 ssa_4 = flt ssa_0.x, ssa_3.x * * if ssa_4 { * vec2 32 ssa_5 = fadd ssa_1.xx, ssa_3.xx * } else { * } * * After: * * No change. */ nir_ssa_def *a = nir_fadd(&bld, v1, v3); nir_alu_instr *flt = nir_alu_instr_create(bld.shader, nir_op_flt); flt->src[0].src = nir_src_for_ssa(v1); flt->src[1].src = nir_src_for_ssa(a); memcpy(&flt->src[0].swizzle, xxxx, sizeof(xxxx)); memcpy(&flt->src[1].swizzle, xxxx, sizeof(xxxx)); nir_builder_alu_instr_finish_and_insert(&bld, flt); flt->dest.dest.ssa.num_components = 1; flt->dest.write_mask = 1; nir_if *nif = nir_push_if(&bld, &flt->dest.dest.ssa); nir_alu_instr *fadd = nir_alu_instr_create(bld.shader, nir_op_fadd); fadd->src[0].src = nir_src_for_ssa(v2); fadd->src[1].src = nir_src_for_ssa(a); memcpy(&fadd->src[0].swizzle, xxxx, sizeof(xxxx)); memcpy(&fadd->src[1].swizzle, xxxx, sizeof(xxxx)); nir_builder_alu_instr_finish_and_insert(&bld, fadd); fadd->dest.dest.ssa.num_components = 2; fadd->dest.write_mask = 3; nir_pop_if(&bld, nif); EXPECT_FALSE(nir_opt_comparison_pre_impl(bld.impl)); } @ 1.1.1.1 log @Import mesa 19.1.7 New features in mesa 19.1.0: GL_ARB_parallel_shader_compile on all drivers. GL_EXT_gpu_shader4 on all GL 3.1 drivers. GL_EXT_shader_image_load_formatted on radeonsi. GL_EXT_texture_buffer_object on all GL 3.1 drivers. GL_EXT_texture_compression_s3tc_srgb on Gallium drivers and i965 (ES extension). GL_NV_compute_shader_derivatives on iris and i965. GL_KHR_parallel_shader_compile on all drivers. VK_EXT_buffer_device_address on Intel and RADV. VK_EXT_depth_clip_enable on Intel and RADV. VK_KHR_ycbcr_image_arrays on Intel. VK_EXT_inline_uniform_block on Intel and RADV. VK_EXT_external_memory_host on Intel. VK_EXT_host_query_reset on Intel and RADV. VK_KHR_surface_protected_capabilities on Intel and RADV. VK_EXT_pipeline_creation_feedback on Intel and RADV. VK_KHR_8bit_storage on RADV. VK_AMD_gpu_shader_int16 on RADV. VK_AMD_gpu_shader_half_float on RADV. VK_NV_compute_shader_derivatives on Intel. VK_KHR_shader_float16_int8 on Intel and RADV (RADV only supports int8). VK_KHR_shader_atomic_int64 on Intel. VK_EXT_descriptor_indexing on Intel. VK_KHR_shader_float16_int8 on Intel and RADV. GL_INTEL_conservative_rasterization on iris. VK_EXT_memory_budget on Intel. New features in mesa 19.0.0: GL_AMD_texture_texture4 on all GL 4.0 drivers. GL_EXT_shader_implicit_conversions on all drivers (ES extension). GL_EXT_texture_compression_bptc on all GL 4.0 drivers (ES extension). GL_EXT_texture_compression_rgtc on all GL 3.0 drivers (ES extension). GL_EXT_render_snorm on gallium drivers (ES extension). GL_EXT_texture_view on drivers supporting texture views (ES extension). GL_OES_texture_view on drivers supporting texture views (ES extension). GL_NV_shader_atomic_float on nvc0 (Fermi/Kepler only). Shader-based software implementations of GL_ARB_gpu_shader_fp64, GL_ARB_gpu_shader_int64, GL_ARB_vertex_attrib_64bit, and GL_ARB_shader_ballot on i965. VK_ANDROID_external_memory_android_hardware_buffer on Intel Fixed and re-exposed VK_EXT_pci_bus_info on Intel and RADV VK_EXT_scalar_block_layout on Intel and RADV VK_KHR_depth_stencil_resolve on Intel VK_KHR_draw_indirect_count on Intel VK_EXT_conditional_rendering on Intel VK_EXT_memory_budget on RADV Also, bug fixes. @ text @@ 1.1.1.2 log @initial import of mesa 21.3.7 main changes since 19.1.7 include: - more support for Vulkan functions - better supported for newer radeonsi (both amdgpu and radeon backends) - various bug fixes in many drivers - many fixes and enhancements for intel drivers - some fixes for nvidia - OpenGL 4.6 for some drivers (intel, radeonsi) - intel Tigerlake and Rocketlake support - Vulkan 1.2 for some drivers - OpenGL 4.5, GLES 3.2, and more on llvmpipe - working Panfrost and Midgard drivers - fix warnings in radeonsi vs newer llvm @ text @a30 2 glsl_type_singleton_init_or_ref(); d32 1 a32 2 bld = nir_builder_init_simple_shader(MESA_SHADER_VERTEX, &options, "comparison test"); a41 1 glsl_type_singleton_decref(); a475 50 TEST_F(comparison_pre_test, swizzle_of_same_immediate_vector) { /* Before: * * vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0) * vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0) * vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0) * vec4 32 ssa_3 = fadd ssa_0, ssa_2 * vec1 1 ssa_4 = flt ssa_0.x, ssa_3.x * * if ssa_4 { * vec1 32 ssa_5 = fadd ssa_0.w, ssa_3.x * } else { * } */ nir_ssa_def *a = nir_fadd(&bld, v1, v3); nir_alu_instr *flt = nir_alu_instr_create(bld.shader, nir_op_flt); flt->src[0].src = nir_src_for_ssa(v1); flt->src[1].src = nir_src_for_ssa(a); memcpy(&flt->src[0].swizzle, xxxx, sizeof(xxxx)); memcpy(&flt->src[1].swizzle, xxxx, sizeof(xxxx)); nir_builder_alu_instr_finish_and_insert(&bld, flt); flt->dest.dest.ssa.num_components = 1; flt->dest.write_mask = 1; nir_if *nif = nir_push_if(&bld, &flt->dest.dest.ssa); nir_alu_instr *fadd = nir_alu_instr_create(bld.shader, nir_op_fadd); fadd->src[0].src = nir_src_for_ssa(v1); fadd->src[1].src = nir_src_for_ssa(a); memcpy(&fadd->src[0].swizzle, wwww, sizeof(wwww)); memcpy(&fadd->src[1].swizzle, xxxx, sizeof(xxxx)); nir_builder_alu_instr_finish_and_insert(&bld, fadd); fadd->dest.dest.ssa.num_components = 1; fadd->dest.write_mask = 1; nir_pop_if(&bld, nif); EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl)); } @