head 1.3; access; symbols netbsd-10-2-RELEASE:1.3 netbsd-9-5-RELEASE:1.3 netbsd-11-0-RELEASE:1.3 netbsd-11-0-RC7:1.3 netbsd-11-0-RC6:1.3 netbsd-11-0-RC5:1.3 netbsd-11-0-RC4:1.3 netbsd-11-0-RC3:1.3 netbsd-11-0-RC2:1.3 netbsd-11-0-RC1:1.3 perseant-exfatfs-base-20250801:1.3 netbsd-11:1.3.0.146 netbsd-11-base:1.3 netbsd-10-1-RELEASE:1.3 perseant-exfatfs-base-20240630:1.3 perseant-exfatfs:1.3.0.144 perseant-exfatfs-base:1.3 netbsd-8-3-RELEASE:1.3 netbsd-9-4-RELEASE:1.3 netbsd-10-0-RELEASE:1.3 netbsd-10-0-RC6:1.3 netbsd-10-0-RC5:1.3 netbsd-10-0-RC4:1.3 netbsd-10-0-RC3:1.3 netbsd-10-0-RC2:1.3 thorpej-ifq:1.3.0.142 thorpej-ifq-base:1.3 thorpej-altq-separation:1.3.0.140 thorpej-altq-separation-base:1.3 netbsd-10-0-RC1:1.3 netbsd-10:1.3.0.138 netbsd-10-base:1.3 bouyer-sunxi-drm:1.3.0.136 bouyer-sunxi-drm-base:1.3 netbsd-9-3-RELEASE:1.3 thorpej-i2c-spi-conf2:1.3.0.134 thorpej-i2c-spi-conf2-base:1.3 thorpej-futex2:1.3.0.132 thorpej-futex2-base:1.3 thorpej-cfargs2:1.3.0.130 thorpej-cfargs2-base:1.3 cjep_sun2x-base1:1.3 cjep_sun2x:1.3.0.128 cjep_sun2x-base:1.3 cjep_staticlib_x-base1:1.3 netbsd-9-2-RELEASE:1.3 cjep_staticlib_x:1.3.0.126 cjep_staticlib_x-base:1.3 thorpej-i2c-spi-conf:1.3.0.124 thorpej-i2c-spi-conf-base:1.3 thorpej-cfargs:1.3.0.122 thorpej-cfargs-base:1.3 thorpej-futex:1.3.0.120 thorpej-futex-base:1.3 netbsd-9-1-RELEASE:1.3 bouyer-xenpvh-base2:1.3 phil-wifi-20200421:1.3 bouyer-xenpvh-base1:1.3 phil-wifi-20200411:1.3 bouyer-xenpvh:1.3.0.118 bouyer-xenpvh-base:1.3 is-mlppp:1.3.0.116 is-mlppp-base:1.3 phil-wifi-20200406:1.3 netbsd-8-2-RELEASE:1.3 ad-namecache-base3:1.3 netbsd-9-0-RELEASE:1.3 netbsd-9-0-RC2:1.3 ad-namecache-base2:1.3 ad-namecache-base1:1.3 ad-namecache:1.3.0.114 ad-namecache-base:1.3 netbsd-9-0-RC1:1.3 phil-wifi-20191119:1.3 netbsd-9:1.3.0.112 netbsd-9-base:1.3 phil-wifi-20190609:1.3 netbsd-8-1-RELEASE:1.3 netbsd-8-1-RC1:1.3 isaki-audio2:1.3.0.110 isaki-audio2-base:1.3 pgoyette-compat-merge-20190127:1.3 pgoyette-compat-20190127:1.3 pgoyette-compat-20190118:1.3 pgoyette-compat-1226:1.3 pgoyette-compat-1126:1.3 pgoyette-compat-1020:1.3 pgoyette-compat-0930:1.3 pgoyette-compat-0906:1.3 netbsd-7-2-RELEASE:1.3 pgoyette-compat-0728:1.3 netbsd-8-0-RELEASE:1.3 phil-wifi:1.3.0.108 phil-wifi-base:1.3 pgoyette-compat-0625:1.3 netbsd-8-0-RC2:1.3 pgoyette-compat-0521:1.3 pgoyette-compat-0502:1.3 pgoyette-compat-0422:1.3 netbsd-8-0-RC1:1.3 pgoyette-compat-0415:1.3 pgoyette-compat-0407:1.3 pgoyette-compat-0330:1.3 pgoyette-compat-0322:1.3 pgoyette-compat-0315:1.3 netbsd-7-1-2-RELEASE:1.3 pgoyette-compat:1.3.0.106 pgoyette-compat-base:1.3 netbsd-7-1-1-RELEASE:1.3 tls-maxphys-base-20171202:1.3 matt-nb8-mediatek:1.3.0.104 matt-nb8-mediatek-base:1.3 nick-nhusb-base-20170825:1.3 perseant-stdc-iso10646:1.3.0.102 perseant-stdc-iso10646-base:1.3 netbsd-8:1.3.0.100 netbsd-8-base:1.3 prg-localcount2-base3:1.3 prg-localcount2-base2:1.3 prg-localcount2-base1:1.3 prg-localcount2:1.3.0.98 prg-localcount2-base:1.3 pgoyette-localcount-20170426:1.3 bouyer-socketcan-base1:1.3 jdolecek-ncq:1.3.0.96 jdolecek-ncq-base:1.3 pgoyette-localcount-20170320:1.3 netbsd-7-1:1.3.0.94 netbsd-7-1-RELEASE:1.3 netbsd-7-1-RC2:1.3 nick-nhusb-base-20170204:1.3 netbsd-7-nhusb-base-20170116:1.3 bouyer-socketcan:1.3.0.92 bouyer-socketcan-base:1.3 pgoyette-localcount-20170107:1.3 netbsd-7-1-RC1:1.3 nick-nhusb-base-20161204:1.3 pgoyette-localcount-20161104:1.3 netbsd-7-0-2-RELEASE:1.3 nick-nhusb-base-20161004:1.3 localcount-20160914:1.3 netbsd-7-nhusb:1.3.0.90 netbsd-7-nhusb-base:1.3 pgoyette-localcount-20160806:1.3 pgoyette-localcount-20160726:1.3 pgoyette-localcount:1.3.0.88 pgoyette-localcount-base:1.3 nick-nhusb-base-20160907:1.3 nick-nhusb-base-20160529:1.3 netbsd-7-0-1-RELEASE:1.3 nick-nhusb-base-20160422:1.3 nick-nhusb-base-20160319:1.3 nick-nhusb-base-20151226:1.3 netbsd-7-0:1.3.0.86 netbsd-7-0-RELEASE:1.3 nick-nhusb-base-20150921:1.3 netbsd-7-0-RC3:1.3 netbsd-7-0-RC2:1.3 netbsd-7-0-RC1:1.3 nick-nhusb-base-20150606:1.3 nick-nhusb-base-20150406:1.3 nick-nhusb:1.3.0.84 nick-nhusb-base:1.3 netbsd-5-2-3-RELEASE:1.3 netbsd-5-1-5-RELEASE:1.3 netbsd-6-0-6-RELEASE:1.3 netbsd-6-1-5-RELEASE:1.3 netbsd-7:1.3.0.82 netbsd-7-base:1.3 yamt-pagecache-base9:1.3 yamt-pagecache-tag8:1.3 netbsd-6-1-4-RELEASE:1.3 netbsd-6-0-5-RELEASE:1.3 tls-earlyentropy:1.3.0.80 tls-earlyentropy-base:1.3 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.3 riastradh-drm2-base3:1.3 netbsd-6-1-3-RELEASE:1.3 netbsd-6-0-4-RELEASE:1.3 netbsd-5-2-2-RELEASE:1.3 netbsd-5-1-4-RELEASE:1.3 netbsd-6-1-2-RELEASE:1.3 netbsd-6-0-3-RELEASE:1.3 netbsd-5-2-1-RELEASE:1.3 netbsd-5-1-3-RELEASE:1.3 rmind-smpnet-nbase:1.3 netbsd-6-1-1-RELEASE:1.3 riastradh-drm2-base2:1.3 riastradh-drm2-base1:1.3 riastradh-drm2:1.3.0.78 riastradh-drm2-base:1.3 rmind-smpnet:1.3.0.70 rmind-smpnet-base:1.3 netbsd-6-1:1.3.0.76 netbsd-6-0-2-RELEASE:1.3 netbsd-6-1-RELEASE:1.3 khorben-n900:1.3.0.74 netbsd-6-1-RC4:1.3 netbsd-6-1-RC3:1.3 agc-symver:1.3.0.72 agc-symver-base:1.3 netbsd-6-1-RC2:1.3 netbsd-6-1-RC1:1.3 yamt-pagecache-base8:1.3 netbsd-5-2:1.3.0.68 netbsd-6-0-1-RELEASE:1.3 yamt-pagecache-base7:1.3 netbsd-5-2-RELEASE:1.3 netbsd-5-2-RC1:1.3 matt-nb6-plus-nbase:1.3 yamt-pagecache-base6:1.3 netbsd-6-0:1.3.0.66 netbsd-6-0-RELEASE:1.3 netbsd-6-0-RC2:1.3 tls-maxphys:1.3.0.64 tls-maxphys-base:1.3 matt-nb6-plus:1.3.0.62 matt-nb6-plus-base:1.3 netbsd-6-0-RC1:1.3 jmcneill-usbmp-base10:1.3 yamt-pagecache-base5:1.3 jmcneill-usbmp-base9:1.3 yamt-pagecache-base4:1.3 jmcneill-usbmp-base8:1.3 jmcneill-usbmp-base7:1.3 jmcneill-usbmp-base6:1.3 jmcneill-usbmp-base5:1.3 jmcneill-usbmp-base4:1.3 jmcneill-usbmp-base3:1.3 jmcneill-usbmp-pre-base2:1.3 jmcneill-usbmp-base2:1.3 netbsd-6:1.3.0.60 netbsd-6-base:1.3 netbsd-5-1-2-RELEASE:1.3 netbsd-5-1-1-RELEASE:1.3 jmcneill-usbmp:1.3.0.58 jmcneill-usbmp-base:1.3 jmcneill-audiomp3:1.3.0.56 jmcneill-audiomp3-base:1.3 yamt-pagecache-base3:1.3 yamt-pagecache-base2:1.3 yamt-pagecache:1.3.0.54 yamt-pagecache-base:1.3 rmind-uvmplock-nbase:1.3 cherry-xenmp:1.3.0.52 cherry-xenmp-base:1.3 jym-xensuspend-nbase:1.3 uebayasi-xip-base7:1.3 bouyer-quota2-nbase:1.3 bouyer-quota2:1.3.0.50 bouyer-quota2-base:1.3 jruoho-x86intr:1.3.0.48 jruoho-x86intr-base:1.3 matt-mips64-premerge-20101231:1.3 matt-nb5-mips64-premerge-20101231:1.3 matt-nb5-pq3:1.3.0.46 matt-nb5-pq3-base:1.3 netbsd-5-1:1.3.0.44 uebayasi-xip-base6:1.3 uebayasi-xip-base5:1.3 netbsd-5-1-RELEASE:1.3 uebayasi-xip-base4:1.3 uebayasi-xip-base3:1.3 yamt-nfs-mp-base11:1.3 netbsd-5-1-RC4:1.3 matt-nb5-mips64-k15:1.3 uebayasi-xip-base2:1.3 yamt-nfs-mp-base10:1.3 netbsd-5-1-RC3:1.3 netbsd-5-1-RC2:1.3 uebayasi-xip-base1:1.3 netbsd-5-1-RC1:1.3 rmind-uvmplock:1.3.0.42 rmind-uvmplock-base:1.3 yamt-nfs-mp-base9:1.3 uebayasi-xip:1.3.0.40 uebayasi-xip-base:1.3 netbsd-5-0-2-RELEASE:1.3 matt-nb5-mips64-premerge-20091211:1.3 matt-premerge-20091211:1.3 yamt-nfs-mp-base8:1.3 matt-nb5-mips64-u2-k2-k4-k7-k8-k9:1.3 matt-nb4-mips64-k7-u2a-k9b:1.3 matt-nb5-mips64-u1-k1-k5:1.3 yamt-nfs-mp-base7:1.3 matt-nb5-mips64:1.3.0.38 netbsd-5-0-1-RELEASE:1.3 jymxensuspend-base:1.3 yamt-nfs-mp-base6:1.3 yamt-nfs-mp-base5:1.3 yamt-nfs-mp-base4:1.3 yamt-nfs-mp-base3:1.3 nick-hppapmap-base4:1.3 nick-hppapmap-base3:1.3 netbsd-5-0:1.3.0.36 netbsd-5-0-RELEASE:1.3 netbsd-5-0-RC4:1.3 netbsd-5-0-RC3:1.3 nick-hppapmap-base2:1.3 netbsd-5-0-RC2:1.3 jym-xensuspend:1.3.0.34 jym-xensuspend-base:1.3 netbsd-5-0-RC1:1.3 haad-dm-base2:1.3 haad-nbase2:1.3 ad-audiomp2:1.3.0.32 ad-audiomp2-base:1.3 netbsd-5:1.3.0.30 netbsd-5-base:1.3 nick-hppapmap:1.3.0.28 nick-hppapmap-base:1.3 matt-mips64-base2:1.3 haad-dm-base1:1.3 wrstuden-revivesa-base-4:1.3 netbsd-4-0-1-RELEASE:1.2 wrstuden-revivesa-base-3:1.3 wrstuden-revivesa-base-2:1.3 wrstuden-fixsa-newbase:1.2 nick-csl-alignment-base5:1.2 haad-dm:1.3.0.26 haad-dm-base:1.3 wrstuden-revivesa-base-1:1.3 simonb-wapbl-nbase:1.3 yamt-pf42-base4:1.3 simonb-wapbl:1.3.0.24 simonb-wapbl-base:1.3 yamt-pf42-base3:1.3 hpcarm-cleanup-nbase:1.3 yamt-pf42-baseX:1.3 yamt-pf42-base2:1.3 yamt-nfs-mp-base2:1.3 wrstuden-revivesa:1.3.0.22 wrstuden-revivesa-base:1.3 yamt-nfs-mp:1.3.0.20 yamt-nfs-mp-base:1.3 yamt-pf42:1.3.0.18 yamt-pf42-base:1.3 ad-socklock-base1:1.3 yamt-lazymbuf-base15:1.3 yamt-lazymbuf-base14:1.3 keiichi-mipv6-nbase:1.3 mjf-devfs2:1.3.0.16 mjf-devfs2-base:1.3 nick-net80211-sync:1.3.0.14 nick-net80211-sync-base:1.3 keiichi-mipv6:1.3.0.12 keiichi-mipv6-base:1.3 bouyer-xeni386-merge1:1.3 matt-armv6-prevmlocking:1.2.102.1 wrstuden-fixsa-base-1:1.2 vmlocking2-base3:1.3 netbsd-4-0:1.2.0.110 netbsd-4-0-RELEASE:1.2 bouyer-xeni386-nbase:1.3 yamt-kmem-base3:1.3 cube-autoconf:1.3.0.10 cube-autoconf-base:1.3 yamt-kmem-base2:1.3 bouyer-xeni386:1.3.0.8 bouyer-xeni386-base:1.3 yamt-kmem:1.3.0.6 yamt-kmem-base:1.3 vmlocking2-base2:1.3 reinoud-bufcleanup-nbase:1.3 vmlocking2:1.3.0.4 vmlocking2-base1:1.3 netbsd-4-0-RC5:1.2 matt-nb4-arm:1.2.0.108 matt-nb4-arm-base:1.2 matt-armv6-nbase:1.3 jmcneill-base:1.3 netbsd-4-0-RC4:1.2 mjf-devfs:1.3.0.2 mjf-devfs-base:1.3 bouyer-xenamd64-base2:1.3 vmlocking-nbase:1.3 yamt-x86pmap-base4:1.3 bouyer-xenamd64:1.2.0.106 bouyer-xenamd64-base:1.3 netbsd-4-0-RC3:1.2 yamt-x86pmap-base3:1.2 yamt-x86pmap-base2:1.2 netbsd-4-0-RC2:1.2 yamt-x86pmap:1.2.0.104 yamt-x86pmap-base:1.2 netbsd-4-0-RC1:1.2 matt-armv6:1.2.0.102 matt-armv6-base:1.3 jmcneill-pm:1.2.0.100 jmcneill-pm-base:1.3 hpcarm-cleanup:1.2.0.98 hpcarm-cleanup-base:1.3 nick-csl-alignment:1.2.0.96 nick-csl-alignment-base:1.2 matt-mips64:1.2.0.94 matt-mips64-base:1.2 netbsd-3-1-1-RELEASE:1.2 netbsd-3-0-3-RELEASE:1.2 yamt-idlelwp-base8:1.2 wrstuden-fixsa:1.2.0.92 wrstuden-fixsa-base:1.2 ppcoea-renovation:1.2.0.90 ppcoea-renovation-base:1.2 thorpej-atomic:1.2.0.88 thorpej-atomic-base:1.2 reinoud-bufcleanup:1.2.0.86 reinoud-bufcleanup-base:1.3 mjf-ufs-trans:1.2.0.84 mjf-ufs-trans-base:1.2 vmlocking:1.2.0.82 vmlocking-base:1.2 ad-audiomp:1.2.0.80 ad-audiomp-base:1.2 yamt-idlelwp:1.2.0.78 post-newlock2-merge:1.2 newlock2-nbase:1.2 yamt-splraiseipl-base5:1.2 yamt-splraiseipl-base4:1.2 yamt-splraiseipl-base3:1.2 abandoned-netbsd-4-base:1.2 abandoned-netbsd-4:1.2.0.68 netbsd-3-1:1.2.0.74 netbsd-3-1-RELEASE:1.2 netbsd-3-0-2-RELEASE:1.2 yamt-splraiseipl-base2:1.2 netbsd-3-1-RC4:1.2 yamt-splraiseipl:1.2.0.72 yamt-splraiseipl-base:1.2 netbsd-3-1-RC3:1.2 yamt-pdpolicy-base9:1.2 newlock2:1.2.0.70 newlock2-base:1.2 yamt-pdpolicy-base8:1.2 netbsd-3-1-RC2:1.2 netbsd-3-1-RC1:1.2 yamt-pdpolicy-base7:1.2 netbsd-4:1.2.0.76 netbsd-4-base:1.2 yamt-pdpolicy-base6:1.2 chap-midi-nbase:1.2 netbsd-3-0-1-RELEASE:1.2 gdamore-uart:1.2.0.66 gdamore-uart-base:1.2 simonb-timcounters-final:1.2 yamt-pdpolicy-base5:1.2 chap-midi:1.2.0.64 chap-midi-base:1.2 yamt-pdpolicy-base4:1.2 yamt-pdpolicy-base3:1.2 peter-altq-base:1.2 peter-altq:1.2.0.62 yamt-pdpolicy-base2:1.2 elad-kernelauth-base:1.2 elad-kernelauth:1.2.0.60 yamt-pdpolicy:1.2.0.58 yamt-pdpolicy-base:1.2 yamt-uio_vmspace-base5:1.2 simonb-timecounters:1.2.0.56 simonb-timecounters-base:1.2 rpaulo-netinet-merge-pcb:1.2.0.54 rpaulo-netinet-merge-pcb-base:1.2 yamt-uio_vmspace:1.2.0.52 netbsd-3-0:1.2.0.50 netbsd-3-0-RELEASE:1.2 netbsd-3-0-RC6:1.2 yamt-readahead-base3:1.2 netbsd-3-0-RC5:1.2 netbsd-3-0-RC4:1.2 netbsd-3-0-RC3:1.2 yamt-readahead-base2:1.2 netbsd-3-0-RC2:1.2 yamt-readahead-pervnode:1.2 yamt-readahead-perfile:1.2 yamt-readahead:1.2.0.48 yamt-readahead-base:1.2 netbsd-3-0-RC1:1.2 yamt-vop-base3:1.2 netbsd-2-0-3-RELEASE:1.2 netbsd-2-1:1.2.0.46 yamt-vop-base2:1.2 thorpej-vnode-attr:1.2.0.44 thorpej-vnode-attr-base:1.2 netbsd-2-1-RELEASE:1.2 yamt-vop:1.2.0.42 yamt-vop-base:1.2 netbsd-2-1-RC6:1.2 netbsd-2-1-RC5:1.2 netbsd-2-1-RC4:1.2 netbsd-2-1-RC3:1.2 netbsd-2-1-RC2:1.2 netbsd-2-1-RC1:1.2 yamt-lazymbuf:1.2.0.40 yamt-km-base4:1.2 netbsd-2-0-2-RELEASE:1.2 yamt-km-base3:1.2 netbsd-3:1.2.0.38 netbsd-3-base:1.2 yamt-km-base2:1.2 yamt-km:1.2.0.34 yamt-km-base:1.2 kent-audio2:1.2.0.32 kent-audio2-base:1.2 netbsd-2-0-1-RELEASE:1.2 kent-audio1-beforemerge:1.2 netbsd-2:1.2.0.30 netbsd-2-base:1.2 kent-audio1:1.2.0.28 kent-audio1-base:1.2 netbsd-2-0-RELEASE:1.2 netbsd-2-0-RC5:1.2 netbsd-2-0-RC4:1.2 netbsd-2-0-RC3:1.2 netbsd-2-0-RC2:1.2 netbsd-2-0-RC1:1.2 netbsd-2-0:1.2.0.26 netbsd-2-0-base:1.2 netbsd-1-6-PATCH002-RELEASE:1.2 netbsd-1-6-PATCH002:1.2 netbsd-1-6-PATCH002-RC4:1.2 netbsd-1-6-PATCH002-RC3:1.2 netbsd-1-6-PATCH002-RC2:1.2 netbsd-1-6-PATCH002-RC1:1.2 ktrace-lwp:1.2.0.24 ktrace-lwp-base:1.2 netbsd-1-6-PATCH001:1.2 netbsd-1-6-PATCH001-RELEASE:1.2 netbsd-1-6-PATCH001-RC3:1.2 netbsd-1-6-PATCH001-RC2:1.2 netbsd-1-6-PATCH001-RC1:1.2 nathanw_sa_end:1.2 nathanw_sa_before_merge:1.2 fvdl_fs64_base:1.2 gmcgarry_ctxsw:1.2.0.22 gmcgarry_ctxsw_base:1.2 gmcgarry_ucred:1.2.0.20 gmcgarry_ucred_base:1.2 nathanw_sa_base:1.2 kqueue-aftermerge:1.2 kqueue-beforemerge:1.2 netbsd-1-6-RELEASE:1.2 netbsd-1-6-RC3:1.2 netbsd-1-6-RC2:1.2 netbsd-1-6-RC1:1.2 netbsd-1-6:1.2.0.18 netbsd-1-6-base:1.2 gehenna-devsw:1.2.0.16 gehenna-devsw-base:1.2 eeh-devprop:1.2.0.14 eeh-devprop-base:1.2 newlock:1.2.0.12 newlock-base:1.2 ifpoll-base:1.2 nathanw_sa:1.2.0.8 thorpej-mips-cache:1.2.0.6 thorpej-mips-cache-base:1.2 thorpej-devvp-base3:1.2 thorpej-devvp-base2:1.2 post-chs-ubcperf:1.2 pre-chs-ubcperf:1.2 thorpej-devvp:1.2.0.4 thorpej-devvp-base:1.2 kqueue:1.2.0.2 kqueue-base:1.2 thorpej_scsipi_beforemerge:1.2 thorpej_scsipi_base:1.2 thorpej_scsipi:1.1.0.2 thorpej_scsipi_nbase:1.2; locks; strict; comment @# @; 1.3 date 2007.10.17.19.56.54; author garbled; state Exp; branches; next 1.2; 1.2 date 2001.03.06.20.16.09; author briggs; state Exp; branches 1.2.8.1 1.2.40.1 1.2.82.1 1.2.90.1 1.2.100.1 1.2.102.1 1.2.104.1 1.2.106.1; next 1.1; 1.1 date 2001.02.04.18.32.10; author briggs; state Exp; branches 1.1.2.1 1.1.4.1; next ; 1.2.8.1 date 2001.03.06.20.16.09; author briggs; state dead; branches; next 1.2.8.2; 1.2.8.2 date 2001.03.06.20.16.10; author briggs; state Exp; branches; next ; 1.2.40.1 date 2007.10.27.11.28.12; author yamt; state Exp; branches; next ; 1.2.82.1 date 2007.10.23.20.14.26; author ad; state Exp; branches; next ; 1.2.90.1 date 2007.05.04.19.26.52; author nisimura; state Exp; branches; next ; 1.2.100.1 date 2007.10.26.15.43.27; author joerg; state Exp; branches; next ; 1.2.102.1 date 2007.11.06.23.21.17; author matt; state Exp; branches; next ; 1.2.104.1 date 2007.10.18.08.32.55; author yamt; state Exp; branches; next ; 1.2.106.1 date 2007.10.25.22.36.37; author bouyer; state Exp; branches; next ; 1.1.2.1 date 2001.02.04.18.32.10; author bouyer; state dead; branches; next 1.1.2.2; 1.1.2.2 date 2001.02.11.19.11.40; author bouyer; state Exp; branches; next 1.1.2.3; 1.1.2.3 date 2001.03.12.13.29.16; author bouyer; state Exp; branches; next ; 1.1.4.1 date 2001.04.09.01.54.39; author nathanw; state Exp; branches; next ; desc @@ 1.3 log @Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target. @ text @/* $NetBSD: README,v 1.2.90.1 2007/05/04 19:26:52 nisimura Exp $ */ Overview This is a port to the Motorola "SandPoint" evaluation system. The SandPoint is the successor to the "Yellowknife" system. The system can be fitted with different PMCs (Processor Mezzanine Cards). This port is specifically for the rev X2 motherboard system with the PPC 8240 PMC rev X4 installed. It also works with the Altimus X2 PMC (MPC7400 with MPC107). All references (cf) listed here are for the MPC8240 Integrated Processor User's Manual. Information on the Sandpoint can be found on Motorola's web site: http://www.mot.com/SPS/PowerPC/teksupport/refdesigns/sandpoint.html SandPoint Hardware Configuration This port was developed on a Sandpoint X2 motherboard with a Unity X4 PMC. This port assumes that the jumpers are set as follows: S3/S4 - Mode 1: PMC w/o IDE (switches opposite, one nearest PCI slot toward near edge) S5 - Interrupt to PMC normal (switch toward near edge) S6 - Local I/O shared with slot 2 (switch toward near edge) Mode 0 (PMC w/ IDE) does not appear to work right with ISA interrupts. The interrupts from the Winbond chip do not appear at the PMC. On the PPMC, we assume a 100MHz clock. on PPMC: (C == closed, or "on") SW2: C ROM on PCI bus (DINK32 on mainboard) - Map "B": CHRP C Motorola PPMC C Wait for initialization (peripheral mode) - Program mode: Normal mode - Select normal ROM - 33 MHz only - COP only resets local CPU/MPC107 SW3: -C--C PCI 33, Mem 66, PPC 266 -- 0.5 - 0.9 ns PCI hold time C 25 ohm PCI drive strength Address Map For this port, we choose the "Address Map B" (CHRP-compatible) for the system (see SW2, #2, above): (Processor View) 0000 0000 0009 FFFF System Memory 000A 0000 000F FFFF Compatibility Hole (programmable to go to PCI space or system memory--programmed for system memory--cf 5.8) 0010 0000 3FFF FFFF System memory 4000 0000 7FFF FFFF Reserved (programmed to give a memory select error if accessed--cf 5.7.2) 8000 0000 FCFF FFFF PCI memory space FD00 0000 FDFF FFFF PCI/ISA memory space (see 5.8, CPU_FD_ALIAS_EN) FE00 0000 FE7F FFFF PCI/ISA I/O space (Forwarded to PCI address space with high byte zeroed, but FE01 0000 and up are reserved) FE80 0000 FEBF FFFF PCI I/O space (Forwarded to PCI I/O space with high byte zeroed) FEC0 0000 FEDF FFFF PCI configuration address register (Each word in this range is aliased to the PCI CONFIG_ADDR register) FEE0 0000 FEEF FFFF PCI configuration data register (Each word in this range is aliased to the PCI CONFIG_DATA register) FEF0 0000 FEFF FFFF PCI interrupt acknowledge FF00 0000 FF7F FFFF 32- or 64-bit Flash/ROM space (Can hit either local memory or PCI bus -- cf. 5.6) FF80 0000 FFFF FFFF 8-, 32- or 64-bit Flash/ROM space (Can hit either local memory or PCI bus -- cf. 5.6) This is a host-mode port, so the inbound and output translation windows are unused. The Embedded Utilities Memory Block (EUMB) is set to be 1M below the end of the PCI memory space: FC00 0000, so EUMBBAR is FC00 0000, giving us Message unit (I2O) base : FC00 0000 (cf. 10.2, 10.2.3, 10.3) DMA base : FC00 1000 (cf. 9.2) ATU base : FC00 2000 (cf. 4.3.3) I2C base : FC00 3000 (cf. 11.3) EPIC base : FC04 0000 (cf. 12.2) Boot Information The SandPoint ships with the Motorola DINK32 ROM. This is a rather basic ROM with only serial-download (S-Record) capability for loading the kernel. Basically, the kernel is loaded to a specified address and you jump to it. The ROM takes care of initializing the MICRs and MCCRs. There is really no boot information to pass. It would be nice to have a much more complete ROM interface, allowing settings for, say, bootp/tftp boot, automatic boot, and persistent settings (for console rate, auto boot, bootp, etc), and that might be provided at some point, but that's not available as of this writing. So, the kernel is hard-coded to boot w/ 32MB for now. Interrupt Configuration The 8240 has the internal EPIC. For the SandPoint, the EPIC is programmed in mixed-mode (GCR) with direct interrupts (EICR). With this configuration, there are 13 available interrupts: 4 global timers 5 direct IRQs IRQ0 - PCI Slot #0 INTA# IRQ1 - PCI Slot #1 INTA# / shared with WinBond I/O IRQ2 - PCI Slot #2 INTA# IRQ3 - PCI Slot #3 INTA# IRQ4 - On-PPMC 16552 interrupt (Unity X2) IRQ4 - pulled down w/ resistor (Unity X4) 4 internal interrupts I2C DMA Ch0 DMA Ch1 I2O message unit The SandPoint can run in one of 4 interrupt modes: 0 - PMC host with IDE (3.3v PCI slots are unavailable) 1 - PMC host w/o IDE (all PCI slots are available) 2 - PMC agent, Winbond providing arbitration & interrupt to INTA# on PMC 3 - Yellowknife mode--just like #2, except drives INTA# on 4th PCI slot We choose to run in mode 1 as Motorola recommends modes 0 or 1 for all new development. Unfortunately, mode 0 does not appear to work--"ISA" interrupts are lost. In this mode, with interrupts routed to PCI slot 3, we have to check for both a Winbond (ISA) interrupt, and a PCI slot interrupt. So basically, we have a two-level interrupt configuration for Winbond interrupts. The ISA bus attachment registers an interrupt for PCI slot 3 with its own interrupt handler. Drivers for ISA devices on the Winbond will register interrupts with the ISA interrupt handler. The sticky part of this is how to deal with one global interrupt priority. SandPoint III "SP3" Interrupt Configuration With a help of additional logic circuit SP3 organizes external interrupt sources as EPIC serial mode interrupts. 16 serial IRQs IRQ0 - WinBond South bridge i8259 PIC, polarity inverted IRQ1 - reserved IRQ2 - PCI Slot #1, INTA# IRQ3 - PCI Slot #2, INTA# IRQ4 - PCI Slot #3, INTA# IRQ5 - PCI Slot #4, INTA# IRQ6 - WinBond INTA# IRQ7 - WinBond INTB# IRQ8 - WinBond INTC# IRQ9 - WinBond INTD# IRQ10 thru 15 - reserved SP3 provides switch selections to emulate SP1/2 compatible EPIC direct mode interrupt assignments. @ 1.2 log @Sync with reality. Add NetBSD tag. @ text @d1 1 a1 1 /* $NetBSD$ */ d147 19 @ 1.2.8.1 log @file README was added on branch nathanw_sa on 2001-03-06 20:16:10 +0000 @ text @d1 146 @ 1.2.8.2 log @Sync with reality. Add NetBSD tag. @ text @a0 146 /* $NetBSD: README,v 1.2 2001/03/06 20:16:09 briggs Exp $ */ Overview This is a port to the Motorola "SandPoint" evaluation system. The SandPoint is the successor to the "Yellowknife" system. The system can be fitted with different PMCs (Processor Mezzanine Cards). This port is specifically for the rev X2 motherboard system with the PPC 8240 PMC rev X4 installed. It also works with the Altimus X2 PMC (MPC7400 with MPC107). All references (cf) listed here are for the MPC8240 Integrated Processor User's Manual. Information on the Sandpoint can be found on Motorola's web site: http://www.mot.com/SPS/PowerPC/teksupport/refdesigns/sandpoint.html SandPoint Hardware Configuration This port was developed on a Sandpoint X2 motherboard with a Unity X4 PMC. This port assumes that the jumpers are set as follows: S3/S4 - Mode 1: PMC w/o IDE (switches opposite, one nearest PCI slot toward near edge) S5 - Interrupt to PMC normal (switch toward near edge) S6 - Local I/O shared with slot 2 (switch toward near edge) Mode 0 (PMC w/ IDE) does not appear to work right with ISA interrupts. The interrupts from the Winbond chip do not appear at the PMC. On the PPMC, we assume a 100MHz clock. on PPMC: (C == closed, or "on") SW2: C ROM on PCI bus (DINK32 on mainboard) - Map "B": CHRP C Motorola PPMC C Wait for initialization (peripheral mode) - Program mode: Normal mode - Select normal ROM - 33 MHz only - COP only resets local CPU/MPC107 SW3: -C--C PCI 33, Mem 66, PPC 266 -- 0.5 - 0.9 ns PCI hold time C 25 ohm PCI drive strength Address Map For this port, we choose the "Address Map B" (CHRP-compatible) for the system (see SW2, #2, above): (Processor View) 0000 0000 0009 FFFF System Memory 000A 0000 000F FFFF Compatibility Hole (programmable to go to PCI space or system memory--programmed for system memory--cf 5.8) 0010 0000 3FFF FFFF System memory 4000 0000 7FFF FFFF Reserved (programmed to give a memory select error if accessed--cf 5.7.2) 8000 0000 FCFF FFFF PCI memory space FD00 0000 FDFF FFFF PCI/ISA memory space (see 5.8, CPU_FD_ALIAS_EN) FE00 0000 FE7F FFFF PCI/ISA I/O space (Forwarded to PCI address space with high byte zeroed, but FE01 0000 and up are reserved) FE80 0000 FEBF FFFF PCI I/O space (Forwarded to PCI I/O space with high byte zeroed) FEC0 0000 FEDF FFFF PCI configuration address register (Each word in this range is aliased to the PCI CONFIG_ADDR register) FEE0 0000 FEEF FFFF PCI configuration data register (Each word in this range is aliased to the PCI CONFIG_DATA register) FEF0 0000 FEFF FFFF PCI interrupt acknowledge FF00 0000 FF7F FFFF 32- or 64-bit Flash/ROM space (Can hit either local memory or PCI bus -- cf. 5.6) FF80 0000 FFFF FFFF 8-, 32- or 64-bit Flash/ROM space (Can hit either local memory or PCI bus -- cf. 5.6) This is a host-mode port, so the inbound and output translation windows are unused. The Embedded Utilities Memory Block (EUMB) is set to be 1M below the end of the PCI memory space: FC00 0000, so EUMBBAR is FC00 0000, giving us Message unit (I2O) base : FC00 0000 (cf. 10.2, 10.2.3, 10.3) DMA base : FC00 1000 (cf. 9.2) ATU base : FC00 2000 (cf. 4.3.3) I2C base : FC00 3000 (cf. 11.3) EPIC base : FC04 0000 (cf. 12.2) Boot Information The SandPoint ships with the Motorola DINK32 ROM. This is a rather basic ROM with only serial-download (S-Record) capability for loading the kernel. Basically, the kernel is loaded to a specified address and you jump to it. The ROM takes care of initializing the MICRs and MCCRs. There is really no boot information to pass. It would be nice to have a much more complete ROM interface, allowing settings for, say, bootp/tftp boot, automatic boot, and persistent settings (for console rate, auto boot, bootp, etc), and that might be provided at some point, but that's not available as of this writing. So, the kernel is hard-coded to boot w/ 32MB for now. Interrupt Configuration The 8240 has the internal EPIC. For the SandPoint, the EPIC is programmed in mixed-mode (GCR) with direct interrupts (EICR). With this configuration, there are 13 available interrupts: 4 global timers 5 direct IRQs IRQ0 - PCI Slot #0 INTA# IRQ1 - PCI Slot #1 INTA# / shared with WinBond I/O IRQ2 - PCI Slot #2 INTA# IRQ3 - PCI Slot #3 INTA# IRQ4 - On-PPMC 16552 interrupt (Unity X2) IRQ4 - pulled down w/ resistor (Unity X4) 4 internal interrupts I2C DMA Ch0 DMA Ch1 I2O message unit The SandPoint can run in one of 4 interrupt modes: 0 - PMC host with IDE (3.3v PCI slots are unavailable) 1 - PMC host w/o IDE (all PCI slots are available) 2 - PMC agent, Winbond providing arbitration & interrupt to INTA# on PMC 3 - Yellowknife mode--just like #2, except drives INTA# on 4th PCI slot We choose to run in mode 1 as Motorola recommends modes 0 or 1 for all new development. Unfortunately, mode 0 does not appear to work--"ISA" interrupts are lost. In this mode, with interrupts routed to PCI slot 3, we have to check for both a Winbond (ISA) interrupt, and a PCI slot interrupt. So basically, we have a two-level interrupt configuration for Winbond interrupts. The ISA bus attachment registers an interrupt for PCI slot 3 with its own interrupt handler. Drivers for ISA devices on the Winbond will register interrupts with the ISA interrupt handler. The sticky part of this is how to deal with one global interrupt priority. @ 1.2.102.1 log @sync with HEAD @ text @d1 1 a1 1 /* $NetBSD: README,v 1.3 2007/10/17 19:56:54 garbled Exp $ */ a146 19 SandPoint III "SP3" Interrupt Configuration With a help of additional logic circuit SP3 organizes external interrupt sources as EPIC serial mode interrupts. 16 serial IRQs IRQ0 - WinBond South bridge i8259 PIC, polarity inverted IRQ1 - reserved IRQ2 - PCI Slot #1, INTA# IRQ3 - PCI Slot #2, INTA# IRQ4 - PCI Slot #3, INTA# IRQ5 - PCI Slot #4, INTA# IRQ6 - WinBond INTA# IRQ7 - WinBond INTB# IRQ8 - WinBond INTC# IRQ9 - WinBond INTD# IRQ10 thru 15 - reserved SP3 provides switch selections to emulate SP1/2 compatible EPIC direct mode interrupt assignments. @ 1.2.40.1 log @sync with head. @ text @d1 1 a1 1 /* $NetBSD: README,v 1.2 2001/03/06 20:16:09 briggs Exp $ */ a146 19 SandPoint III "SP3" Interrupt Configuration With a help of additional logic circuit SP3 organizes external interrupt sources as EPIC serial mode interrupts. 16 serial IRQs IRQ0 - WinBond South bridge i8259 PIC, polarity inverted IRQ1 - reserved IRQ2 - PCI Slot #1, INTA# IRQ3 - PCI Slot #2, INTA# IRQ4 - PCI Slot #3, INTA# IRQ5 - PCI Slot #4, INTA# IRQ6 - WinBond INTA# IRQ7 - WinBond INTB# IRQ8 - WinBond INTC# IRQ9 - WinBond INTD# IRQ10 thru 15 - reserved SP3 provides switch selections to emulate SP1/2 compatible EPIC direct mode interrupt assignments. @ 1.2.100.1 log @Sync with HEAD. Follow the merge of pmap.c on i386 and amd64 and move pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup code to restore CR4 before jumping back into kernel space as the large page option might cover that. @ text @d1 1 a1 1 /* $NetBSD: README,v 1.2 2001/03/06 20:16:09 briggs Exp $ */ a146 19 SandPoint III "SP3" Interrupt Configuration With a help of additional logic circuit SP3 organizes external interrupt sources as EPIC serial mode interrupts. 16 serial IRQs IRQ0 - WinBond South bridge i8259 PIC, polarity inverted IRQ1 - reserved IRQ2 - PCI Slot #1, INTA# IRQ3 - PCI Slot #2, INTA# IRQ4 - PCI Slot #3, INTA# IRQ5 - PCI Slot #4, INTA# IRQ6 - WinBond INTA# IRQ7 - WinBond INTB# IRQ8 - WinBond INTC# IRQ9 - WinBond INTD# IRQ10 thru 15 - reserved SP3 provides switch selections to emulate SP1/2 compatible EPIC direct mode interrupt assignments. @ 1.2.106.1 log @Sync with HEAD. @ text @a146 19 SandPoint III "SP3" Interrupt Configuration With a help of additional logic circuit SP3 organizes external interrupt sources as EPIC serial mode interrupts. 16 serial IRQs IRQ0 - WinBond South bridge i8259 PIC, polarity inverted IRQ1 - reserved IRQ2 - PCI Slot #1, INTA# IRQ3 - PCI Slot #2, INTA# IRQ4 - PCI Slot #3, INTA# IRQ5 - PCI Slot #4, INTA# IRQ6 - WinBond INTA# IRQ7 - WinBond INTB# IRQ8 - WinBond INTC# IRQ9 - WinBond INTD# IRQ10 thru 15 - reserved SP3 provides switch selections to emulate SP1/2 compatible EPIC direct mode interrupt assignments. @ 1.2.82.1 log @Sync with head. @ text @d1 1 a1 1 /* $NetBSD: README,v 1.2 2001/03/06 20:16:09 briggs Exp $ */ a146 19 SandPoint III "SP3" Interrupt Configuration With a help of additional logic circuit SP3 organizes external interrupt sources as EPIC serial mode interrupts. 16 serial IRQs IRQ0 - WinBond South bridge i8259 PIC, polarity inverted IRQ1 - reserved IRQ2 - PCI Slot #1, INTA# IRQ3 - PCI Slot #2, INTA# IRQ4 - PCI Slot #3, INTA# IRQ5 - PCI Slot #4, INTA# IRQ6 - WinBond INTA# IRQ7 - WinBond INTB# IRQ8 - WinBond INTC# IRQ9 - WinBond INTD# IRQ10 thru 15 - reserved SP3 provides switch selections to emulate SP1/2 compatible EPIC direct mode interrupt assignments. @ 1.2.104.1 log @sync with head. @ text @d1 1 a1 1 /* $NetBSD: README,v 1.2 2001/03/06 20:16:09 briggs Exp $ */ a146 19 SandPoint III "SP3" Interrupt Configuration With a help of additional logic circuit SP3 organizes external interrupt sources as EPIC serial mode interrupts. 16 serial IRQs IRQ0 - WinBond South bridge i8259 PIC, polarity inverted IRQ1 - reserved IRQ2 - PCI Slot #1, INTA# IRQ3 - PCI Slot #2, INTA# IRQ4 - PCI Slot #3, INTA# IRQ5 - PCI Slot #4, INTA# IRQ6 - WinBond INTA# IRQ7 - WinBond INTB# IRQ8 - WinBond INTC# IRQ9 - WinBond INTD# IRQ10 thru 15 - reserved SP3 provides switch selections to emulate SP1/2 compatible EPIC direct mode interrupt assignments. @ 1.2.90.1 log @- add EPIC interrupt assignment description about SandPoint III "SP3" eval. - the following two PDFs were found useful to learn the difference between SP3 and SP2. http://www.freescale.com/files/soft_dev_tools/doc/user_guide/SPX3UM.pdf http://www.freescale.com/files/archives/doc/user_guide/SANDPOINTX2UM.pdf @ text @d1 1 a1 1 /* $NetBSD: README,v 1.2 2001/03/06 20:16:09 briggs Exp $ */ a146 19 SandPoint III "SP3" Interrupt Configuration With a help of additional logic circuit SP3 organizes external interrupt sources as EPIC serial mode interrupts. 16 serial IRQs IRQ0 - WinBond South bridge i8259 PIC, polarity inverted IRQ1 - reserved IRQ2 - PCI Slot #1, INTA# IRQ3 - PCI Slot #2, INTA# IRQ4 - PCI Slot #3, INTA# IRQ5 - PCI Slot #4, INTA# IRQ6 - WinBond INTA# IRQ7 - WinBond INTB# IRQ8 - WinBond INTC# IRQ9 - WinBond INTD# IRQ10 thru 15 - reserved SP3 provides switch selections to emulate SP1/2 compatible EPIC direct mode interrupt assignments. @ 1.1 log @Support for the Motorola Sandpoint reference platform using the MPC8240 processor module. See the README for more information. @ text @d1 2 d9 2 a10 1 8240 PMC rev X4 installed. d15 2 d82 1 a82 1 of the PCI memory space: FCF0 0000, so EUMBBAR is FCF0 0000, giving us d84 5 a88 5 Message unit (I2O) base : FCF0 0000 (cf. 10.2, 10.2.3, 10.3) DMA base : FCF0 1000 (cf. 9.2) ATU base : FCF0 2000 (cf. 4.3.3) I2C base : FCF0 3000 (cf. 11.3) EPIC base : FCF4 0000 (cf. 12.2) d106 1 a106 1 So, the kernel is hard-coded to boot w/ 64MB for now. @ 1.1.2.1 log @file README was added on branch thorpej_scsipi on 2001-02-11 19:11:40 +0000 @ text @d1 141 @ 1.1.2.2 log @Sync with HEAD. @ text @a0 141 Overview This is a port to the Motorola "SandPoint" evaluation system. The SandPoint is the successor to the "Yellowknife" system. The system can be fitted with different PMCs (Processor Mezzanine Cards). This port is specifically for the rev X2 motherboard system with the PPC 8240 PMC rev X4 installed. All references (cf) listed here are for the MPC8240 Integrated Processor User's Manual. SandPoint Hardware Configuration This port was developed on a Sandpoint X2 motherboard with a Unity X4 PMC. This port assumes that the jumpers are set as follows: S3/S4 - Mode 1: PMC w/o IDE (switches opposite, one nearest PCI slot toward near edge) S5 - Interrupt to PMC normal (switch toward near edge) S6 - Local I/O shared with slot 2 (switch toward near edge) Mode 0 (PMC w/ IDE) does not appear to work right with ISA interrupts. The interrupts from the Winbond chip do not appear at the PMC. On the PPMC, we assume a 100MHz clock. on PPMC: (C == closed, or "on") SW2: C ROM on PCI bus (DINK32 on mainboard) - Map "B": CHRP C Motorola PPMC C Wait for initialization (peripheral mode) - Program mode: Normal mode - Select normal ROM - 33 MHz only - COP only resets local CPU/MPC107 SW3: -C--C PCI 33, Mem 66, PPC 266 -- 0.5 - 0.9 ns PCI hold time C 25 ohm PCI drive strength Address Map For this port, we choose the "Address Map B" (CHRP-compatible) for the system (see SW2, #2, above): (Processor View) 0000 0000 0009 FFFF System Memory 000A 0000 000F FFFF Compatibility Hole (programmable to go to PCI space or system memory--programmed for system memory--cf 5.8) 0010 0000 3FFF FFFF System memory 4000 0000 7FFF FFFF Reserved (programmed to give a memory select error if accessed--cf 5.7.2) 8000 0000 FCFF FFFF PCI memory space FD00 0000 FDFF FFFF PCI/ISA memory space (see 5.8, CPU_FD_ALIAS_EN) FE00 0000 FE7F FFFF PCI/ISA I/O space (Forwarded to PCI address space with high byte zeroed, but FE01 0000 and up are reserved) FE80 0000 FEBF FFFF PCI I/O space (Forwarded to PCI I/O space with high byte zeroed) FEC0 0000 FEDF FFFF PCI configuration address register (Each word in this range is aliased to the PCI CONFIG_ADDR register) FEE0 0000 FEEF FFFF PCI configuration data register (Each word in this range is aliased to the PCI CONFIG_DATA register) FEF0 0000 FEFF FFFF PCI interrupt acknowledge FF00 0000 FF7F FFFF 32- or 64-bit Flash/ROM space (Can hit either local memory or PCI bus -- cf. 5.6) FF80 0000 FFFF FFFF 8-, 32- or 64-bit Flash/ROM space (Can hit either local memory or PCI bus -- cf. 5.6) This is a host-mode port, so the inbound and output translation windows are unused. The Embedded Utilities Memory Block (EUMB) is set to be 1M below the end of the PCI memory space: FCF0 0000, so EUMBBAR is FCF0 0000, giving us Message unit (I2O) base : FCF0 0000 (cf. 10.2, 10.2.3, 10.3) DMA base : FCF0 1000 (cf. 9.2) ATU base : FCF0 2000 (cf. 4.3.3) I2C base : FCF0 3000 (cf. 11.3) EPIC base : FCF4 0000 (cf. 12.2) Boot Information The SandPoint ships with the Motorola DINK32 ROM. This is a rather basic ROM with only serial-download (S-Record) capability for loading the kernel. Basically, the kernel is loaded to a specified address and you jump to it. The ROM takes care of initializing the MICRs and MCCRs. There is really no boot information to pass. It would be nice to have a much more complete ROM interface, allowing settings for, say, bootp/tftp boot, automatic boot, and persistent settings (for console rate, auto boot, bootp, etc), and that might be provided at some point, but that's not available as of this writing. So, the kernel is hard-coded to boot w/ 64MB for now. Interrupt Configuration The 8240 has the internal EPIC. For the SandPoint, the EPIC is programmed in mixed-mode (GCR) with direct interrupts (EICR). With this configuration, there are 13 available interrupts: 4 global timers 5 direct IRQs IRQ0 - PCI Slot #0 INTA# IRQ1 - PCI Slot #1 INTA# / shared with WinBond I/O IRQ2 - PCI Slot #2 INTA# IRQ3 - PCI Slot #3 INTA# IRQ4 - On-PPMC 16552 interrupt (Unity X2) IRQ4 - pulled down w/ resistor (Unity X4) 4 internal interrupts I2C DMA Ch0 DMA Ch1 I2O message unit The SandPoint can run in one of 4 interrupt modes: 0 - PMC host with IDE (3.3v PCI slots are unavailable) 1 - PMC host w/o IDE (all PCI slots are available) 2 - PMC agent, Winbond providing arbitration & interrupt to INTA# on PMC 3 - Yellowknife mode--just like #2, except drives INTA# on 4th PCI slot We choose to run in mode 1 as Motorola recommends modes 0 or 1 for all new development. Unfortunately, mode 0 does not appear to work--"ISA" interrupts are lost. In this mode, with interrupts routed to PCI slot 3, we have to check for both a Winbond (ISA) interrupt, and a PCI slot interrupt. So basically, we have a two-level interrupt configuration for Winbond interrupts. The ISA bus attachment registers an interrupt for PCI slot 3 with its own interrupt handler. Drivers for ISA devices on the Winbond will register interrupts with the ISA interrupt handler. The sticky part of this is how to deal with one global interrupt priority. @ 1.1.2.3 log @Sync with HEAD. @ text @a0 2 /* $NetBSD: README,v 1.1.2.2 2001/03/12 13:29:16 bouyer Exp $ */ d7 1 a7 2 8240 PMC rev X4 installed. It also works with the Altimus X2 PMC (MPC7400 with MPC107). a11 2 Information on the Sandpoint can be found on Motorola's web site: http://www.mot.com/SPS/PowerPC/teksupport/refdesigns/sandpoint.html d77 1 a77 1 of the PCI memory space: FC00 0000, so EUMBBAR is FC00 0000, giving us d79 5 a83 5 Message unit (I2O) base : FC00 0000 (cf. 10.2, 10.2.3, 10.3) DMA base : FC00 1000 (cf. 9.2) ATU base : FC00 2000 (cf. 4.3.3) I2C base : FC00 3000 (cf. 11.3) EPIC base : FC04 0000 (cf. 12.2) d101 1 a101 1 So, the kernel is hard-coded to boot w/ 32MB for now. @ 1.1.4.1 log @Catch up with -current. @ text @a0 2 /* $NetBSD: README,v 1.2 2001/03/06 20:16:09 briggs Exp $ */ d7 1 a7 2 8240 PMC rev X4 installed. It also works with the Altimus X2 PMC (MPC7400 with MPC107). a11 2 Information on the Sandpoint can be found on Motorola's web site: http://www.mot.com/SPS/PowerPC/teksupport/refdesigns/sandpoint.html d77 1 a77 1 of the PCI memory space: FC00 0000, so EUMBBAR is FC00 0000, giving us d79 5 a83 5 Message unit (I2O) base : FC00 0000 (cf. 10.2, 10.2.3, 10.3) DMA base : FC00 1000 (cf. 9.2) ATU base : FC00 2000 (cf. 4.3.3) I2C base : FC00 3000 (cf. 11.3) EPIC base : FC04 0000 (cf. 12.2) d101 1 a101 1 So, the kernel is hard-coded to boot w/ 32MB for now. @