head	1.3;
access;
symbols
	netbsd-9-5-RELEASE:1.2
	perseant-exfatfs-base-20250801:1.3
	perseant-exfatfs-base-20240630:1.3
	perseant-exfatfs:1.3.0.2
	perseant-exfatfs-base:1.3
	netbsd-8-3-RELEASE:1.1
	netbsd-9-4-RELEASE:1.2
	bouyer-sunxi-drm:1.2.0.28
	bouyer-sunxi-drm-base:1.2
	netbsd-9-3-RELEASE:1.2
	thorpej-i2c-spi-conf2:1.2.0.26
	thorpej-i2c-spi-conf2-base:1.2
	thorpej-futex2:1.2.0.24
	thorpej-futex2-base:1.2
	thorpej-cfargs2:1.2.0.22
	thorpej-cfargs2-base:1.2
	cjep_sun2x-base1:1.2
	cjep_sun2x:1.2.0.20
	cjep_sun2x-base:1.2
	cjep_staticlib_x-base1:1.2
	netbsd-9-2-RELEASE:1.2
	cjep_staticlib_x:1.2.0.18
	cjep_staticlib_x-base:1.2
	thorpej-i2c-spi-conf:1.2.0.16
	thorpej-i2c-spi-conf-base:1.2
	thorpej-cfargs:1.2.0.14
	thorpej-cfargs-base:1.2
	thorpej-futex:1.2.0.12
	thorpej-futex-base:1.2
	netbsd-9-1-RELEASE:1.2
	bouyer-xenpvh-base2:1.2
	phil-wifi-20200421:1.2
	bouyer-xenpvh-base1:1.2
	phil-wifi-20200411:1.2
	bouyer-xenpvh:1.2.0.10
	bouyer-xenpvh-base:1.2
	is-mlppp:1.2.0.8
	is-mlppp-base:1.2
	phil-wifi-20200406:1.2
	netbsd-8-2-RELEASE:1.1
	ad-namecache-base3:1.2
	netbsd-9-0-RELEASE:1.2
	netbsd-9-0-RC2:1.2
	ad-namecache-base2:1.2
	ad-namecache-base1:1.2
	ad-namecache:1.2.0.6
	ad-namecache-base:1.2
	netbsd-9-0-RC1:1.2
	phil-wifi-20191119:1.2
	netbsd-9:1.2.0.4
	netbsd-9-base:1.2
	phil-wifi-20190609:1.2
	netbsd-8-1-RELEASE:1.1
	netbsd-8-1-RC1:1.1
	isaki-audio2:1.2.0.2
	isaki-audio2-base:1.2
	pgoyette-compat-merge-20190127:1.1.22.1
	pgoyette-compat-20190127:1.2
	pgoyette-compat-20190118:1.2
	pgoyette-compat-1226:1.2
	pgoyette-compat-1126:1.2
	pgoyette-compat-1020:1.2
	pgoyette-compat-0930:1.2
	pgoyette-compat-0906:1.1
	netbsd-7-2-RELEASE:1.1.4.2
	pgoyette-compat-0728:1.1
	netbsd-8-0-RELEASE:1.1
	phil-wifi:1.1.0.24
	phil-wifi-base:1.1
	pgoyette-compat-0625:1.1
	netbsd-8-0-RC2:1.1
	pgoyette-compat-0521:1.1
	pgoyette-compat-0502:1.1
	pgoyette-compat-0422:1.1
	netbsd-8-0-RC1:1.1
	pgoyette-compat-0415:1.1
	pgoyette-compat-0407:1.1
	pgoyette-compat-0330:1.1
	pgoyette-compat-0322:1.1
	pgoyette-compat-0315:1.1
	netbsd-7-1-2-RELEASE:1.1.4.2
	pgoyette-compat:1.1.0.22
	pgoyette-compat-base:1.1
	netbsd-7-1-1-RELEASE:1.1.4.2
	tls-maxphys:1.1.0.20
	tls-maxphys-base-20171202:1.1
	matt-nb8-mediatek:1.1.0.18
	matt-nb8-mediatek-base:1.1
	nick-nhusb-base-20170825:1.1
	perseant-stdc-iso10646:1.1.0.16
	perseant-stdc-iso10646-base:1.1
	netbsd-8:1.1.0.14
	netbsd-8-base:1.1
	prg-localcount2-base3:1.1
	prg-localcount2-base2:1.1
	prg-localcount2-base1:1.1
	prg-localcount2:1.1.0.12
	prg-localcount2-base:1.1
	pgoyette-localcount-20170426:1.1
	bouyer-socketcan-base1:1.1
	jdolecek-ncq:1.1.0.10
	jdolecek-ncq-base:1.1
	pgoyette-localcount-20170320:1.1
	netbsd-7-1:1.1.4.2.0.6
	netbsd-7-1-RELEASE:1.1.4.2
	netbsd-7-1-RC2:1.1.4.2
	nick-nhusb-base-20170204:1.1
	netbsd-7-nhusb-base-20170116:1.1.4.2
	bouyer-socketcan:1.1.0.8
	bouyer-socketcan-base:1.1
	pgoyette-localcount-20170107:1.1
	netbsd-7-1-RC1:1.1.4.2
	nick-nhusb-base-20161204:1.1
	pgoyette-localcount-20161104:1.1
	netbsd-7-0-2-RELEASE:1.1.4.2
	nick-nhusb-base-20161004:1.1
	localcount-20160914:1.1
	netbsd-7-nhusb:1.1.4.2.0.4
	netbsd-7-nhusb-base:1.1.4.2
	pgoyette-localcount-20160806:1.1
	pgoyette-localcount-20160726:1.1
	pgoyette-localcount:1.1.0.6
	pgoyette-localcount-base:1.1
	nick-nhusb-base-20160907:1.1
	nick-nhusb-base-20160529:1.1
	netbsd-7-0-1-RELEASE:1.1.4.2
	nick-nhusb-base-20160422:1.1
	nick-nhusb-base-20160319:1.1
	nick-nhusb-base-20151226:1.1
	netbsd-7-0:1.1.4.2.0.2
	netbsd-7-0-RELEASE:1.1.4.2
	nick-nhusb-base-20150921:1.1
	netbsd-7-0-RC3:1.1.4.2
	netbsd-7-0-RC2:1.1.4.2
	netbsd-7-0-RC1:1.1.4.2
	nick-nhusb-base-20150606:1.1
	netbsd-7:1.1.0.4
	nick-nhusb:1.1.0.2
	nick-nhusb-base-20150406:1.1;
locks; strict;
comment	@# @;


1.3
date	2022.10.28.20.37.04;	author jmcneill;	state dead;
branches;
next	1.2;
commitid	NabqIhGnJEFbHwZD;

1.2
date	2018.09.21.12.04.07;	author skrll;	state Exp;
branches;
next	1.1;
commitid	koRgyXMfdOPKZXSA;

1.1
date	2015.01.23.12.34.09;	author hkenken;	state Exp;
branches
	1.1.2.1
	1.1.4.1
	1.1.20.1
	1.1.22.1
	1.1.24.1;
next	;
commitid	8qH4SQRVyckz997y;

1.1.2.1
date	2015.01.23.12.34.09;	author skrll;	state dead;
branches;
next	1.1.2.2;
commitid	pz01Zhy7RP6iGxgy;

1.1.2.2
date	2015.04.06.15.17.53;	author skrll;	state Exp;
branches;
next	;
commitid	pz01Zhy7RP6iGxgy;

1.1.4.1
date	2015.01.23.12.34.09;	author msaitoh;	state dead;
branches;
next	1.1.4.2;
commitid	1AAwci6rxEcea1ly;

1.1.4.2
date	2015.05.11.11.00.33;	author msaitoh;	state Exp;
branches;
next	;
commitid	1AAwci6rxEcea1ly;

1.1.20.1
date	2015.01.23.12.34.09;	author jdolecek;	state dead;
branches;
next	1.1.20.2;
commitid	XcIYRZTAh1LmerhA;

1.1.20.2
date	2017.12.03.11.35.57;	author jdolecek;	state Exp;
branches;
next	;
commitid	XcIYRZTAh1LmerhA;

1.1.22.1
date	2018.09.30.01.45.39;	author pgoyette;	state Exp;
branches;
next	;
commitid	SQ44grEPCeKPh4UA;

1.1.24.1
date	2019.06.10.22.05.58;	author christos;	state Exp;
branches;
next	;
commitid	jtc8rnCzWiEEHGqB;


desc
@@


1.3
log
@Retire PARALLELLA and ZEDBOARD kernel configs.

The Zynq-7000 port has been converted to Devicetree and is supported
by the GENERIC kernel now.
@
text
@#	$NetBSD: files.zynq,v 1.2 2018/09/21 12:04:07 skrll Exp $
#
# Configuration info for xilinx Zynq-7000 ARM Peripherals
#

include "arch/arm/pic/files.pic"
include "arch/arm/cortex/files.cortex"

file	arch/arm/zynq/zynq_space.c
file	arch/arm/zynq/zynq_dma.c

file	arch/arm/arm32/arm32_boot.c
file	arch/arm/arm32/arm32_kvminit.c
file	arch/arm/arm32/arm32_reboot.c
file	arch/arm/arm32/irq_dispatch.S

file	arch/arm/zynq/zynq7000_board.c

# Console parameters
defflag opt_zynq.h				ZYNQ
defflag opt_zynq.h				ZYNQ7000
defparam opt_zynq.h				MEMSIZE

# AXI bus interface and SoC domains
device	axi {[addr=-1], [size=0], [irq=-1], [irqbase=-1]} : bus_space_generic
attach	axi at mainbus
file	arch/arm/zynq/zynq_axi.c		axi

# System Level Control Module
device	zynqslcr
attach	zynqslcr at axi
file	arch/arm/zynq/zynq_slcr.c		zynqslcr needs-flag

# UART
device	zynquart
attach	zynquart at axi
file	arch/arm/zynq/zynq_uart.c		zynquart needs-flag
file	arch/arm/zynq/zynq7000_uart.c		zynquart
defflag	opt_zynquart.h				ZYNQUARTCONSOLE

# USB controller
attach	ehci at axi with zynqusb
file	arch/arm/zynq/zynq_usb.c		zynqusb
file	arch/arm/zynq/zynq7000_usb.c		zynqusb

# SD host controller for SD/MMC
attach	sdhc at axi with sdhc_axi
file	arch/arm/zynq/zynq7000_sdhc.c		sdhc_axi

# Gigabit Ethernet Controller
device	cemac: ether, ifnet, arp, mii, bus_dma_generic
attach	cemac at axi
file	dev/cadence/if_cemac.c			cemac
file	arch/arm/zynq/zynq_cemac.c		cemac

@


1.2
log
@Centralise defparam CONSADDR, CONSPEED, CONMODE and CONADDR into
opt_console.h and adjust.
@
text
@d1 1
a1 1
#	$NetBSD: files.zynq,v 1.1 2015/01/23 12:34:09 hkenken Exp $
@


1.1
log
@Initial Zynq (Xilinx) support
Add support for ZedBoard evaluation board and Parallella board.
* cemac(4) Cadence EMAC/GEM(Gigabit) Ethernet Controller driver
  based on at91emac
@
text
@d1 1
a1 1
#	$NetBSD$
a21 3
defparam opt_zynq.h				CONADDR
defparam opt_zynq.h				CONSPEED
defparam opt_zynq.h				CONMODE
@


1.1.24.1
log
@Sync with HEAD
@
text
@d1 1
a1 1
#	$NetBSD: files.zynq,v 1.2 2018/09/21 12:04:07 skrll Exp $
d22 3
@


1.1.22.1
log
@Ssync with HEAD
@
text
@d1 1
a1 1
#	$NetBSD: files.zynq,v 1.2 2018/09/21 12:04:07 skrll Exp $
d22 3
@


1.1.20.1
log
@file files.zynq was added on branch tls-maxphys on 2017-12-03 11:35:57 +0000
@
text
@d1 58
@


1.1.20.2
log
@update from HEAD
@
text
@a0 58
#	$NetBSD$
#
# Configuration info for xilinx Zynq-7000 ARM Peripherals
#

include "arch/arm/pic/files.pic"
include "arch/arm/cortex/files.cortex"

file	arch/arm/zynq/zynq_space.c
file	arch/arm/zynq/zynq_dma.c

file	arch/arm/arm32/arm32_boot.c
file	arch/arm/arm32/arm32_kvminit.c
file	arch/arm/arm32/arm32_reboot.c
file	arch/arm/arm32/irq_dispatch.S

file	arch/arm/zynq/zynq7000_board.c

# Console parameters
defflag opt_zynq.h				ZYNQ
defflag opt_zynq.h				ZYNQ7000
defparam opt_zynq.h				CONADDR
defparam opt_zynq.h				CONSPEED
defparam opt_zynq.h				CONMODE
defparam opt_zynq.h				MEMSIZE

# AXI bus interface and SoC domains
device	axi {[addr=-1], [size=0], [irq=-1], [irqbase=-1]} : bus_space_generic
attach	axi at mainbus
file	arch/arm/zynq/zynq_axi.c		axi

# System Level Control Module
device	zynqslcr
attach	zynqslcr at axi
file	arch/arm/zynq/zynq_slcr.c		zynqslcr needs-flag

# UART
device	zynquart
attach	zynquart at axi
file	arch/arm/zynq/zynq_uart.c		zynquart needs-flag
file	arch/arm/zynq/zynq7000_uart.c		zynquart
defflag	opt_zynquart.h				ZYNQUARTCONSOLE

# USB controller
attach	ehci at axi with zynqusb
file	arch/arm/zynq/zynq_usb.c		zynqusb
file	arch/arm/zynq/zynq7000_usb.c		zynqusb

# SD host controller for SD/MMC
attach	sdhc at axi with sdhc_axi
file	arch/arm/zynq/zynq7000_sdhc.c		sdhc_axi

# Gigabit Ethernet Controller
device	cemac: ether, ifnet, arp, mii, bus_dma_generic
attach	cemac at axi
file	dev/cadence/if_cemac.c			cemac
file	arch/arm/zynq/zynq_cemac.c		cemac

@


1.1.4.1
log
@file files.zynq was added on branch netbsd-7 on 2015-05-11 11:00:33 +0000
@
text
@d1 58
@


1.1.4.2
log
@Pull up following revision(s) (requested by nonaka in ticket #751):
	sys/arch/arm/zynq/zynq_axi.c: revision 1.1
	sys/arch/evbarm/conf/files.zynq: revision 1.1
	sys/arch/arm/zynq/zynq_uart.c: revision 1.1
	sys/arch/evbarm/zynq/genassym.cf: revision 1.1
	sys/arch/evbarm/zynq/zynq_start.S: revision 1.1
	sys/arch/arm/zynq/zynq_slcrreg.h: revision 1.1
	sys/arch/arm/zynq/zynq_usbreg.h: revision 1.1
	sys/arch/arm/zynq/zynq7000_uart.c: revision 1.1
	sys/arch/arm/zynq/zynq7000_sdhc.c: revision 1.1
	sys/arch/arm/zynq/zynq_slcrvar.h: revision 1.1
	sys/arch/arm/zynq/zynq_usbvar.h: revision 1.1
	sys/arch/evbarm/conf/PARALLELLA_INSTALL: revision 1.1
	sys/arch/arm/zynq/zynq_uartreg.h: revision 1.1
	sys/arch/evbarm/zynq/platform.h: revision 1.1
	sys/arch/evbarm/conf/mk.zynq: revision 1.1
	sys/arch/evbarm/conf/files.zedboard: revision 1.1
	sys/arch/arm/zynq/zynq7000_usb.c: revision 1.1
	sys/dev/cadence/if_cemacvar.h: revision 1.1
	sys/arch/arm/zynq/files.zynq: revision 1.1
	sys/arch/arm/zynq/zynq_slcr.c: revision 1.1
	sys/arch/arm/zynq/zynq7000_intr.h: revision 1.1
	sys/arch/arm/conf/majors.arm32: revision 1.36
	sys/arch/arm/zynq/zynq_uartvar.h: revision 1.1
	sys/arch/evbarm/conf/files.parallella: revision 1.1
	sys/arch/arm/zynq/zynq_space.c: revision 1.1
	sys/dev/cadence/if_cemac.c: revision 1.1
	sys/arch/evbarm/conf/PARALLELLA: revision 1.1
	sys/arch/arm/zynq/zynq7000_board.c: revision 1.1
	sys/arch/evbarm/Makefile: revision 1.10
	sys/arch/evbarm/zynq/zynq_machdep.c: revision 1.1
	sys/arch/arm/zynq/zynq7000_reg.h: revision 1.1
	sys/arch/evbarm/conf/ZEDBOARD: revision 1.1
	sys/dev/cadence/cemacreg.h: revision 1.1
	sys/arch/evbarm/conf/std.zynq: revision 1.1
	sys/arch/arm/zynq/zynq_dma.c: revision 1.1
	sys/arch/arm/zynq/zynq_cemac.c: revision 1.1
	sys/arch/arm/zynq/zynq7000_var.h: revision 1.1
	sys/arch/evbarm/conf/ZEDBOARD_INSTALL: revision 1.1
	sys/arch/arm/zynq/zynq_usb.c: revision 1.1
Initial Zynq (Xilinx) support
Add support for ZedBoard evaluation board and Parallella board.
* cemac(4) Cadence EMAC/GEM(Gigabit) Ethernet Controller driver
  based on at91emac
@
text
@a0 58
#	$NetBSD: files.zynq,v 1.1 2015/01/23 12:34:09 hkenken Exp $
#
# Configuration info for xilinx Zynq-7000 ARM Peripherals
#

include "arch/arm/pic/files.pic"
include "arch/arm/cortex/files.cortex"

file	arch/arm/zynq/zynq_space.c
file	arch/arm/zynq/zynq_dma.c

file	arch/arm/arm32/arm32_boot.c
file	arch/arm/arm32/arm32_kvminit.c
file	arch/arm/arm32/arm32_reboot.c
file	arch/arm/arm32/irq_dispatch.S

file	arch/arm/zynq/zynq7000_board.c

# Console parameters
defflag opt_zynq.h				ZYNQ
defflag opt_zynq.h				ZYNQ7000
defparam opt_zynq.h				CONADDR
defparam opt_zynq.h				CONSPEED
defparam opt_zynq.h				CONMODE
defparam opt_zynq.h				MEMSIZE

# AXI bus interface and SoC domains
device	axi {[addr=-1], [size=0], [irq=-1], [irqbase=-1]} : bus_space_generic
attach	axi at mainbus
file	arch/arm/zynq/zynq_axi.c		axi

# System Level Control Module
device	zynqslcr
attach	zynqslcr at axi
file	arch/arm/zynq/zynq_slcr.c		zynqslcr needs-flag

# UART
device	zynquart
attach	zynquart at axi
file	arch/arm/zynq/zynq_uart.c		zynquart needs-flag
file	arch/arm/zynq/zynq7000_uart.c		zynquart
defflag	opt_zynquart.h				ZYNQUARTCONSOLE

# USB controller
attach	ehci at axi with zynqusb
file	arch/arm/zynq/zynq_usb.c		zynqusb
file	arch/arm/zynq/zynq7000_usb.c		zynqusb

# SD host controller for SD/MMC
attach	sdhc at axi with sdhc_axi
file	arch/arm/zynq/zynq7000_sdhc.c		sdhc_axi

# Gigabit Ethernet Controller
device	cemac: ether, ifnet, arp, mii, bus_dma_generic
attach	cemac at axi
file	dev/cadence/if_cemac.c			cemac
file	arch/arm/zynq/zynq_cemac.c		cemac

@


1.1.2.1
log
@file files.zynq was added on branch nick-nhusb on 2015-04-06 15:17:53 +0000
@
text
@d1 58
@


1.1.2.2
log
@Sync with HEAD
@
text
@a0 58
#	$NetBSD: files.zynq,v 1.1 2015/01/23 12:34:09 hkenken Exp $
#
# Configuration info for xilinx Zynq-7000 ARM Peripherals
#

include "arch/arm/pic/files.pic"
include "arch/arm/cortex/files.cortex"

file	arch/arm/zynq/zynq_space.c
file	arch/arm/zynq/zynq_dma.c

file	arch/arm/arm32/arm32_boot.c
file	arch/arm/arm32/arm32_kvminit.c
file	arch/arm/arm32/arm32_reboot.c
file	arch/arm/arm32/irq_dispatch.S

file	arch/arm/zynq/zynq7000_board.c

# Console parameters
defflag opt_zynq.h				ZYNQ
defflag opt_zynq.h				ZYNQ7000
defparam opt_zynq.h				CONADDR
defparam opt_zynq.h				CONSPEED
defparam opt_zynq.h				CONMODE
defparam opt_zynq.h				MEMSIZE

# AXI bus interface and SoC domains
device	axi {[addr=-1], [size=0], [irq=-1], [irqbase=-1]} : bus_space_generic
attach	axi at mainbus
file	arch/arm/zynq/zynq_axi.c		axi

# System Level Control Module
device	zynqslcr
attach	zynqslcr at axi
file	arch/arm/zynq/zynq_slcr.c		zynqslcr needs-flag

# UART
device	zynquart
attach	zynquart at axi
file	arch/arm/zynq/zynq_uart.c		zynquart needs-flag
file	arch/arm/zynq/zynq7000_uart.c		zynquart
defflag	opt_zynquart.h				ZYNQUARTCONSOLE

# USB controller
attach	ehci at axi with zynqusb
file	arch/arm/zynq/zynq_usb.c		zynqusb
file	arch/arm/zynq/zynq7000_usb.c		zynqusb

# SD host controller for SD/MMC
attach	sdhc at axi with sdhc_axi
file	arch/arm/zynq/zynq7000_sdhc.c		sdhc_axi

# Gigabit Ethernet Controller
device	cemac: ether, ifnet, arp, mii, bus_dma_generic
attach	cemac at axi
file	dev/cadence/if_cemac.c			cemac
file	arch/arm/zynq/zynq_cemac.c		cemac

@