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branch	1.1.1;
access;
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	gmp:1.1.1;
locks; strict;
comment	@;; @;


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desc
@@


1.1
log
@Initial revision
@
text
@dnl  AMD64 mpn_modexact_1_odd -- exact division style remainder.

dnl  Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software
dnl  Foundation, Inc.
dnl
dnl  This file is part of the GNU MP Library.
dnl
dnl  The GNU MP Library is free software; you can redistribute it and/or
dnl  modify it under the terms of the GNU Lesser General Public License as
dnl  published by the Free Software Foundation; either version 3 of the
dnl  License, or (at your option) any later version.
dnl
dnl  The GNU MP Library is distributed in the hope that it will be useful,
dnl  but WITHOUT ANY WARRANTY; without even the implied warranty of
dnl  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
dnl  Lesser General Public License for more details.
dnl
dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')


C	     cycles/limb
C K8,K9:	10
C K10:		10
C P4:		33
C P6 core2:	13
C P6 corei7:	14.5
C P6 Atom:	35


C mp_limb_t mpn_modexact_1_odd (mp_srcptr src, mp_size_t size,
C                               mp_limb_t divisor);
C mp_limb_t mpn_modexact_1c_odd (mp_srcptr src, mp_size_t size,
C                                mp_limb_t divisor, mp_limb_t carry);
C
C
C The dependent chain in the main loop is
C
C                            cycles
C	subq	%rdx, %rax	1
C	imulq	%r9, %rax	4
C	mulq	%r8		5
C			      ----
C       total		       10
C
C The movq load from src seems to need to be scheduled back before the jz to
C achieve this speed, out-of-order execution apparently can't completely
C hide the latency otherwise.
C
C The l=src[i]-cbit step is rotated back too, since that allows us to avoid
C it for the first iteration (where there's no cbit).
C
C The code alignment used (32-byte) for the loop also seems necessary.
C Without that the non-PIC case has adcq crossing the 0x60 offset,
C apparently making it run at 11 cycles instead of 10.
C
C Not done:
C
C divq for size==1 was measured at about 79 cycles, compared to the inverse
C at about 25 cycles (both including function call overheads), so that's not
C used.
C
C Enhancements:
C
C For PIC, we shouldn't really need the GOT fetch for binvert_limb_table,
C it'll be in rodata or text in libgmp.so and can be accessed directly %rip
C relative.  This would be for small model only (something we don't
C presently detect, but which is all that gcc 3.3.3 supports), since 8-byte
C PC-relative relocations are apparently not available.  Some rough
C experiments with binutils 2.13 looked worrylingly like it might come out
C with an unwanted text segment relocation though, even with ".protected".


ASM_START()
	TEXT
	ALIGN(32)
PROLOGUE(mpn_modexact_1_odd)

	movl	$0, %ecx

PROLOGUE(mpn_modexact_1c_odd)

	C rdi	src
	C rsi	size
	C rdx	divisor
	C rcx	carry

	movq	%rdx, %r8		C d
	shrl	%edx			C d/2
ifdef(`PIC',`
	movq	binvert_limb_table@@GOTPCREL(%rip), %r9
',`
	movabsq	$binvert_limb_table, %r9
')

	andl	$127, %edx
	movq	%rcx, %r10		C initial carry

	movzbl	(%r9,%rdx), %edx	C inv 8 bits

	movq	(%rdi), %rax		C src[0]
	leaq	(%rdi,%rsi,8), %r11	C src end
	movq	%r8, %rdi		C d, made available to imull

	leal	(%rdx,%rdx), %ecx	C 2*inv
	imull	%edx, %edx		C inv*inv

	negq	%rsi			C -size

	imull	%edi, %edx		C inv*inv*d

	subl	%edx, %ecx		C inv = 2*inv - inv*inv*d, 16 bits

	leal	(%rcx,%rcx), %edx	C 2*inv
	imull	%ecx, %ecx		C inv*inv

	imull	%edi, %ecx		C inv*inv*d

	subl	%ecx, %edx		C inv = 2*inv - inv*inv*d, 32 bits
	xorl	%ecx, %ecx		C initial cbit

	leaq	(%rdx,%rdx), %r9	C 2*inv
	imulq	%rdx, %rdx		C inv*inv

	imulq	%r8, %rdx		C inv*inv*d

	subq	%rdx, %r9		C inv = 2*inv - inv*inv*d, 64 bits
	movq	%r10, %rdx		C initial climb

	ASSERT(e,`	C d*inv == 1 mod 2^64
	movq	%r8, %r10
	imulq	%r9, %r10
	cmpq	$1, %r10')

	incq	%rsi
	jz	L(one)


	ALIGN(16)
L(top):
	C rax	l = src[i]-cbit
	C rcx	new cbit, 0 or 1
	C rdx	climb, high of last product
	C rsi	counter, limbs, negative
	C rdi
	C r8	divisor
	C r9	inverse
	C r11	src end ptr

	subq	%rdx, %rax		C l = src[i]-cbit - climb

	adcq	$0, %rcx		C more cbit
	imulq	%r9, %rax		C q = l * inverse

	mulq	%r8			C climb = high (q * d)

	movq	(%r11,%rsi,8), %rax	C src[i+1]
	subq	%rcx, %rax		C next l = src[i+1] - cbit
	setc	%cl			C new cbit

	incq	%rsi
	jnz	L(top)


L(one):
	subq	%rdx, %rax		C l = src[i]-cbit - climb

	adcq	$0, %rcx		C more cbit
	imulq	%r9, %rax		C q = l * inverse

	mulq	%r8			C climb = high (q * d)

	leaq	(%rcx,%rdx), %rax	C climb+cbit
	ret

EPILOGUE(mpn_modexact_1c_odd)
EPILOGUE(mpn_modexact_1_odd)
@


1.1.1.1
log
@initial import of GMP 5.0.2.

GNU MP is a library for arbitrary precision arithmetic, operating on signed
integers, rational numbers, and floating point numbers.  It has a rich set
of functions, and the functions have a regular interface.

GMP is necessary for GCC >= 4.2.
@
text
@@


1.1.1.1.8.1
log
@Rebase to HEAD as of a few days ago.
@
text
@d1 1
a1 4
dnl  AMD64 mpn_modexact_1_odd -- Hensel norm remainder.

dnl  Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2011, 2012 Free
dnl  Software Foundation, Inc.
d3 3
d7 11
a17 11

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

d25 6
a30 7
C AMD K8,K9	10
C AMD K10	10
C Intel P4	33
C Intel core2	13
C Intel corei	14.5
C Intel atom	35
C VIA nano	 ?
d33 6
d42 3
a44 3
C	sub	%rdx, %rax	1
C	imul	%r9, %rax	4
C	mul	%r8		5
d48 10
a57 3
C The mov load from src seems to need to be scheduled back before the jz to
C achieve this speed, out-of-order execution apparently can't completely hide
C the latency otherwise.
d59 1
a59 2
C The l=src[i]-cbit step is rotated back too, since that allows us to avoid it
C for the first iteration (where there's no cbit).
d61 13
a73 4
C The code alignment used (32-byte) for the loop also seems necessary.  Without
C that the non-PIC case has adc crossing the 0x60 offset, apparently making it
C run at 11 cycles instead of 10.

a74 2
ABI_SUPPORT(DOS64)
ABI_SUPPORT(STD64)
d80 2
a81 3
	FUNC_ENTRY(3)
	mov	$0, R32(%rcx)
IFDOS(`	jmp	L(ent)		')
d84 1
a84 2
	FUNC_ENTRY(4)
L(ent):
d90 7
a96 4
	mov	%rdx, %r8		C d
	shr	R32(%rdx)		C d/2

	LEA(	binvert_limb_table, %r9)
d98 2
a99 2
	and	$127, R32(%rdx)
	mov	%rcx, %r10		C initial carry
d101 1
a101 1
	movzbl	(%r9,%rdx), R32(%rdx)	C inv 8 bits
d103 3
a105 3
	mov	(%rdi), %rax		C src[0]
	lea	(%rdi,%rsi,8), %r11	C src end
	mov	%r8, %rdi		C d, made available to imull
d107 2
a108 2
	lea	(%rdx,%rdx), R32(%rcx)	C 2*inv
	imul	R32(%rdx), R32(%rdx)	C inv*inv
d110 1
a110 1
	neg	%rsi			C -size
d112 1
a112 1
	imul	R32(%rdi), R32(%rdx)	C inv*inv*d
d114 1
a114 1
	sub	R32(%rdx), R32(%rcx)	C inv = 2*inv - inv*inv*d, 16 bits
d116 2
a117 2
	lea	(%rcx,%rcx), R32(%rdx)	C 2*inv
	imul	R32(%rcx), R32(%rcx)	C inv*inv
d119 1
a119 1
	imul	R32(%rdi), R32(%rcx)	C inv*inv*d
d121 2
a122 2
	sub	R32(%rcx), R32(%rdx)	C inv = 2*inv - inv*inv*d, 32 bits
	xor	R32(%rcx), R32(%rcx)	C initial cbit
d124 2
a125 2
	lea	(%rdx,%rdx), %r9	C 2*inv
	imul	%rdx, %rdx		C inv*inv
d127 1
a127 1
	imul	%r8, %rdx		C inv*inv*d
d129 2
a130 2
	sub	%rdx, %r9		C inv = 2*inv - inv*inv*d, 64 bits
	mov	%r10, %rdx		C initial climb
d133 3
a135 3
	mov	%r8, %r10
	imul	%r9, %r10
	cmp	$1, %r10')
d137 1
a137 1
	inc	%rsi
d152 1
a152 1
	sub	%rdx, %rax		C l = src[i]-cbit - climb
d154 2
a155 2
	adc	$0, %rcx		C more cbit
	imul	%r9, %rax		C q = l * inverse
d157 1
a157 1
	mul	%r8			C climb = high (q * d)
d159 3
a161 3
	mov	(%r11,%rsi,8), %rax	C src[i+1]
	sub	%rcx, %rax		C next l = src[i+1] - cbit
	setc	R8(%rcx)		C new cbit
d163 1
a163 1
	inc	%rsi
d168 1
a168 1
	sub	%rdx, %rax		C l = src[i]-cbit - climb
d170 2
a171 2
	adc	$0, %rcx		C more cbit
	imul	%r9, %rax		C q = l * inverse
d173 1
a173 1
	mul	%r8			C climb = high (q * d)
d175 1
a175 2
	lea	(%rcx,%rdx), %rax	C climb+cbit
	FUNC_EXIT()
@


1.1.1.1.2.1
log
@sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")
@
text
@d1 1
a1 4
dnl  AMD64 mpn_modexact_1_odd -- Hensel norm remainder.

dnl  Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2011, 2012 Free
dnl  Software Foundation, Inc.
d3 3
d7 11
a17 11

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

d25 6
a30 7
C AMD K8,K9	10
C AMD K10	10
C Intel P4	33
C Intel core2	13
C Intel corei	14.5
C Intel atom	35
C VIA nano	 ?
d33 6
d42 3
a44 3
C	sub	%rdx, %rax	1
C	imul	%r9, %rax	4
C	mul	%r8		5
d48 10
a57 3
C The mov load from src seems to need to be scheduled back before the jz to
C achieve this speed, out-of-order execution apparently can't completely hide
C the latency otherwise.
d59 1
a59 2
C The l=src[i]-cbit step is rotated back too, since that allows us to avoid it
C for the first iteration (where there's no cbit).
d61 13
a73 4
C The code alignment used (32-byte) for the loop also seems necessary.  Without
C that the non-PIC case has adc crossing the 0x60 offset, apparently making it
C run at 11 cycles instead of 10.

a74 2
ABI_SUPPORT(DOS64)
ABI_SUPPORT(STD64)
d80 2
a81 3
	FUNC_ENTRY(3)
	mov	$0, R32(%rcx)
IFDOS(`	jmp	L(ent)		')
d84 1
a84 2
	FUNC_ENTRY(4)
L(ent):
d90 7
a96 4
	mov	%rdx, %r8		C d
	shr	R32(%rdx)		C d/2

	LEA(	binvert_limb_table, %r9)
d98 2
a99 2
	and	$127, R32(%rdx)
	mov	%rcx, %r10		C initial carry
d101 1
a101 1
	movzbl	(%r9,%rdx), R32(%rdx)	C inv 8 bits
d103 3
a105 3
	mov	(%rdi), %rax		C src[0]
	lea	(%rdi,%rsi,8), %r11	C src end
	mov	%r8, %rdi		C d, made available to imull
d107 2
a108 2
	lea	(%rdx,%rdx), R32(%rcx)	C 2*inv
	imul	R32(%rdx), R32(%rdx)	C inv*inv
d110 1
a110 1
	neg	%rsi			C -size
d112 1
a112 1
	imul	R32(%rdi), R32(%rdx)	C inv*inv*d
d114 1
a114 1
	sub	R32(%rdx), R32(%rcx)	C inv = 2*inv - inv*inv*d, 16 bits
d116 2
a117 2
	lea	(%rcx,%rcx), R32(%rdx)	C 2*inv
	imul	R32(%rcx), R32(%rcx)	C inv*inv
d119 1
a119 1
	imul	R32(%rdi), R32(%rcx)	C inv*inv*d
d121 2
a122 2
	sub	R32(%rcx), R32(%rdx)	C inv = 2*inv - inv*inv*d, 32 bits
	xor	R32(%rcx), R32(%rcx)	C initial cbit
d124 2
a125 2
	lea	(%rdx,%rdx), %r9	C 2*inv
	imul	%rdx, %rdx		C inv*inv
d127 1
a127 1
	imul	%r8, %rdx		C inv*inv*d
d129 2
a130 2
	sub	%rdx, %r9		C inv = 2*inv - inv*inv*d, 64 bits
	mov	%r10, %rdx		C initial climb
d133 3
a135 3
	mov	%r8, %r10
	imul	%r9, %r10
	cmp	$1, %r10')
d137 1
a137 1
	inc	%rsi
d152 1
a152 1
	sub	%rdx, %rax		C l = src[i]-cbit - climb
d154 2
a155 2
	adc	$0, %rcx		C more cbit
	imul	%r9, %rax		C q = l * inverse
d157 1
a157 1
	mul	%r8			C climb = high (q * d)
d159 3
a161 3
	mov	(%r11,%rsi,8), %rax	C src[i+1]
	sub	%rcx, %rax		C next l = src[i+1] - cbit
	setc	R8(%rcx)		C new cbit
d163 1
a163 1
	inc	%rsi
d168 1
a168 1
	sub	%rdx, %rax		C l = src[i]-cbit - climb
d170 2
a171 2
	adc	$0, %rcx		C more cbit
	imul	%r9, %rax		C q = l * inverse
d173 1
a173 1
	mul	%r8			C climb = high (q * d)
d175 1
a175 2
	lea	(%rcx,%rdx), %rax	C climb+cbit
	FUNC_EXIT()
@


1.1.1.2
log
@initial import GMP 5.1.3 sources.  changes include:

fixes for:
- mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec
- mpz_powm_ui
- AMD family 11h
- mpz_powm_sec and mpn_powm_sec
- ASSERT() fixes
- gcd, gcdext, and invert function fixes
- some PPC division operations
@
text
@d1 1
a1 4
dnl  AMD64 mpn_modexact_1_odd -- Hensel norm remainder.

dnl  Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2011, 2012 Free
dnl  Software Foundation, Inc.
d3 3
d7 11
a17 11

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

d25 6
a30 7
C AMD K8,K9	10
C AMD K10	10
C Intel P4	33
C Intel core2	13
C Intel corei	14.5
C Intel atom	35
C VIA nano	 ?
d33 6
d42 3
a44 3
C	sub	%rdx, %rax	1
C	imul	%r9, %rax	4
C	mul	%r8		5
d48 10
a57 3
C The mov load from src seems to need to be scheduled back before the jz to
C achieve this speed, out-of-order execution apparently can't completely hide
C the latency otherwise.
d59 1
a59 2
C The l=src[i]-cbit step is rotated back too, since that allows us to avoid it
C for the first iteration (where there's no cbit).
d61 13
a73 4
C The code alignment used (32-byte) for the loop also seems necessary.  Without
C that the non-PIC case has adc crossing the 0x60 offset, apparently making it
C run at 11 cycles instead of 10.

a74 2
ABI_SUPPORT(DOS64)
ABI_SUPPORT(STD64)
d80 2
a81 3
	FUNC_ENTRY(3)
	mov	$0, R32(%rcx)
IFDOS(`	jmp	L(ent)		')
d84 1
a84 2
	FUNC_ENTRY(4)
L(ent):
d90 7
a96 4
	mov	%rdx, %r8		C d
	shr	R32(%rdx)		C d/2

	LEA(	binvert_limb_table, %r9)
d98 2
a99 2
	and	$127, R32(%rdx)
	mov	%rcx, %r10		C initial carry
d101 1
a101 1
	movzbl	(%r9,%rdx), R32(%rdx)	C inv 8 bits
d103 3
a105 3
	mov	(%rdi), %rax		C src[0]
	lea	(%rdi,%rsi,8), %r11	C src end
	mov	%r8, %rdi		C d, made available to imull
d107 2
a108 2
	lea	(%rdx,%rdx), R32(%rcx)	C 2*inv
	imul	R32(%rdx), R32(%rdx)	C inv*inv
d110 1
a110 1
	neg	%rsi			C -size
d112 1
a112 1
	imul	R32(%rdi), R32(%rdx)	C inv*inv*d
d114 1
a114 1
	sub	R32(%rdx), R32(%rcx)	C inv = 2*inv - inv*inv*d, 16 bits
d116 2
a117 2
	lea	(%rcx,%rcx), R32(%rdx)	C 2*inv
	imul	R32(%rcx), R32(%rcx)	C inv*inv
d119 1
a119 1
	imul	R32(%rdi), R32(%rcx)	C inv*inv*d
d121 2
a122 2
	sub	R32(%rcx), R32(%rdx)	C inv = 2*inv - inv*inv*d, 32 bits
	xor	R32(%rcx), R32(%rcx)	C initial cbit
d124 2
a125 2
	lea	(%rdx,%rdx), %r9	C 2*inv
	imul	%rdx, %rdx		C inv*inv
d127 1
a127 1
	imul	%r8, %rdx		C inv*inv*d
d129 2
a130 2
	sub	%rdx, %r9		C inv = 2*inv - inv*inv*d, 64 bits
	mov	%r10, %rdx		C initial climb
d133 3
a135 3
	mov	%r8, %r10
	imul	%r9, %r10
	cmp	$1, %r10')
d137 1
a137 1
	inc	%rsi
d152 1
a152 1
	sub	%rdx, %rax		C l = src[i]-cbit - climb
d154 2
a155 2
	adc	$0, %rcx		C more cbit
	imul	%r9, %rax		C q = l * inverse
d157 1
a157 1
	mul	%r8			C climb = high (q * d)
d159 3
a161 3
	mov	(%r11,%rsi,8), %rax	C src[i+1]
	sub	%rcx, %rax		C next l = src[i+1] - cbit
	setc	R8(%rcx)		C new cbit
d163 1
a163 1
	inc	%rsi
d168 1
a168 1
	sub	%rdx, %rax		C l = src[i]-cbit - climb
d170 2
a171 2
	adc	$0, %rcx		C more cbit
	imul	%r9, %rax		C q = l * inverse
d173 1
a173 1
	mul	%r8			C climb = high (q * d)
d175 1
a175 2
	lea	(%rcx,%rdx), %rax	C climb+cbit
	FUNC_EXIT()
@


1.1.1.3
log
@initial import of GMP 6.1.2.  main changes from 5.1.3 below.

notes:
 - support for thumb-less ARM chips was in our port of 5.1.3, but a
   similar method has been provided upstream now
 - someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

  FEATURES
  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
    on Skylake Pentiums).
  * Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

  BUGS FIXED
  * The public function mpn_com is now correctly declared in gmp.h.
  * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
    some obsolete CPUs.
  * Various problems related to precision for mpf have been fixed.
  * Fixed ABI incompatible stack alignment in calls from assembly code.
  * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
  SPEEDUPS
  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    new ADX instructions.
  * Square root is now faster when the remainder is not needed. Also the speed
    to compute the k-th root improved, for small sizes.
  FEATURES
  * New C++ functions gcd and lcm for mpz_class.
  * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
  * New public mpq_cmp_z function, to efficiently compare rationals with
    integers.
  * Support for more 32-bit arm processors.
  * Support for AVX-less modern x86 CPUs. (Such support might be missing either
    because the CPU vendor chose to disable AVX, or because the running kernel
    lacks AVX context switch support.)
  * Support for NetBSD under Xen; we switch off AVX unconditionally under
    NetBSD since a bug in NetBSD makes AVX fail under Xen.
  MISC
  * Tuned values for FFT multiplications are provided for larger number on
    many platforms.

Changes between GMP version 5.1.* and 6.0.0
  BUGS FIXED
  * The function mpz_invert now considers any number invertible in Z/1Z.
  * The mpn multiply code now handles operands of more than 2^31 limbs
    correctly.  (Note however that the mpz code is limited to 2^32 bits on
    32-bit hosts and 2^37 bits on 64-bit hosts.)
  SPEEDUPS
  * Plain division of large operands is faster and more monotonous in operand
    size.
  * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
    assembly.
  * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
    and vastly expanded assembly support.  Speedup also for the older Core 2
    and Nehalem.
  * Faster mixed arithmetic between mpq_class and double.
  FEATURES
  * Support for new Intel and AMD CPUs.
  * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
    silent multiplication and squaring.
  * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
    side-channel silent division.
  * New public functions mpn_cnd_add_n and mpn_cnd_sub_n.  Side-channel silent
    conditional addition and subtraction.
  * New public function mpn_sec_powm, implementing side-channel silent modexp.
  * New public function mpn_sec_invert, implementing side-channel silent
    modular inversion.
  * Better support for applications which use the mpz_t type, but nevertheless
    need to call some of the lower-level mpn functions.  See the documentation
    for mpz_limbs_read and related functions.
@
text
@d3 2
a4 1
dnl  Copyright 2000-2006, 2011, 2012 Free Software Foundation, Inc.
d7 1
a7 1
dnl
d9 4
a12 14
dnl  it under the terms of either:
dnl
dnl    * the GNU Lesser General Public License as published by the Free
dnl      Software Foundation; either version 3 of the License, or (at your
dnl      option) any later version.
dnl
dnl  or
dnl
dnl    * the GNU General Public License as published by the Free Software
dnl      Foundation; either version 2 of the License, or (at your option) any
dnl      later version.
dnl
dnl  or both in parallel, as here.
dnl
d15 5
a19 6
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
dnl  for more details.
dnl
dnl  You should have received copies of the GNU General Public License and the
dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
dnl  see https://www.gnu.org/licenses/.
@