head	1.1;
branch	1.1.1;
access;
symbols
	netbsd-11-0-RC5:1.1.1.3
	netbsd-11-0-RC4:1.1.1.3
	netbsd-11-0-RC3:1.1.1.3
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	netbsd-7-0-1-RELEASE:1.1.1.1
	netbsd-7-0:1.1.1.1.0.10
	netbsd-7-0-RELEASE:1.1.1.1
	netbsd-7-0-RC3:1.1.1.1
	netbsd-7-0-RC2:1.1.1.1
	netbsd-7-0-RC1:1.1.1.1
	tls-maxphys-base:1.1.1.1
	tls-maxphys:1.1.1.1.0.8
	netbsd-7:1.1.1.1.0.6
	netbsd-7-base:1.1.1.1
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	gmp-5-1-3:1.1.1.1
	gmp:1.1.1;
locks; strict;
comment	@;; @;


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desc
@@


1.1
log
@Initial revision
@
text
@dnl  AMD64 mpn_copyi optimised for CPUs with fast SSE copying and SSSE3.

dnl  Copyright 2012 Free Software Foundation, Inc.

dnl  Contributed to the GNU project by Torbjorn Granlund.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C	     cycles/limb     cycles/limb     cycles/limb      good
C              aligned	      unaligned	      best seen	     for cpu?
C AMD K8,K9	 2.0		 illop		1.0/1.0		N
C AMD K10	 0.85		 illop				Y/N
C AMD bd1	 1.39		 ? 1.45				Y/N
C AMD bobcat	 1.97		 ? 8.17		1.5/1.5		N
C Intel P4	 2.26		 illop				Y/N
C Intel core2	 0.52		 0.82		opt/0.74	Y
C Intel NHM	 0.52		 0.65		opt/opt		Y
C Intel SBR	 0.51		 0.55		opt/0.51	Y
C Intel atom	 1.16		 1.70		opt/opt		Y
C VIA nano	 1.09		 1.10		opt/opt		Y

C We use only 16-byte operations, except for unaligned top-most and bottom-most
C limbs.  We use the SSSE3 palignr instruction when rp - up = 8 (mod 16).  That
C instruction is better adapted to mpn_copyd's needs, we need to contort the
C code to use it here.
C
C For operands of < COPYI_SSE_THRESHOLD limbs, we use a plain 64-bit loop,
C taken from the x86_64 default code.

C INPUT PARAMETERS
define(`rp', `%rdi')
define(`up', `%rsi')
define(`n',  `%rdx')

C There are three instructions for loading an aligned 128-bit quantity.  We use
C movaps, since it has the shortest coding.
define(`movdqa', ``movaps'')

ifdef(`COPYI_SSE_THRESHOLD',`',`define(`COPYI_SSE_THRESHOLD', 7)')

ASM_START()
	TEXT
	ALIGN(64)
PROLOGUE(mpn_copyi)
	FUNC_ENTRY(3)

	cmp	$COPYI_SSE_THRESHOLD, n
	jbe	L(bc)

	bt	$3, R32(rp)		C is rp 16-byte aligned?
	jnc	L(rp_aligned)		C jump if rp aligned

	movsq				C copy one limb
	dec	n

L(rp_aligned):
	bt	$3, R32(up)
	jc	L(uent)

ifelse(eval(COPYI_SSE_THRESHOLD >= 8),1,
`	sub	$8, n',
`	jmp	L(am)')

	ALIGN(16)
L(atop):movdqa	0(up), %xmm0
	movdqa	16(up), %xmm1
	movdqa	32(up), %xmm2
	movdqa	48(up), %xmm3
	lea	64(up), up
	movdqa	%xmm0, (rp)
	movdqa	%xmm1, 16(rp)
	movdqa	%xmm2, 32(rp)
	movdqa	%xmm3, 48(rp)
	lea	64(rp), rp
L(am):	sub	$8, n
	jnc	L(atop)

	bt	$2, R32(n)
	jnc	1f
	movdqa	(up), %xmm0
	movdqa	16(up), %xmm1
	lea	32(up), up
	movdqa	%xmm0, (rp)
	movdqa	%xmm1, 16(rp)
	lea	32(rp), rp

1:	bt	$1, R32(n)
	jnc	1f
	movdqa	(up), %xmm0
	lea	16(up), up
	movdqa	%xmm0, (rp)
	lea	16(rp), rp

1:	bt	$0, n
	jnc	1f
	mov	(up), %r8
	mov	%r8, (rp)

1:	FUNC_EXIT()
	ret

L(uent):
C Code handling up - rp = 8 (mod 16)

C FIXME: The code below only handles overlap if it is close to complete, or
C quite separate: up-rp < 5 or up-up > 15 limbs
	lea	-40(up), %rax		C 40 = 5 * GMP_LIMB_BYTES
	sub	rp, %rax
	cmp	$80, %rax		C 80 = (15-5) * GMP_LIMB_BYTES
	jbe	L(bc)			C deflect to plain loop

	sub	$16, n
	jc	L(uend)

	movdqa	120(up), %xmm3

	sub	$16, n
	jmp	L(um)

	ALIGN(16)
L(utop):movdqa	120(up), %xmm3
	movdqa	%xmm0, -128(rp)
	sub	$16, n
L(um):	movdqa	104(up), %xmm2
	palignr($8, %xmm2, %xmm3)
	movdqa	88(up), %xmm1
	movdqa	%xmm3, 112(rp)
	palignr($8, %xmm1, %xmm2)
	movdqa	72(up), %xmm0
	movdqa	%xmm2, 96(rp)
	palignr($8, %xmm0, %xmm1)
	movdqa	56(up), %xmm3
	movdqa	%xmm1, 80(rp)
	palignr($8, %xmm3, %xmm0)
	movdqa	40(up), %xmm2
	movdqa	%xmm0, 64(rp)
	palignr($8, %xmm2, %xmm3)
	movdqa	24(up), %xmm1
	movdqa	%xmm3, 48(rp)
	palignr($8, %xmm1, %xmm2)
	movdqa	8(up), %xmm0
	movdqa	%xmm2, 32(rp)
	palignr($8, %xmm0, %xmm1)
	movdqa	-8(up), %xmm3
	movdqa	%xmm1, 16(rp)
	palignr($8, %xmm3, %xmm0)
	lea	128(up), up
	lea	128(rp), rp
	jnc	L(utop)

	movdqa	%xmm0, -128(rp)

L(uend):bt	$3, R32(n)
	jnc	1f
	movdqa	56(up), %xmm3
	movdqa	40(up), %xmm2
	palignr($8, %xmm2, %xmm3)
	movdqa	24(up), %xmm1
	movdqa	%xmm3, 48(rp)
	palignr($8, %xmm1, %xmm2)
	movdqa	8(up), %xmm0
	movdqa	%xmm2, 32(rp)
	palignr($8, %xmm0, %xmm1)
	movdqa	-8(up), %xmm3
	movdqa	%xmm1, 16(rp)
	palignr($8, %xmm3, %xmm0)
	lea	64(up), up
	movdqa	%xmm0, (rp)
	lea	64(rp), rp

1:	bt	$2, R32(n)
	jnc	1f
	movdqa	24(up), %xmm1
	movdqa	8(up), %xmm0
	palignr($8, %xmm0, %xmm1)
	movdqa	-8(up), %xmm3
	movdqa	%xmm1, 16(rp)
	palignr($8, %xmm3, %xmm0)
	lea	32(up), up
	movdqa	%xmm0, (rp)
	lea	32(rp), rp

1:	bt	$1, R32(n)
	jnc	1f
	movdqa	8(up), %xmm0
	movdqa	-8(up), %xmm3
	palignr($8, %xmm3, %xmm0)
	lea	16(up), up
	movdqa	%xmm0, (rp)
	lea	16(rp), rp

1:	bt	$0, n
	jnc	1f
	mov	(up), %r8
	mov	%r8, (rp)

1:	FUNC_EXIT()
	ret

C Basecase code.  Needed for good small operands speed, not for
C correctness as the above code is currently written.

L(bc):	lea	-8(rp), rp
	sub	$4, R32(n)
	jc	L(end)

	ALIGN(16)
L(top):	mov	(up), %r8
	mov	8(up), %r9
	lea	32(rp), rp
	mov	16(up), %r10
	mov	24(up), %r11
	lea	32(up), up
	mov	%r8, -24(rp)
	mov	%r9, -16(rp)
ifelse(eval(1 || COPYI_SSE_THRESHOLD >= 8),1,
`	sub	$4, R32(n)')
	mov	%r10, -8(rp)
	mov	%r11, (rp)
ifelse(eval(1 || COPYI_SSE_THRESHOLD >= 8),1,
`	jnc	L(top)')

L(end):	bt	$0, R32(n)
	jnc	1f
	mov	(up), %r8
	mov	%r8, 8(rp)
	lea	8(rp), rp
	lea	8(up), up
1:	bt	$1, R32(n)
	jnc	1f
	mov	(up), %r8
	mov	8(up), %r9
	mov	%r8, 8(rp)
	mov	%r9, 16(rp)
1:	FUNC_EXIT()
	ret
EPILOGUE()
@


1.1.1.1
log
@initial import GMP 5.1.3 sources.  changes include:

fixes for:
- mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec
- mpz_powm_ui
- AMD family 11h
- mpz_powm_sec and mpn_powm_sec
- ASSERT() fixes
- gcd, gcdext, and invert function fixes
- some PPC division operations
@
text
@@


1.1.1.2
log
@initial import of GMP 6.1.2.  main changes from 5.1.3 below.

notes:
 - support for thumb-less ARM chips was in our port of 5.1.3, but a
   similar method has been provided upstream now
 - someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

  FEATURES
  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
    on Skylake Pentiums).
  * Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

  BUGS FIXED
  * The public function mpn_com is now correctly declared in gmp.h.
  * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
    some obsolete CPUs.
  * Various problems related to precision for mpf have been fixed.
  * Fixed ABI incompatible stack alignment in calls from assembly code.
  * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
  SPEEDUPS
  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    new ADX instructions.
  * Square root is now faster when the remainder is not needed. Also the speed
    to compute the k-th root improved, for small sizes.
  FEATURES
  * New C++ functions gcd and lcm for mpz_class.
  * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
  * New public mpq_cmp_z function, to efficiently compare rationals with
    integers.
  * Support for more 32-bit arm processors.
  * Support for AVX-less modern x86 CPUs. (Such support might be missing either
    because the CPU vendor chose to disable AVX, or because the running kernel
    lacks AVX context switch support.)
  * Support for NetBSD under Xen; we switch off AVX unconditionally under
    NetBSD since a bug in NetBSD makes AVX fail under Xen.
  MISC
  * Tuned values for FFT multiplications are provided for larger number on
    many platforms.

Changes between GMP version 5.1.* and 6.0.0
  BUGS FIXED
  * The function mpz_invert now considers any number invertible in Z/1Z.
  * The mpn multiply code now handles operands of more than 2^31 limbs
    correctly.  (Note however that the mpz code is limited to 2^32 bits on
    32-bit hosts and 2^37 bits on 64-bit hosts.)
  SPEEDUPS
  * Plain division of large operands is faster and more monotonous in operand
    size.
  * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
    assembly.
  * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
    and vastly expanded assembly support.  Speedup also for the older Core 2
    and Nehalem.
  * Faster mixed arithmetic between mpq_class and double.
  FEATURES
  * Support for new Intel and AMD CPUs.
  * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
    silent multiplication and squaring.
  * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
    side-channel silent division.
  * New public functions mpn_cnd_add_n and mpn_cnd_sub_n.  Side-channel silent
    conditional addition and subtraction.
  * New public function mpn_sec_powm, implementing side-channel silent modexp.
  * New public function mpn_sec_invert, implementing side-channel silent
    modular inversion.
  * Better support for applications which use the mpz_t type, but nevertheless
    need to call some of the lower-level mpn functions.  See the documentation
    for mpz_limbs_read and related functions.
@
text
@d3 1
a3 1
dnl  Copyright 2012, 2013, 2015 Free Software Foundation, Inc.
d5 1
a5 1
dnl  Contributed to the GNU project by Torbjörn Granlund.
d8 1
a8 1
dnl
d10 4
a13 14
dnl  it under the terms of either:
dnl
dnl    * the GNU Lesser General Public License as published by the Free
dnl      Software Foundation; either version 3 of the License, or (at your
dnl      option) any later version.
dnl
dnl  or
dnl
dnl    * the GNU General Public License as published by the Free Software
dnl      Foundation; either version 2 of the License, or (at your option) any
dnl      later version.
dnl
dnl  or both in parallel, as here.
dnl
d16 5
a20 6
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
dnl  for more details.
dnl
dnl  You should have received copies of the GNU General Public License and the
dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
dnl  see https://www.gnu.org/licenses/.
d28 2
a29 6
C AMD bull	 0.70		 0.66				Y
C AMD pile	 0.68		 0.66				Y
C AMD steam	 ?		 ?
C AMD excavator	 ?		 ?
C AMD bobcat	 1.97		 8.16		1.5/1.5		N
C AMD jaguar	 0.77		 0.93		0.65/opt	N/Y
d31 5
a35 9
C Intel core	 0.52		 0.64		opt/opt		Y
C Intel NHM	 0.52		 0.71		opt/opt		Y
C Intel SBR	 0.51		 0.54		opt/0.51	Y
C Intel IBR	 0.50		 0.54		opt/opt		Y
C Intel HWL	 0.50		 0.51		opt/opt		Y
C Intel BWL	 0.55		 0.55		opt/opt		Y
C Intel atom	 1.16		 1.61		opt/opt		Y
C Intel SLM	 1.02		 1.07		opt/opt		Y
C VIA nano	 1.09		 1.08		opt/opt		Y
d52 1
a52 1
dnl define(`movdqa', ``movaps'')
d65 2
a66 2
	test	$8, R8(rp)		C is rp 16-byte aligned?
	jz	L(rp_aligned)		C jump if rp aligned
d72 2
a73 2
	test	$8, R8(up)
	jnz	L(uent)
d93 2
a94 2
	test	$4, R8(n)
	jz	1f
d102 2
a103 2
1:	test	$2, R8(n)
	jz	1f
d109 2
a110 2
1:	test	$1, R8(n)
	jz	1f
d120 11
a130 2
	cmp	$16, n
	jc	L(ued0)
d132 2
a133 14
IFDOS(`	add	$-56, %rsp	')
IFDOS(`	movdqa	%xmm6, (%rsp)	')
IFDOS(`	movdqa	%xmm7, 16(%rsp)	')
IFDOS(`	movdqa	%xmm8, 32(%rsp)	')

	movaps	120(up), %xmm7
	movaps	104(up), %xmm6
	movaps	88(up), %xmm5
	movaps	72(up), %xmm4
	movaps	56(up), %xmm3
	movaps	40(up), %xmm2
	lea	128(up), up
	sub	$32, n
	jc	L(ued1)
d136 2
a137 1
L(utop):movaps	-104(up), %xmm1
d139 1
a139 13
	movaps	-120(up), %xmm0
	palignr($8, %xmm6, %xmm7)
	movaps	-136(up), %xmm8
	movdqa	%xmm7, 112(rp)
	palignr($8, %xmm5, %xmm6)
	movaps	120(up), %xmm7
	movdqa	%xmm6, 96(rp)
	palignr($8, %xmm4, %xmm5)
	movaps	104(up), %xmm6
	movdqa	%xmm5, 80(rp)
	palignr($8, %xmm3, %xmm4)
	movaps	88(up), %xmm5
	movdqa	%xmm4, 64(rp)
d141 13
a153 1
	movaps	72(up), %xmm4
d156 1
a156 1
	movaps	56(up), %xmm3
d159 1
a159 1
	movaps	40(up), %xmm2
d161 1
a161 1
	palignr($8, %xmm8, %xmm0)
a162 1
	movdqa	%xmm0, (rp)
d166 1
a166 20
L(ued1):movaps	-104(up), %xmm1
	movaps	-120(up), %xmm0
	movaps	-136(up), %xmm8
	palignr($8, %xmm6, %xmm7)
	movdqa	%xmm7, 112(rp)
	palignr($8, %xmm5, %xmm6)
	movdqa	%xmm6, 96(rp)
	palignr($8, %xmm4, %xmm5)
	movdqa	%xmm5, 80(rp)
	palignr($8, %xmm3, %xmm4)
	movdqa	%xmm4, 64(rp)
	palignr($8, %xmm2, %xmm3)
	movdqa	%xmm3, 48(rp)
	palignr($8, %xmm1, %xmm2)
	movdqa	%xmm2, 32(rp)
	palignr($8, %xmm0, %xmm1)
	movdqa	%xmm1, 16(rp)
	palignr($8, %xmm8, %xmm0)
	movdqa	%xmm0, (rp)
	lea	128(rp), rp
d168 4
a171 12
IFDOS(`	movdqa	(%rsp), %xmm6	')
IFDOS(`	movdqa	16(%rsp), %xmm7	')
IFDOS(`	movdqa	32(%rsp), %xmm8	')
IFDOS(`	add	$56, %rsp	')

L(ued0):test	$8, R8(n)
	jz	1f
	movaps	56(up), %xmm3
	movaps	40(up), %xmm2
	movaps	24(up), %xmm1
	movaps	8(up), %xmm0
	movaps	-8(up), %xmm4
d173 1
d176 1
d179 1
d181 1
a181 1
	palignr($8, %xmm4, %xmm0)
d186 4
a189 4
1:	test	$4, R8(n)
	jz	1f
	movaps	24(up), %xmm1
	movaps	8(up), %xmm0
d191 1
a191 1
	movaps	-8(up), %xmm3
d198 2
a199 2
1:	test	$2, R8(n)
	jz	1f
d207 2
a208 2
1:	test	$1, R8(n)
	jz	1f
d231 1
a231 1
ifelse(eval(COPYI_SSE_THRESHOLD >= 8),1,
d235 1
a235 1
ifelse(eval(COPYI_SSE_THRESHOLD >= 8),1,
d238 2
a239 2
L(end):	test	$1, R8(n)
	jz	1f
d244 2
a245 2
1:	test	$2, R8(n)
	jz	1f
@


1.1.1.3
log
@initial import of GMP 6.2.0.  changes include:

- Bug fixes to gmp_snprintf, conversion to double, mpz_powm,
  and mpf_set_str.
- New functions for factorial, primorial, fibonacci, mpz_2fac_ui,
  and mpz_mfac_uiui.
- MIPS r6 cores are now supported.
- Various speeds ups.
@
text
@d39 6
a44 8
C AMD bd1	 0.70		 0.66				Y
C AMD bd2	 0.68		 0.66				Y
C AMD bd3	 ?		 ?
C AMD bd4	 ?		 ?
C AMD bt1	 1.97		 8.16		1.5/1.5		N
C AMD bt2	 0.77		 0.93		0.65/opt	N/Y
C AMD zn1	 ?		 ?
C AMD zn2	 ?		 ?
d46 2
a47 2
C Intel CNR	 0.52		 0.64		opt/opt		Y
C Intel NHM	 0.52		 0.71		0.50/0.67	N
@


1.1.1.1.8.1
log
@file copyi-palignr.asm was added on branch tls-maxphys on 2014-08-19 23:59:56 +0000
@
text
@d1 252
@


1.1.1.1.8.2
log
@Rebase to HEAD as of a few days ago.
@
text
@a0 252
dnl  AMD64 mpn_copyi optimised for CPUs with fast SSE copying and SSSE3.

dnl  Copyright 2012 Free Software Foundation, Inc.

dnl  Contributed to the GNU project by Torbjorn Granlund.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C	     cycles/limb     cycles/limb     cycles/limb      good
C              aligned	      unaligned	      best seen	     for cpu?
C AMD K8,K9	 2.0		 illop		1.0/1.0		N
C AMD K10	 0.85		 illop				Y/N
C AMD bd1	 1.39		 ? 1.45				Y/N
C AMD bobcat	 1.97		 ? 8.17		1.5/1.5		N
C Intel P4	 2.26		 illop				Y/N
C Intel core2	 0.52		 0.82		opt/0.74	Y
C Intel NHM	 0.52		 0.65		opt/opt		Y
C Intel SBR	 0.51		 0.55		opt/0.51	Y
C Intel atom	 1.16		 1.70		opt/opt		Y
C VIA nano	 1.09		 1.10		opt/opt		Y

C We use only 16-byte operations, except for unaligned top-most and bottom-most
C limbs.  We use the SSSE3 palignr instruction when rp - up = 8 (mod 16).  That
C instruction is better adapted to mpn_copyd's needs, we need to contort the
C code to use it here.
C
C For operands of < COPYI_SSE_THRESHOLD limbs, we use a plain 64-bit loop,
C taken from the x86_64 default code.

C INPUT PARAMETERS
define(`rp', `%rdi')
define(`up', `%rsi')
define(`n',  `%rdx')

C There are three instructions for loading an aligned 128-bit quantity.  We use
C movaps, since it has the shortest coding.
define(`movdqa', ``movaps'')

ifdef(`COPYI_SSE_THRESHOLD',`',`define(`COPYI_SSE_THRESHOLD', 7)')

ASM_START()
	TEXT
	ALIGN(64)
PROLOGUE(mpn_copyi)
	FUNC_ENTRY(3)

	cmp	$COPYI_SSE_THRESHOLD, n
	jbe	L(bc)

	bt	$3, R32(rp)		C is rp 16-byte aligned?
	jnc	L(rp_aligned)		C jump if rp aligned

	movsq				C copy one limb
	dec	n

L(rp_aligned):
	bt	$3, R32(up)
	jc	L(uent)

ifelse(eval(COPYI_SSE_THRESHOLD >= 8),1,
`	sub	$8, n',
`	jmp	L(am)')

	ALIGN(16)
L(atop):movdqa	0(up), %xmm0
	movdqa	16(up), %xmm1
	movdqa	32(up), %xmm2
	movdqa	48(up), %xmm3
	lea	64(up), up
	movdqa	%xmm0, (rp)
	movdqa	%xmm1, 16(rp)
	movdqa	%xmm2, 32(rp)
	movdqa	%xmm3, 48(rp)
	lea	64(rp), rp
L(am):	sub	$8, n
	jnc	L(atop)

	bt	$2, R32(n)
	jnc	1f
	movdqa	(up), %xmm0
	movdqa	16(up), %xmm1
	lea	32(up), up
	movdqa	%xmm0, (rp)
	movdqa	%xmm1, 16(rp)
	lea	32(rp), rp

1:	bt	$1, R32(n)
	jnc	1f
	movdqa	(up), %xmm0
	lea	16(up), up
	movdqa	%xmm0, (rp)
	lea	16(rp), rp

1:	bt	$0, n
	jnc	1f
	mov	(up), %r8
	mov	%r8, (rp)

1:	FUNC_EXIT()
	ret

L(uent):
C Code handling up - rp = 8 (mod 16)

C FIXME: The code below only handles overlap if it is close to complete, or
C quite separate: up-rp < 5 or up-up > 15 limbs
	lea	-40(up), %rax		C 40 = 5 * GMP_LIMB_BYTES
	sub	rp, %rax
	cmp	$80, %rax		C 80 = (15-5) * GMP_LIMB_BYTES
	jbe	L(bc)			C deflect to plain loop

	sub	$16, n
	jc	L(uend)

	movdqa	120(up), %xmm3

	sub	$16, n
	jmp	L(um)

	ALIGN(16)
L(utop):movdqa	120(up), %xmm3
	movdqa	%xmm0, -128(rp)
	sub	$16, n
L(um):	movdqa	104(up), %xmm2
	palignr($8, %xmm2, %xmm3)
	movdqa	88(up), %xmm1
	movdqa	%xmm3, 112(rp)
	palignr($8, %xmm1, %xmm2)
	movdqa	72(up), %xmm0
	movdqa	%xmm2, 96(rp)
	palignr($8, %xmm0, %xmm1)
	movdqa	56(up), %xmm3
	movdqa	%xmm1, 80(rp)
	palignr($8, %xmm3, %xmm0)
	movdqa	40(up), %xmm2
	movdqa	%xmm0, 64(rp)
	palignr($8, %xmm2, %xmm3)
	movdqa	24(up), %xmm1
	movdqa	%xmm3, 48(rp)
	palignr($8, %xmm1, %xmm2)
	movdqa	8(up), %xmm0
	movdqa	%xmm2, 32(rp)
	palignr($8, %xmm0, %xmm1)
	movdqa	-8(up), %xmm3
	movdqa	%xmm1, 16(rp)
	palignr($8, %xmm3, %xmm0)
	lea	128(up), up
	lea	128(rp), rp
	jnc	L(utop)

	movdqa	%xmm0, -128(rp)

L(uend):bt	$3, R32(n)
	jnc	1f
	movdqa	56(up), %xmm3
	movdqa	40(up), %xmm2
	palignr($8, %xmm2, %xmm3)
	movdqa	24(up), %xmm1
	movdqa	%xmm3, 48(rp)
	palignr($8, %xmm1, %xmm2)
	movdqa	8(up), %xmm0
	movdqa	%xmm2, 32(rp)
	palignr($8, %xmm0, %xmm1)
	movdqa	-8(up), %xmm3
	movdqa	%xmm1, 16(rp)
	palignr($8, %xmm3, %xmm0)
	lea	64(up), up
	movdqa	%xmm0, (rp)
	lea	64(rp), rp

1:	bt	$2, R32(n)
	jnc	1f
	movdqa	24(up), %xmm1
	movdqa	8(up), %xmm0
	palignr($8, %xmm0, %xmm1)
	movdqa	-8(up), %xmm3
	movdqa	%xmm1, 16(rp)
	palignr($8, %xmm3, %xmm0)
	lea	32(up), up
	movdqa	%xmm0, (rp)
	lea	32(rp), rp

1:	bt	$1, R32(n)
	jnc	1f
	movdqa	8(up), %xmm0
	movdqa	-8(up), %xmm3
	palignr($8, %xmm3, %xmm0)
	lea	16(up), up
	movdqa	%xmm0, (rp)
	lea	16(rp), rp

1:	bt	$0, n
	jnc	1f
	mov	(up), %r8
	mov	%r8, (rp)

1:	FUNC_EXIT()
	ret

C Basecase code.  Needed for good small operands speed, not for
C correctness as the above code is currently written.

L(bc):	lea	-8(rp), rp
	sub	$4, R32(n)
	jc	L(end)

	ALIGN(16)
L(top):	mov	(up), %r8
	mov	8(up), %r9
	lea	32(rp), rp
	mov	16(up), %r10
	mov	24(up), %r11
	lea	32(up), up
	mov	%r8, -24(rp)
	mov	%r9, -16(rp)
ifelse(eval(1 || COPYI_SSE_THRESHOLD >= 8),1,
`	sub	$4, R32(n)')
	mov	%r10, -8(rp)
	mov	%r11, (rp)
ifelse(eval(1 || COPYI_SSE_THRESHOLD >= 8),1,
`	jnc	L(top)')

L(end):	bt	$0, R32(n)
	jnc	1f
	mov	(up), %r8
	mov	%r8, 8(rp)
	lea	8(rp), rp
	lea	8(up), up
1:	bt	$1, R32(n)
	jnc	1f
	mov	(up), %r8
	mov	8(up), %r9
	mov	%r8, 8(rp)
	mov	%r9, 16(rp)
1:	FUNC_EXIT()
	ret
EPILOGUE()
@


1.1.1.1.4.1
log
@file copyi-palignr.asm was added on branch yamt-pagecache on 2014-05-22 14:09:07 +0000
@
text
@d1 252
@


1.1.1.1.4.2
log
@sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")
@
text
@a0 252
dnl  AMD64 mpn_copyi optimised for CPUs with fast SSE copying and SSSE3.

dnl  Copyright 2012 Free Software Foundation, Inc.

dnl  Contributed to the GNU project by Torbjorn Granlund.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C	     cycles/limb     cycles/limb     cycles/limb      good
C              aligned	      unaligned	      best seen	     for cpu?
C AMD K8,K9	 2.0		 illop		1.0/1.0		N
C AMD K10	 0.85		 illop				Y/N
C AMD bd1	 1.39		 ? 1.45				Y/N
C AMD bobcat	 1.97		 ? 8.17		1.5/1.5		N
C Intel P4	 2.26		 illop				Y/N
C Intel core2	 0.52		 0.82		opt/0.74	Y
C Intel NHM	 0.52		 0.65		opt/opt		Y
C Intel SBR	 0.51		 0.55		opt/0.51	Y
C Intel atom	 1.16		 1.70		opt/opt		Y
C VIA nano	 1.09		 1.10		opt/opt		Y

C We use only 16-byte operations, except for unaligned top-most and bottom-most
C limbs.  We use the SSSE3 palignr instruction when rp - up = 8 (mod 16).  That
C instruction is better adapted to mpn_copyd's needs, we need to contort the
C code to use it here.
C
C For operands of < COPYI_SSE_THRESHOLD limbs, we use a plain 64-bit loop,
C taken from the x86_64 default code.

C INPUT PARAMETERS
define(`rp', `%rdi')
define(`up', `%rsi')
define(`n',  `%rdx')

C There are three instructions for loading an aligned 128-bit quantity.  We use
C movaps, since it has the shortest coding.
define(`movdqa', ``movaps'')

ifdef(`COPYI_SSE_THRESHOLD',`',`define(`COPYI_SSE_THRESHOLD', 7)')

ASM_START()
	TEXT
	ALIGN(64)
PROLOGUE(mpn_copyi)
	FUNC_ENTRY(3)

	cmp	$COPYI_SSE_THRESHOLD, n
	jbe	L(bc)

	bt	$3, R32(rp)		C is rp 16-byte aligned?
	jnc	L(rp_aligned)		C jump if rp aligned

	movsq				C copy one limb
	dec	n

L(rp_aligned):
	bt	$3, R32(up)
	jc	L(uent)

ifelse(eval(COPYI_SSE_THRESHOLD >= 8),1,
`	sub	$8, n',
`	jmp	L(am)')

	ALIGN(16)
L(atop):movdqa	0(up), %xmm0
	movdqa	16(up), %xmm1
	movdqa	32(up), %xmm2
	movdqa	48(up), %xmm3
	lea	64(up), up
	movdqa	%xmm0, (rp)
	movdqa	%xmm1, 16(rp)
	movdqa	%xmm2, 32(rp)
	movdqa	%xmm3, 48(rp)
	lea	64(rp), rp
L(am):	sub	$8, n
	jnc	L(atop)

	bt	$2, R32(n)
	jnc	1f
	movdqa	(up), %xmm0
	movdqa	16(up), %xmm1
	lea	32(up), up
	movdqa	%xmm0, (rp)
	movdqa	%xmm1, 16(rp)
	lea	32(rp), rp

1:	bt	$1, R32(n)
	jnc	1f
	movdqa	(up), %xmm0
	lea	16(up), up
	movdqa	%xmm0, (rp)
	lea	16(rp), rp

1:	bt	$0, n
	jnc	1f
	mov	(up), %r8
	mov	%r8, (rp)

1:	FUNC_EXIT()
	ret

L(uent):
C Code handling up - rp = 8 (mod 16)

C FIXME: The code below only handles overlap if it is close to complete, or
C quite separate: up-rp < 5 or up-up > 15 limbs
	lea	-40(up), %rax		C 40 = 5 * GMP_LIMB_BYTES
	sub	rp, %rax
	cmp	$80, %rax		C 80 = (15-5) * GMP_LIMB_BYTES
	jbe	L(bc)			C deflect to plain loop

	sub	$16, n
	jc	L(uend)

	movdqa	120(up), %xmm3

	sub	$16, n
	jmp	L(um)

	ALIGN(16)
L(utop):movdqa	120(up), %xmm3
	movdqa	%xmm0, -128(rp)
	sub	$16, n
L(um):	movdqa	104(up), %xmm2
	palignr($8, %xmm2, %xmm3)
	movdqa	88(up), %xmm1
	movdqa	%xmm3, 112(rp)
	palignr($8, %xmm1, %xmm2)
	movdqa	72(up), %xmm0
	movdqa	%xmm2, 96(rp)
	palignr($8, %xmm0, %xmm1)
	movdqa	56(up), %xmm3
	movdqa	%xmm1, 80(rp)
	palignr($8, %xmm3, %xmm0)
	movdqa	40(up), %xmm2
	movdqa	%xmm0, 64(rp)
	palignr($8, %xmm2, %xmm3)
	movdqa	24(up), %xmm1
	movdqa	%xmm3, 48(rp)
	palignr($8, %xmm1, %xmm2)
	movdqa	8(up), %xmm0
	movdqa	%xmm2, 32(rp)
	palignr($8, %xmm0, %xmm1)
	movdqa	-8(up), %xmm3
	movdqa	%xmm1, 16(rp)
	palignr($8, %xmm3, %xmm0)
	lea	128(up), up
	lea	128(rp), rp
	jnc	L(utop)

	movdqa	%xmm0, -128(rp)

L(uend):bt	$3, R32(n)
	jnc	1f
	movdqa	56(up), %xmm3
	movdqa	40(up), %xmm2
	palignr($8, %xmm2, %xmm3)
	movdqa	24(up), %xmm1
	movdqa	%xmm3, 48(rp)
	palignr($8, %xmm1, %xmm2)
	movdqa	8(up), %xmm0
	movdqa	%xmm2, 32(rp)
	palignr($8, %xmm0, %xmm1)
	movdqa	-8(up), %xmm3
	movdqa	%xmm1, 16(rp)
	palignr($8, %xmm3, %xmm0)
	lea	64(up), up
	movdqa	%xmm0, (rp)
	lea	64(rp), rp

1:	bt	$2, R32(n)
	jnc	1f
	movdqa	24(up), %xmm1
	movdqa	8(up), %xmm0
	palignr($8, %xmm0, %xmm1)
	movdqa	-8(up), %xmm3
	movdqa	%xmm1, 16(rp)
	palignr($8, %xmm3, %xmm0)
	lea	32(up), up
	movdqa	%xmm0, (rp)
	lea	32(rp), rp

1:	bt	$1, R32(n)
	jnc	1f
	movdqa	8(up), %xmm0
	movdqa	-8(up), %xmm3
	palignr($8, %xmm3, %xmm0)
	lea	16(up), up
	movdqa	%xmm0, (rp)
	lea	16(rp), rp

1:	bt	$0, n
	jnc	1f
	mov	(up), %r8
	mov	%r8, (rp)

1:	FUNC_EXIT()
	ret

C Basecase code.  Needed for good small operands speed, not for
C correctness as the above code is currently written.

L(bc):	lea	-8(rp), rp
	sub	$4, R32(n)
	jc	L(end)

	ALIGN(16)
L(top):	mov	(up), %r8
	mov	8(up), %r9
	lea	32(rp), rp
	mov	16(up), %r10
	mov	24(up), %r11
	lea	32(up), up
	mov	%r8, -24(rp)
	mov	%r9, -16(rp)
ifelse(eval(1 || COPYI_SSE_THRESHOLD >= 8),1,
`	sub	$4, R32(n)')
	mov	%r10, -8(rp)
	mov	%r11, (rp)
ifelse(eval(1 || COPYI_SSE_THRESHOLD >= 8),1,
`	jnc	L(top)')

L(end):	bt	$0, R32(n)
	jnc	1f
	mov	(up), %r8
	mov	%r8, 8(rp)
	lea	8(rp), rp
	lea	8(up), up
1:	bt	$1, R32(n)
	jnc	1f
	mov	(up), %r8
	mov	8(up), %r9
	mov	%r8, 8(rp)
	mov	%r9, 16(rp)
1:	FUNC_EXIT()
	ret
EPILOGUE()
@