head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC5:1.1.1.2 netbsd-11-0-RC4:1.1.1.2 netbsd-11-0-RC3:1.1.1.2 netbsd-11-0-RC2:1.1.1.2 netbsd-11-0-RC1:1.1.1.2 perseant-exfatfs-base-20250801:1.1.1.2 netbsd-11:1.1.1.2.0.18 netbsd-11-base:1.1.1.2 netbsd-10-1-RELEASE:1.1.1.2 perseant-exfatfs-base-20240630:1.1.1.2 perseant-exfatfs:1.1.1.2.0.16 perseant-exfatfs-base:1.1.1.2 netbsd-8-3-RELEASE:1.1.1.1 netbsd-9-4-RELEASE:1.1.1.2 netbsd-10-0-RELEASE:1.1.1.2 netbsd-10-0-RC6:1.1.1.2 netbsd-10-0-RC5:1.1.1.2 netbsd-10-0-RC4:1.1.1.2 netbsd-10-0-RC3:1.1.1.2 netbsd-10-0-RC2:1.1.1.2 netbsd-10-0-RC1:1.1.1.2 netbsd-10:1.1.1.2.0.14 netbsd-10-base:1.1.1.2 netbsd-9-3-RELEASE:1.1.1.2 gmp-6-2-1:1.1.1.2 cjep_sun2x-base1:1.1.1.2 cjep_sun2x:1.1.1.2.0.12 cjep_sun2x-base:1.1.1.2 cjep_staticlib_x-base1:1.1.1.2 netbsd-9-2-RELEASE:1.1.1.2 cjep_staticlib_x:1.1.1.2.0.10 cjep_staticlib_x-base:1.1.1.2 netbsd-9-1-RELEASE:1.1.1.2 gmp-6-2-0:1.1.1.2 phil-wifi-20200421:1.1.1.2 phil-wifi-20200411:1.1.1.2 is-mlppp:1.1.1.2.0.8 is-mlppp-base:1.1.1.2 phil-wifi-20200406:1.1.1.2 netbsd-8-2-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.2 netbsd-9-0-RC2:1.1.1.2 netbsd-9-0-RC1:1.1.1.2 phil-wifi-20191119:1.1.1.2 netbsd-9:1.1.1.2.0.6 netbsd-9-base:1.1.1.2 phil-wifi-20190609:1.1.1.2 netbsd-8-1-RELEASE:1.1.1.1 netbsd-8-1-RC1:1.1.1.1 pgoyette-compat-merge-20190127:1.1.1.2 pgoyette-compat-20190127:1.1.1.2 pgoyette-compat-20190118:1.1.1.2 pgoyette-compat-1226:1.1.1.2 pgoyette-compat-1126:1.1.1.2 pgoyette-compat-1020:1.1.1.2 pgoyette-compat-0930:1.1.1.2 pgoyette-compat-0906:1.1.1.2 netbsd-7-2-RELEASE:1.1.1.1 pgoyette-compat-0728:1.1.1.2 netbsd-8-0-RELEASE:1.1.1.1 phil-wifi:1.1.1.2.0.4 phil-wifi-base:1.1.1.2 pgoyette-compat-0625:1.1.1.2 netbsd-8-0-RC2:1.1.1.1 pgoyette-compat-0521:1.1.1.2 pgoyette-compat-0502:1.1.1.2 pgoyette-compat-0422:1.1.1.2 netbsd-8-0-RC1:1.1.1.1 pgoyette-compat-0415:1.1.1.2 pgoyette-compat-0407:1.1.1.2 pgoyette-compat-0330:1.1.1.2 pgoyette-compat-0322:1.1.1.2 pgoyette-compat-0315:1.1.1.2 netbsd-7-1-2-RELEASE:1.1.1.1 pgoyette-compat:1.1.1.2.0.2 pgoyette-compat-base:1.1.1.2 netbsd-7-1-1-RELEASE:1.1.1.1 matt-nb8-mediatek:1.1.1.1.0.38 matt-nb8-mediatek-base:1.1.1.1 gmp-6-1-2:1.1.1.2 perseant-stdc-iso10646:1.1.1.1.0.36 perseant-stdc-iso10646-base:1.1.1.1 netbsd-8:1.1.1.1.0.34 netbsd-8-base:1.1.1.1 prg-localcount2-base3:1.1.1.1 prg-localcount2-base2:1.1.1.1 prg-localcount2-base1:1.1.1.1 prg-localcount2:1.1.1.1.0.32 prg-localcount2-base:1.1.1.1 pgoyette-localcount-20170426:1.1.1.1 bouyer-socketcan-base1:1.1.1.1 pgoyette-localcount-20170320:1.1.1.1 netbsd-7-1:1.1.1.1.0.30 netbsd-7-1-RELEASE:1.1.1.1 netbsd-7-1-RC2:1.1.1.1 netbsd-7-nhusb-base-20170116:1.1.1.1 bouyer-socketcan:1.1.1.1.0.28 bouyer-socketcan-base:1.1.1.1 pgoyette-localcount-20170107:1.1.1.1 netbsd-7-1-RC1:1.1.1.1 pgoyette-localcount-20161104:1.1.1.1 netbsd-7-0-2-RELEASE:1.1.1.1 localcount-20160914:1.1.1.1 netbsd-7-nhusb:1.1.1.1.0.26 netbsd-7-nhusb-base:1.1.1.1 pgoyette-localcount-20160806:1.1.1.1 pgoyette-localcount-20160726:1.1.1.1 pgoyette-localcount:1.1.1.1.0.24 pgoyette-localcount-base:1.1.1.1 netbsd-7-0-1-RELEASE:1.1.1.1 netbsd-7-0:1.1.1.1.0.22 netbsd-7-0-RELEASE:1.1.1.1 netbsd-7-0-RC3:1.1.1.1 netbsd-7-0-RC2:1.1.1.1 netbsd-7-0-RC1:1.1.1.1 netbsd-6-0-6-RELEASE:1.1.1.1 netbsd-6-1-5-RELEASE:1.1.1.1 netbsd-7:1.1.1.1.0.20 netbsd-7-base:1.1.1.1 yamt-pagecache-base9:1.1.1.1 yamt-pagecache-tag8:1.1.1.1 netbsd-6-1-4-RELEASE:1.1.1.1 netbsd-6-0-5-RELEASE:1.1.1.1 tls-earlyentropy:1.1.1.1.0.18 tls-earlyentropy-base:1.1.1.1 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.1.1.1 riastradh-drm2-base3:1.1.1.1 netbsd-6-1-3-RELEASE:1.1.1.1 netbsd-6-0-4-RELEASE:1.1.1.1 gmp-5-1-3:1.1.1.1 netbsd-6-1-2-RELEASE:1.1.1.1 netbsd-6-0-3-RELEASE:1.1.1.1 netbsd-6-1-1-RELEASE:1.1.1.1 riastradh-drm2-base2:1.1.1.1 riastradh-drm2-base1:1.1.1.1 riastradh-drm2:1.1.1.1.0.12 riastradh-drm2-base:1.1.1.1 netbsd-6-1:1.1.1.1.0.16 netbsd-6-0-2-RELEASE:1.1.1.1 netbsd-6-1-RELEASE:1.1.1.1 netbsd-6-1-RC4:1.1.1.1 netbsd-6-1-RC3:1.1.1.1 agc-symver:1.1.1.1.0.14 agc-symver-base:1.1.1.1 netbsd-6-1-RC2:1.1.1.1 netbsd-6-1-RC1:1.1.1.1 yamt-pagecache-base8:1.1.1.1 netbsd-6-0-1-RELEASE:1.1.1.1 yamt-pagecache-base7:1.1.1.1 matt-nb6-plus-nbase:1.1.1.1 yamt-pagecache-base6:1.1.1.1 netbsd-6-0:1.1.1.1.0.10 netbsd-6-0-RELEASE:1.1.1.1 netbsd-6-0-RC2:1.1.1.1 tls-maxphys:1.1.1.1.0.8 tls-maxphys-base:1.1.1.1 matt-nb6-plus:1.1.1.1.0.6 matt-nb6-plus-base:1.1.1.1 netbsd-6-0-RC1:1.1.1.1 yamt-pagecache-base5:1.1.1.1 yamt-pagecache-base4:1.1.1.1 netbsd-6:1.1.1.1.0.4 netbsd-6-base:1.1.1.1 yamt-pagecache-base3:1.1.1.1 yamt-pagecache-base2:1.1.1.1 yamt-pagecache:1.1.1.1.0.2 yamt-pagecache-base:1.1.1.1 gmp-5-0-2:1.1.1.1 gmp:1.1.1; locks; strict; comment @;; @; 1.1 date 2011.06.20.05.54.43; author mrg; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2011.06.20.05.54.43; author mrg; state Exp; branches; next 1.1.1.2; 1.1.1.2 date 2017.08.22.09.40.49; author mrg; state Exp; branches; next ; commitid W5kmAIk8hwVpSb4A; desc @@ 1.1 log @Initial revision @ text @dnl mpn_mul_basecase for Pentium 4 and P6 models with SSE2 (i.e., 9,D,E,F). dnl Copyright 2001, 2002, 2005, 2007 Free Software Foundation, Inc. dnl dnl This file is part of the GNU MP Library. dnl dnl The GNU MP Library is free software; you can redistribute it and/or modify dnl it under the terms of the GNU Lesser General Public License as published dnl by the Free Software Foundation; either version 3 of the License, or (at dnl your option) any later version. dnl dnl The GNU MP Library is distributed in the hope that it will be useful, but dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public dnl License for more details. dnl dnl You should have received a copy of the GNU Lesser General Public License dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. include(`../config.m4') C TODO: C * Improve ad-hoc outer loop code and register handling. Some feed-in C scheduling could improve things by several cycles per outer iteration. C * In code for un <= 3, try keeping accumulation operands in registers, C without storing intermediates to rp. C * We might want to keep 32 in a free mm register, since the register form is C 3 bytes and the immediate form is 4 bytes. About 70 bytes to save. C * Look into different loop alignment, we now expand the code about 50 bytes C with possibly needless alignment. C * Perhaps rewrap loops 00,01,02 (6 loops) to allow fall-through entry. C * Use OSP, should solve feed-in latency problems. C * Save a few tens of bytes by doing cross-jumping for Loel0, etc. C * Save around 120 bytes by remapping "m 0", "m 1", "m 2" and "m 3" registers C so that they can share feed-in code, and changing the branch targets from C L to Lm. C cycles/limb C P6 model 9 (Banias) ? C P6 model 13 (Dothan) 5.24 C P6 model 14 (Yonah) ? C P4 model 0-1 (Willamette): 5 C P4 model 2 (Northwood): 4.60 at 32 limbs C P4 model 3-4 (Prescott): 4.94 at 32 limbs C INPUT PARAMETERS C rp sp + 4 C up sp + 8 C un sp + 12 C vp sp + 16 C vn sp + 20 TEXT ALIGN(16) PROLOGUE(mpn_mul_basecase) push %esi push %ebx mov 12(%esp), %edx C rp mov 16(%esp), %eax C up mov 20(%esp), %ecx C un mov 24(%esp), %esi C vp mov 28(%esp), %ebx C vn movd (%esi), %mm7 C L(ent): cmp $3, %ecx ja L(big) movd (%eax), %mm6 pmuludq %mm7, %mm6 jz L(un3) cmp $2, %ecx jz L(un2) L(un1): movd %mm6, (%edx) C un=1 psrlq $32, %mm6 C un=1 movd %mm6, 4(%edx) C un=1 jmp L(rtr) C un=1 L(un2): movd 4(%eax), %mm1 C un=2 pmuludq %mm7, %mm1 C un=2 movd %mm6, (%edx) C un=2 psrlq $32, %mm6 C un=2 paddq %mm1, %mm6 C un=2 movd %mm6, 4(%edx) C un=2 psrlq $32, %mm6 C un=2 movd %mm6, 8(%edx) C un=2 dec %ebx C un=2 jz L(rtr) C un=2 movd 4(%esi), %mm7 C un=2 movd (%eax), %mm6 C un=2 pmuludq %mm7, %mm6 C un=2 movd 4(%eax), %mm1 C un=2 movd 4(%edx), %mm4 C un=2 pmuludq %mm7, %mm1 C un=2 movd 8(%edx), %mm5 C un=2 paddq %mm4, %mm6 C un=2 paddq %mm1, %mm5 C un=2 movd %mm6, 4(%edx) C un=2 psrlq $32, %mm6 C un=2 paddq %mm5, %mm6 C un=2 movd %mm6, 8(%edx) C un=2 psrlq $32, %mm6 C un=2 movd %mm6, 12(%edx) C un=2 L(rtr): emms pop %ebx pop %esi ret L(un3): movd 4(%eax), %mm1 C un=3 pmuludq %mm7, %mm1 C un=3 movd 8(%eax), %mm2 C un=3 pmuludq %mm7, %mm2 C un=3 movd %mm6, (%edx) C un=3 psrlq $32, %mm6 C un=3 paddq %mm1, %mm6 C un=3 movd %mm6, 4(%edx) C un=3 psrlq $32, %mm6 C un=3 paddq %mm2, %mm6 C un=3 movd %mm6, 8(%edx) C un=3 psrlq $32, %mm6 C un=3 movd %mm6, 12(%edx) C un=3 dec %ebx C un=3 jz L(rtr) C un=3 movd 4(%esi), %mm7 C un=3 movd (%eax), %mm6 C un=3 pmuludq %mm7, %mm6 C un=3 movd 4(%eax), %mm1 C un=3 movd 4(%edx), %mm4 C un=3 pmuludq %mm7, %mm1 C un=3 movd 8(%eax), %mm2 C un=3 movd 8(%edx), %mm5 C un=3 pmuludq %mm7, %mm2 C un=3 paddq %mm4, %mm6 C un=3 paddq %mm1, %mm5 C un=3 movd 12(%edx), %mm4 C un=3 movd %mm6, 4(%edx) C un=3 psrlq $32, %mm6 C un=3 paddq %mm5, %mm6 C un=3 paddq %mm2, %mm4 C un=3 movd %mm6, 8(%edx) C un=3 psrlq $32, %mm6 C un=3 paddq %mm4, %mm6 C un=3 movd %mm6, 12(%edx) C un=3 psrlq $32, %mm6 C un=3 movd %mm6, 16(%edx) C un=3 dec %ebx C un=3 jz L(rtr) C un=3 movd 8(%esi), %mm7 C un=3 movd (%eax), %mm6 C un=3 pmuludq %mm7, %mm6 C un=3 movd 4(%eax), %mm1 C un=3 movd 8(%edx), %mm4 C un=3 pmuludq %mm7, %mm1 C un=3 movd 8(%eax), %mm2 C un=3 movd 12(%edx), %mm5 C un=3 pmuludq %mm7, %mm2 C un=3 paddq %mm4, %mm6 C un=3 paddq %mm1, %mm5 C un=3 movd 16(%edx), %mm4 C un=3 movd %mm6, 8(%edx) C un=3 psrlq $32, %mm6 C un=3 paddq %mm5, %mm6 C un=3 paddq %mm2, %mm4 C un=3 movd %mm6, 12(%edx) C un=3 psrlq $32, %mm6 C un=3 paddq %mm4, %mm6 C un=3 movd %mm6, 16(%edx) C un=3 psrlq $32, %mm6 C un=3 movd %mm6, 20(%edx) C un=3 jmp L(rtr) L(big): push %edi pxor %mm6, %mm6 lea 4(%esi), %esi and $3, %ecx jz L(0) cmp $2, %ecx jc L(1) jz L(2) jmp L(3) C FIXME: one case should fall through L(0): movd (%eax), %mm3 C m 0 sub 24(%esp), %ecx C inner loop count m 0 mov %ecx, 24(%esp) C update loop count for later m 0 pmuludq %mm7, %mm3 C m 0 movd 4(%eax), %mm0 C m 0 pmuludq %mm7, %mm0 C m 0 movd 8(%eax), %mm1 C m 0 jmp L(m00) C m 0 ALIGN(16) C m 0 L(lpm0): pmuludq %mm7, %mm4 C m 0 paddq %mm0, %mm6 C m 0 movd (%eax), %mm3 C m 0 movd %mm6, -12(%edx) C m 0 psrlq $32, %mm6 C m 0 pmuludq %mm7, %mm3 C m 0 paddq %mm1, %mm6 C m 0 movd 4(%eax), %mm0 C m 0 movd %mm6, -8(%edx) C m 0 psrlq $32, %mm6 C m 0 pmuludq %mm7, %mm0 C m 0 paddq %mm4, %mm6 C m 0 movd 8(%eax), %mm1 C m 0 movd %mm6, -4(%edx) C m 0 psrlq $32, %mm6 C m 0 L(m00): pmuludq %mm7, %mm1 C m 0 paddq %mm3, %mm6 C m 0 movd 12(%eax), %mm4 C m 0 movd %mm6, (%edx) C m 0 psrlq $32, %mm6 C m 0 lea 16(%eax), %eax C m 0 lea 16(%edx), %edx C m 0 add $4, %ecx C m 0 ja L(lpm0) C m 0 pmuludq %mm7, %mm4 C m 0 paddq %mm0, %mm6 C m 0 movd %mm6, -12(%edx) C m 0 psrlq $32, %mm6 C m 0 paddq %mm1, %mm6 C m 0 mov 16(%esp), %edi C rp 0 jmp L(x0) L(olp0): lea 4(%edi), %edi C am 0 movd (%esi), %mm7 C am 0 lea 4(%esi), %esi C am 0 mov %edi, %edx C rp am 0 mov 20(%esp), %eax C up am 0 movd (%eax), %mm3 C am 0 mov 24(%esp), %ecx C inner loop count am 0 pxor %mm6, %mm6 C am 0 pmuludq %mm7, %mm3 C am 0 movd 4(%eax), %mm0 C am 0 movd (%edx), %mm5 C am 0 pmuludq %mm7, %mm0 C am 0 movd 8(%eax), %mm1 C am 0 paddq %mm3, %mm5 C am 0 movd 4(%edx), %mm4 C am 0 jmp L(am00) C am 0 ALIGN(16) C mm 0 L(lam0): pmuludq %mm7, %mm2 C am 0 paddq %mm4, %mm6 C am 0 movd (%eax), %mm3 C am 0 paddq %mm1, %mm5 C am 0 movd -4(%edx), %mm4 C am 0 movd %mm6, -12(%edx) C am 0 psrlq $32, %mm6 C am 0 pmuludq %mm7, %mm3 C am 0 paddq %mm5, %mm6 C am 0 movd 4(%eax), %mm0 C am 0 paddq %mm2, %mm4 C am 0 movd (%edx), %mm5 C am 0 movd %mm6, -8(%edx) C am 0 psrlq $32, %mm6 C am 0 pmuludq %mm7, %mm0 C am 0 paddq %mm4, %mm6 C am 0 movd 8(%eax), %mm1 C am 0 paddq %mm3, %mm5 C am 0 movd 4(%edx), %mm4 C am 0 movd %mm6, -4(%edx) C am 0 psrlq $32, %mm6 C am 0 L(am00): pmuludq %mm7, %mm1 C am 0 paddq %mm5, %mm6 C am 0 movd 12(%eax), %mm2 C am 0 paddq %mm0, %mm4 C am 0 movd 8(%edx), %mm5 C am 0 movd %mm6, (%edx) C am 0 psrlq $32, %mm6 C am 0 lea 16(%eax), %eax C am 0 lea 16(%edx), %edx C am 0 add $4, %ecx C am 0 jnz L(lam0) C am 0 pmuludq %mm7, %mm2 C am 0 paddq %mm4, %mm6 C am 0 paddq %mm1, %mm5 C am 0 movd -4(%edx), %mm4 C am 0 movd %mm6, -12(%edx) C am 0 psrlq $32, %mm6 C am 0 paddq %mm5, %mm6 C am 0 paddq %mm2, %mm4 C am 0 L(x0): movd %mm6, -8(%edx) C am 0 psrlq $32, %mm6 C am 0 paddq %mm4, %mm6 C am 0 movd %mm6, -4(%edx) C am 0 psrlq $32, %mm6 C am 0 movd %mm6, (%edx) C am 0 dec %ebx C am 0 jnz L(olp0) C am 0 L(oel0): emms C 0 pop %edi C 0 pop %ebx C 0 pop %esi C 0 ret C 0 L(1): movd (%eax), %mm4 C m 1 sub 24(%esp), %ecx C m 1 mov %ecx, 24(%esp) C update loop count for later m 1 pmuludq %mm7, %mm4 C m 1 movd 4(%eax), %mm3 C m 1 pmuludq %mm7, %mm3 C m 1 movd 8(%eax), %mm0 C m 1 jmp L(m01) C m 1 ALIGN(16) C m 1 L(lpm1): pmuludq %mm7, %mm4 C m 1 paddq %mm0, %mm6 C m 1 movd 4(%eax), %mm3 C m 1 movd %mm6, -8(%edx) C m 1 psrlq $32, %mm6 C m 1 pmuludq %mm7, %mm3 C m 1 paddq %mm1, %mm6 C m 1 movd 8(%eax), %mm0 C m 1 movd %mm6, -4(%edx) C m 1 psrlq $32, %mm6 C m 1 L(m01): pmuludq %mm7, %mm0 C m 1 paddq %mm4, %mm6 C m 1 movd 12(%eax), %mm1 C m 1 movd %mm6, (%edx) C m 1 psrlq $32, %mm6 C m 1 pmuludq %mm7, %mm1 C m 1 paddq %mm3, %mm6 C m 1 movd 16(%eax), %mm4 C m 1 movd %mm6, 4(%edx) C m 1 psrlq $32, %mm6 C m 1 lea 16(%eax), %eax C m 1 lea 16(%edx), %edx C m 1 add $4, %ecx C m 1 ja L(lpm1) C m 1 pmuludq %mm7, %mm4 C m 1 paddq %mm0, %mm6 C m 1 movd %mm6, -8(%edx) C m 1 psrlq $32, %mm6 C m 1 paddq %mm1, %mm6 C m 1 mov 16(%esp), %edi C rp 1 jmp L(x1) L(olp1): lea 4(%edi), %edi C am 1 movd (%esi), %mm7 C am 1 lea 4(%esi), %esi C am 1 mov %edi, %edx C rp am 1 mov 20(%esp), %eax C up am 1 movd (%eax), %mm2 C am 1 mov 24(%esp), %ecx C inner loop count am 1 pxor %mm6, %mm6 C am 1 pmuludq %mm7, %mm2 C am 1 movd 4(%eax), %mm3 C am 1 movd (%edx), %mm4 C am 1 pmuludq %mm7, %mm3 C am 1 movd 8(%eax), %mm0 C am 1 paddq %mm2, %mm4 C am 1 movd 4(%edx), %mm5 C am 1 jmp L(am01) C am 1 ALIGN(16) C am 1 L(lam1): pmuludq %mm7, %mm2 C am 1 paddq %mm4, %mm6 C am 1 movd 4(%eax), %mm3 C am 1 paddq %mm1, %mm5 C am 1 movd (%edx), %mm4 C am 1 movd %mm6, -8(%edx) C am 1 psrlq $32, %mm6 C am 1 pmuludq %mm7, %mm3 C am 1 paddq %mm5, %mm6 C am 1 movd 8(%eax), %mm0 C am 1 paddq %mm2, %mm4 C am 1 movd 4(%edx), %mm5 C am 1 movd %mm6, -4(%edx) C am 1 psrlq $32, %mm6 C am 1 L(am01): pmuludq %mm7, %mm0 C am 1 paddq %mm4, %mm6 C am 1 movd 12(%eax), %mm1 C am 1 paddq %mm3, %mm5 C am 1 movd 8(%edx), %mm4 C am 1 movd %mm6, (%edx) C am 1 psrlq $32, %mm6 C am 1 pmuludq %mm7, %mm1 C am 1 paddq %mm5, %mm6 C am 1 movd 16(%eax), %mm2 C am 1 paddq %mm0, %mm4 C am 1 movd 12(%edx), %mm5 C am 1 movd %mm6, 4(%edx) C am 1 psrlq $32, %mm6 C am 1 lea 16(%eax), %eax C am 1 lea 16(%edx), %edx C am 1 add $4, %ecx C am 1 jnz L(lam1) C am 1 pmuludq %mm7, %mm2 C am 1 paddq %mm4, %mm6 C am 1 paddq %mm1, %mm5 C am 1 movd (%edx), %mm4 C am 1 movd %mm6, -8(%edx) C am 1 psrlq $32, %mm6 C am 1 paddq %mm5, %mm6 C am 1 paddq %mm2, %mm4 C am 1 L(x1): movd %mm6, -4(%edx) C am 1 psrlq $32, %mm6 C am 1 paddq %mm4, %mm6 C am 1 movd %mm6, (%edx) C am 1 psrlq $32, %mm6 C am 1 movd %mm6, 4(%edx) C am 1 dec %ebx C am 1 jnz L(olp1) C am 1 L(oel1): emms C 1 pop %edi C 1 pop %ebx C 1 pop %esi C 1 ret C 1 L(2): movd (%eax), %mm1 C m 2 sub 24(%esp), %ecx C m 2 mov %ecx, 24(%esp) C update loop count for later m 2 pmuludq %mm7, %mm1 C m 2 movd 4(%eax), %mm4 C m 2 pmuludq %mm7, %mm4 C m 2 movd 8(%eax), %mm3 C m 2 jmp L(m10) C m 2 ALIGN(16) C m 2 L(lpm2): pmuludq %mm7, %mm4 C m 2 paddq %mm0, %mm6 C m 2 movd 8(%eax), %mm3 C m 2 movd %mm6, -4(%edx) C m 2 psrlq $32, %mm6 C m 2 L(m10): pmuludq %mm7, %mm3 C m 2 paddq %mm1, %mm6 C m 2 movd 12(%eax), %mm0 C m 2 movd %mm6, (%edx) C m 2 psrlq $32, %mm6 C m 2 pmuludq %mm7, %mm0 C m 2 paddq %mm4, %mm6 C m 2 movd 16(%eax), %mm1 C m 2 movd %mm6, 4(%edx) C m 2 psrlq $32, %mm6 C m 2 pmuludq %mm7, %mm1 C m 2 paddq %mm3, %mm6 C m 2 movd 20(%eax), %mm4 C m 2 movd %mm6, 8(%edx) C m 2 psrlq $32, %mm6 C m 2 lea 16(%eax), %eax C m 2 lea 16(%edx), %edx C m 2 add $4, %ecx C m 2 ja L(lpm2) C m 2 pmuludq %mm7, %mm4 C m 2 paddq %mm0, %mm6 C m 2 movd %mm6, -4(%edx) C m 2 psrlq $32, %mm6 C m 2 paddq %mm1, %mm6 C m 2 mov 16(%esp), %edi C rp 2 jmp L(x2) L(olp2): lea 4(%edi), %edi C am 2 movd (%esi), %mm7 C am 2 lea 4(%esi), %esi C am 2 mov %edi, %edx C rp am 2 mov 20(%esp), %eax C up am 2 movd (%eax), %mm1 C am 2 mov 24(%esp), %ecx C inner loop count am 2 pxor %mm6, %mm6 C am 2 pmuludq %mm7, %mm1 C am 2 movd 4(%eax), %mm2 C am 2 movd (%edx), %mm5 C am 2 pmuludq %mm7, %mm2 C am 2 movd 8(%eax), %mm3 C am 2 paddq %mm1, %mm5 C am 2 movd 4(%edx), %mm4 C am 2 jmp L(am10) C am 2 ALIGN(16) C am 2 L(lam2): pmuludq %mm7, %mm2 C am 2 paddq %mm4, %mm6 C am 2 movd 8(%eax), %mm3 C am 2 paddq %mm1, %mm5 C am 2 movd 4(%edx), %mm4 C am 2 movd %mm6, -4(%edx) C am 2 psrlq $32, %mm6 C am 2 L(am10): pmuludq %mm7, %mm3 C am 2 paddq %mm5, %mm6 C am 2 movd 12(%eax), %mm0 C am 2 paddq %mm2, %mm4 C am 2 movd 8(%edx), %mm5 C am 2 movd %mm6, (%edx) C am 2 psrlq $32, %mm6 C am 2 pmuludq %mm7, %mm0 C am 2 paddq %mm4, %mm6 C am 2 movd 16(%eax), %mm1 C am 2 paddq %mm3, %mm5 C am 2 movd 12(%edx), %mm4 C am 2 movd %mm6, 4(%edx) C am 2 psrlq $32, %mm6 C am 2 pmuludq %mm7, %mm1 C am 2 paddq %mm5, %mm6 C am 2 movd 20(%eax), %mm2 C am 2 paddq %mm0, %mm4 C am 2 movd 16(%edx), %mm5 C am 2 movd %mm6, 8(%edx) C am 2 psrlq $32, %mm6 C am 2 lea 16(%eax), %eax C am 2 lea 16(%edx), %edx C am 2 add $4, %ecx C am 2 jnz L(lam2) C am 2 pmuludq %mm7, %mm2 C am 2 paddq %mm4, %mm6 C am 2 paddq %mm1, %mm5 C am 2 movd 4(%edx), %mm4 C am 2 movd %mm6, -4(%edx) C am 2 psrlq $32, %mm6 C am 2 paddq %mm5, %mm6 C am 2 paddq %mm2, %mm4 C am 2 L(x2): movd %mm6, (%edx) C am 2 psrlq $32, %mm6 C am 2 paddq %mm4, %mm6 C am 2 movd %mm6, 4(%edx) C am 2 psrlq $32, %mm6 C am 2 movd %mm6, 8(%edx) C am 2 dec %ebx C am 2 jnz L(olp2) C am 2 L(oel2): emms C 2 pop %edi C 2 pop %ebx C 2 pop %esi C 2 ret C 2 L(3): movd (%eax), %mm0 C m 3 sub 24(%esp), %ecx C m 3 mov %ecx, 24(%esp) C update loop count for later m 3 pmuludq %mm7, %mm0 C m 3 movd 4(%eax), %mm1 C m 3 pmuludq %mm7, %mm1 C m 3 movd 8(%eax), %mm4 C m 3 jmp L(lpm3) C m 3 ALIGN(16) C m 3 L(lpm3): pmuludq %mm7, %mm4 C m 3 paddq %mm0, %mm6 C m 3 movd 12(%eax), %mm3 C m 3 movd %mm6, (%edx) C m 3 psrlq $32, %mm6 C m 3 pmuludq %mm7, %mm3 C m 3 paddq %mm1, %mm6 C m 3 movd 16(%eax), %mm0 C m 3 movd %mm6, 4(%edx) C m 3 psrlq $32, %mm6 C m 3 pmuludq %mm7, %mm0 C m 3 paddq %mm4, %mm6 C m 3 movd 20(%eax), %mm1 C m 3 movd %mm6, 8(%edx) C m 3 psrlq $32, %mm6 C m 3 pmuludq %mm7, %mm1 C m 3 paddq %mm3, %mm6 C m 3 movd 24(%eax), %mm4 C m 3 movd %mm6, 12(%edx) C m 3 psrlq $32, %mm6 C m 3 lea 16(%eax), %eax C m 3 lea 16(%edx), %edx C m 3 add $4, %ecx C m 3 ja L(lpm3) C m 3 pmuludq %mm7, %mm4 C m 3 paddq %mm0, %mm6 C m 3 movd %mm6, (%edx) C m 3 psrlq $32, %mm6 C m 3 paddq %mm1, %mm6 C m 3 mov 16(%esp), %edi C rp 3 jmp L(x3) L(olp3): lea 4(%edi), %edi C am 3 movd (%esi), %mm7 C am 3 lea 4(%esi), %esi C am 3 mov %edi, %edx C rp am 3 mov 20(%esp), %eax C up am 3 movd (%eax), %mm0 C am 3 mov 24(%esp), %ecx C inner loop count am 3 pxor %mm6, %mm6 C am 3 pmuludq %mm7, %mm0 C am 3 movd 4(%eax), %mm1 C am 3 movd (%edx), %mm4 C am 3 pmuludq %mm7, %mm1 C am 3 movd 8(%eax), %mm2 C am 3 paddq %mm0, %mm4 C am 3 movd 4(%edx), %mm5 C am 3 jmp L(lam3) C am 3 ALIGN(16) C am 3 L(lam3): pmuludq %mm7, %mm2 C am 3 paddq %mm4, %mm6 C am 3 movd 12(%eax), %mm3 C am 3 paddq %mm1, %mm5 C am 3 movd 8(%edx), %mm4 C am 3 movd %mm6, (%edx) C am 3 psrlq $32, %mm6 C am 3 pmuludq %mm7, %mm3 C am 3 paddq %mm5, %mm6 C am 3 movd 16(%eax), %mm0 C am 3 paddq %mm2, %mm4 C am 3 movd 12(%edx), %mm5 C am 3 movd %mm6, 4(%edx) C am 3 psrlq $32, %mm6 C am 3 pmuludq %mm7, %mm0 C am 3 paddq %mm4, %mm6 C am 3 movd 20(%eax), %mm1 C am 3 paddq %mm3, %mm5 C am 3 movd 16(%edx), %mm4 C am 3 movd %mm6, 8(%edx) C am 3 psrlq $32, %mm6 C am 3 pmuludq %mm7, %mm1 C am 3 paddq %mm5, %mm6 C am 3 movd 24(%eax), %mm2 C am 3 paddq %mm0, %mm4 C am 3 movd 20(%edx), %mm5 C am 3 movd %mm6, 12(%edx) C am 3 psrlq $32, %mm6 C am 3 lea 16(%eax), %eax C am 3 lea 16(%edx), %edx C am 3 add $4, %ecx C am 3 jnz L(lam3) C am 3 pmuludq %mm7, %mm2 C am 3 paddq %mm4, %mm6 C am 3 paddq %mm1, %mm5 C am 3 movd 8(%edx), %mm4 C am 3 movd %mm6, (%edx) C am 3 psrlq $32, %mm6 C am 3 paddq %mm5, %mm6 C am 3 paddq %mm2, %mm4 C am 3 L(x3): movd %mm6, 4(%edx) C am 3 psrlq $32, %mm6 C am 3 paddq %mm4, %mm6 C am 3 movd %mm6, 8(%edx) C am 3 psrlq $32, %mm6 C am 3 movd %mm6, 12(%edx) C am 3 dec %ebx C am 3 jnz L(olp3) C am 3 L(oel3): emms C 3 pop %edi C 3 pop %ebx C 3 pop %esi C 3 ret C 3 EPILOGUE() @ 1.1.1.1 log @initial import of GMP 5.0.2. GNU MP is a library for arbitrary precision arithmetic, operating on signed integers, rational numbers, and floating point numbers. It has a rich set of functions, and the functions have a regular interface. GMP is necessary for GCC >= 4.2. @ text @@ 1.1.1.2 log @initial import of GMP 6.1.2. main changes from 5.1.3 below. notes: - support for thumb-less ARM chips was in our port of 5.1.3, but a similar method has been provided upstream now - someone should look at the AVX failure reports, and fix them Changes between GMP version 6.1.0 and 6.1.1 FEATURES * Work around faulty cpuid on some recent Intel chips (this allows GMP to run on Skylake Pentiums). * Support thumb-less ARM chips. Changes between GMP version 6.0.* and 6.1.0 BUGS FIXED * The public function mpn_com is now correctly declared in gmp.h. * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for some obsolete CPUs. * Various problems related to precision for mpf have been fixed. * Fixed ABI incompatible stack alignment in calls from assembly code. * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI. SPEEDUPS * Speedup for Intel Broadwell and Skylake through assembly code making use of new ADX instructions. * Square root is now faster when the remainder is not needed. Also the speed to compute the k-th root improved, for small sizes. FEATURES * New C++ functions gcd and lcm for mpz_class. * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap. * New public mpq_cmp_z function, to efficiently compare rationals with integers. * Support for more 32-bit arm processors. * Support for AVX-less modern x86 CPUs. (Such support might be missing either because the CPU vendor chose to disable AVX, or because the running kernel lacks AVX context switch support.) * Support for NetBSD under Xen; we switch off AVX unconditionally under NetBSD since a bug in NetBSD makes AVX fail under Xen. MISC * Tuned values for FFT multiplications are provided for larger number on many platforms. Changes between GMP version 5.1.* and 6.0.0 BUGS FIXED * The function mpz_invert now considers any number invertible in Z/1Z. * The mpn multiply code now handles operands of more than 2^31 limbs correctly. (Note however that the mpz code is limited to 2^32 bits on 32-bit hosts and 2^37 bits on 64-bit hosts.) SPEEDUPS * Plain division of large operands is faster and more monotonous in operand size. * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved assembly. * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten and vastly expanded assembly support. Speedup also for the older Core 2 and Nehalem. * Faster mixed arithmetic between mpq_class and double. FEATURES * Support for new Intel and AMD CPUs. * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel silent multiplication and squaring. * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing side-channel silent division. * New public functions mpn_cnd_add_n and mpn_cnd_sub_n. Side-channel silent conditional addition and subtraction. * New public function mpn_sec_powm, implementing side-channel silent modexp. * New public function mpn_sec_invert, implementing side-channel silent modular inversion. * Better support for applications which use the mpz_t type, but nevertheless need to call some of the lower-level mpn functions. See the documentation for mpz_limbs_read and related functions. @ text @d4 1 a4 1 d8 3 a10 13 dnl it under the terms of either: dnl dnl * the GNU Lesser General Public License as published by the Free dnl Software Foundation; either version 3 of the License, or (at your dnl option) any later version. dnl dnl or dnl dnl * the GNU General Public License as published by the Free Software dnl Foundation; either version 2 of the License, or (at your option) any dnl later version. dnl dnl or both in parallel, as here. d14 2 a15 2 dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License dnl for more details. d17 2 a18 3 dnl You should have received copies of the GNU General Public License and the dnl GNU Lesser General Public License along with the GNU MP Library. If not, dnl see https://www.gnu.org/licenses/. @