head	1.1;
branch	1.1.1;
access;
symbols
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	netbsd-11-0-RC4:1.1.1.3
	netbsd-11-0-RC3:1.1.1.3
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	netbsd-6-0-RC2:1.1.1.1
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	matt-nb6-plus:1.1.1.1.0.6
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	yamt-pagecache-base:1.1.1.1
	gmp-5-0-2:1.1.1.1
	gmp:1.1.1;
locks; strict;
comment	@;; @;


1.1
date	2011.06.20.05.54.42;	author mrg;	state Exp;
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desc
@@


1.1
log
@Initial revision
@
text
@dnl  mpn_mod_1_4 for Pentium 4 and P6 models with SSE2 (i.e., 9,D,E,F).

dnl  Contributed to the GNU project by Torbjorn Granlund.

dnl  Copyright 2009 Free Software Foundation, Inc.
dnl
dnl  This file is part of the GNU MP Library.
dnl
dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.
dnl
dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.
dnl
dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C TODO:
C  * Optimize.  The present code was written quite straightforwardly.
C  * Optimize post-loop reduction code.

C                           cycles/limb
C P6 model 0-8,10-12)           -
C P6 model 9   (Banias)         ?
C P6 model 13  (Dothan)         3.4
C P4 model 0-1 (Willamette):    ?
C P4 model 2   (Northwood):     4
C P4 model 3-4 (Prescott):      ?

C INPUT PARAMETERS
C ap		sp + 4
C n		sp + 8
C b		sp + 12
C cps		sp + 16

define(`B1modb', `%mm1')
define(`B2modb', `%mm2')
define(`B3modb', `%mm3')
define(`B4modb', `%mm4')
define(`B5modb', `%mm5')
define(`ap', `%edx')
define(`n', `%eax')

	TEXT
	ALIGN(16)
PROLOGUE(mpn_mod_1s_4p)
	push	%ebx
	mov	8(%esp), ap
	mov	12(%esp), n
	mov	20(%esp), %ecx

	movd	8(%ecx), B1modb
	movd	12(%ecx), B2modb
	movd	16(%ecx), B3modb
	movd	20(%ecx), B4modb
	movd	24(%ecx), B5modb

	mov	n, %ebx
	lea	-4(ap,n,4), ap
	and	$3, %ebx
	je	L(b0)
	cmp	$2, %ebx
	jc	L(b1)
	je	L(b2)

L(b3):	movd	-4(ap), %mm7
	pmuludq	B1modb, %mm7
	movd	-8(ap), %mm6
	paddq	%mm6, %mm7
	movd	(ap), %mm6
	pmuludq	B2modb, %mm6
	paddq	%mm6, %mm7
	lea	-24(ap), ap
	add	$-3, n
	jz	L(end)
	jmp	L(top)

L(b0):	movd	-8(ap), %mm7
	pmuludq	B1modb, %mm7
	movd	-12(ap), %mm6
	paddq	%mm6, %mm7
	movd	-4(ap), %mm6
	pmuludq	B2modb, %mm6
	paddq	%mm6, %mm7
	movd	(ap), %mm6
	pmuludq	B3modb, %mm6
	paddq	%mm6, %mm7
	lea	-28(ap), ap
	add	$-4, n
	jz	L(end)
	jmp	L(top)

L(b1):	movd	(ap), %mm7
	lea	-16(ap), ap
	dec	n
	jz	L(x)
	jmp	L(top)

L(b2):	movd	(ap), %mm7
	pmuludq	B1modb, %mm7
	movd	-4(ap), %mm6
	paddq	%mm6, %mm7
	lea	-20(ap), ap
	add	$-2, n
	jz	L(end)

	ALIGN(8)
L(top):	movd	4(ap), %mm0
	pmuludq	B1modb, %mm0
	movd	0(ap), %mm6
	paddq	%mm6, %mm0

	movd	8(ap), %mm6
	pmuludq	B2modb, %mm6
	paddq	%mm6, %mm0

	movd	12(ap), %mm6
	pmuludq	B3modb, %mm6
	paddq	%mm6, %mm0

	movq	%mm7, %mm6
	psrlq	$32, %mm7		C rh
	pmuludq	B5modb, %mm7
	pmuludq	B4modb, %mm6

	paddq	%mm0, %mm7
	paddq	%mm6, %mm7

	add	$-16, ap
	add	$-4, n
	jnz	L(top)
L(end):

	pcmpeqd	%mm4, %mm4
	psrlq	$32, %mm4		C 0x00000000FFFFFFFF
	pand	%mm7, %mm4		C rl
	psrlq	$32, %mm7		C rh
	pmuludq	B1modb, %mm7		C rh,cl
	paddq	%mm4, %mm7		C rh,rl

L(x):	movd	4(%ecx), %mm4		C cnt
	psllq	%mm4, %mm7		C rh,rl normalized
	movq	%mm7, %mm2		C rl in low half
	psrlq	$32, %mm7		C rh
	movd	(%ecx), %mm1		C bi
	pmuludq	%mm7, %mm1		C qh,ql
	paddq	%mm2, %mm1		C qh-1,ql
	movd	%mm1, %ecx		C ql
	psrlq	$32, %mm1		C qh-1
	movd	16(%esp), %mm3		C b
	pmuludq	%mm1, %mm3		C (qh-1) * b
	psubq	%mm3, %mm2		C r in low half (could use psubd)
	movd	%mm2, %eax		C r
	mov	16(%esp), %ebx
	sub	%ebx, %eax		C r
	cmp	%eax, %ecx
	lea	(%eax,%ebx), %edx
	cmovc(	%edx, %eax)
	movd	%mm4, %ecx		C cnt
	cmp	%ebx, %eax
	jae	L(fix)
	emms
	pop	%ebx
	shr	%cl, %eax
	ret

L(fix):	sub	%ebx, %eax
	emms
	pop	%ebx
	shr	%cl, %eax
	ret
EPILOGUE()

PROLOGUE(mpn_mod_1s_4p_cps)
	push	%ebp
	push	%edi
	push	%esi
	push	%ebx
	sub	$12, %esp
	mov	36(%esp), %ebx
	bsr	%ebx, %ecx
	xor	$31, %ecx
	mov	%ecx, 4(%esp)
	sal	%cl, %ebx
	mov	%ebx, %edx
	not	%edx
	mov	$-1, %eax
	div	%ebx
	mov	%eax, %esi
	mov	$1, %ebp
	sal	%cl, %ebp
	neg	%ecx
	shr	%cl, %eax
	or	%eax, %ebp
	mov	%ebx, %eax
	neg	%eax
	imul	%ebp, %eax
	mov	%esi, %ecx
	mov	%eax, 8(%esp)
	mul	%ecx
	mov	%edx, %esi
	not	%esi
	sub	8(%esp), %esi
	imul	%ebx, %esi
	lea	(%esi,%ebx), %edx
	cmp	%esi, %eax
	cmovb(	%edx, %esi)
	mov	%esi, %eax
	mul	%ecx
	lea	(%esi,%edx), %edi
	not	%edi
	imul	%ebx, %edi
	lea	(%edi,%ebx), %edx
	cmp	%edi, %eax
	cmovb(	%edx, %edi)
	mov	%edi, %eax
	mul	%ecx
	lea	(%edi,%edx), %ebp
	not	%ebp
	imul	%ebx, %ebp
	lea	(%ebp,%ebx), %edx
	cmp	%ebp, %eax
	cmovb(	%edx, %ebp)
	mov	%ebp, %eax
	mul	%ecx
	add	%ebp, %edx
	not	%edx
	imul	%ebx, %edx
	add	%edx, %ebx
	cmp	%edx, %eax
	cmovb(	%ebx, %edx)
	mov	32(%esp), %eax
	mov	%ecx, (%eax)
	mov	4(%esp), %ecx
	mov	%ecx, 4(%eax)
	mov	8(%esp), %ebx
	shr	%cl, %ebx
	mov	%ebx, 8(%eax)
	shr	%cl, %esi
	mov	%esi, 12(%eax)
	shr	%cl, %edi
	mov	%edi, 16(%eax)
	shr	%cl, %ebp
	mov	%ebp, 20(%eax)
	shr	%cl, %edx
	mov	%edx, 24(%eax)
	add	$12, %esp
	pop	%ebx
	pop	%esi
	pop	%edi
	pop	%ebp
	ret
EPILOGUE()
@


1.1.1.1
log
@initial import of GMP 5.0.2.

GNU MP is a library for arbitrary precision arithmetic, operating on signed
integers, rational numbers, and floating point numbers.  It has a rich set
of functions, and the functions have a regular interface.

GMP is necessary for GCC >= 4.2.
@
text
@@


1.1.1.1.8.1
log
@Rebase to HEAD as of a few days ago.
@
text
@d1 1
a1 1
dnl  x86-32 mpn_mod_1s_4p for Pentium 4 and P6 models with SSE2 (i.e. 9,D,E,F).
d5 1
a5 1
dnl  Copyright 2009, 2010 Free Software Foundation, Inc.
a26 1
C  * Write a cps function that uses sse2 insns.
d28 7
a34 7
C			    cycles/limb
C P6 model 0-8,10-12		-
C P6 model 9   (Banias)		?
C P6 model 13  (Dothan)		3.4
C P4 model 0-1 (Willamette)	?
C P4 model 2   (Northwood)	4
C P4 model 3-4 (Prescott)	4.5
d47 2
a48 2
define(`ap',     `%edx')
define(`n',      `%eax')
a49 1
ASM_START()
d105 4
a108 2
L(b2):	movd	-4(ap), %mm7		C rl
	punpckldq (ap), %mm7		C rh
d138 1
d140 1
a140 1
L(end):	pcmpeqd	%mm4, %mm4
d146 1
a179 1
	ALIGN(16)
a180 1
C CAUTION: This is the same code as in k7/mod_1_4.asm
d185 2
a186 2
	mov	20(%esp), %ebp		C FIXME: avoid bp for 0-idx
	mov	24(%esp), %ebx
d189 2
a190 1
	sal	%cl, %ebx		C b << cnt
d195 27
a221 43
	xor	%edi, %edi
	sub	%ebx, %edi
	mov	$1, %esi
	mov	%eax, (%ebp)		C store bi
	mov	%ecx, 4(%ebp)		C store cnt
	shld	%cl, %eax, %esi
	imul	%edi, %esi
	mov	%eax, %edi
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 8(%ebp)		C store B1modb

	not	%edx
	imul	%ebx, %edx
	lea	(%edx,%ebx), %esi
	cmp	%edx, %eax
	cmovnc(	%edx, %esi)
	mov	%edi, %eax
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 12(%ebp)		C store B2modb

	not	%edx
	imul	%ebx, %edx
	lea	(%edx,%ebx), %esi
	cmp	%edx, %eax
	cmovnc(	%edx, %esi)
	mov	%edi, %eax
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 16(%ebp)		C store B3modb

	not	%edx
	imul	%ebx, %edx
	lea	(%edx,%ebx), %esi
	cmp	%edx, %eax
	cmovnc(	%edx, %esi)
d223 10
a232 6
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 20(%ebp)		C store B4modb

d237 6
a242 2
	cmovnc(	%edx, %ebx)

d244 10
a253 2
	mov	%ebx, 24(%ebp)		C store B5modb

@


1.1.1.1.2.1
log
@sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")
@
text
@d1 1
a1 1
dnl  x86-32 mpn_mod_1s_4p for Pentium 4 and P6 models with SSE2 (i.e. 9,D,E,F).
d5 1
a5 1
dnl  Copyright 2009, 2010 Free Software Foundation, Inc.
a26 1
C  * Write a cps function that uses sse2 insns.
d28 7
a34 7
C			    cycles/limb
C P6 model 0-8,10-12		-
C P6 model 9   (Banias)		?
C P6 model 13  (Dothan)		3.4
C P4 model 0-1 (Willamette)	?
C P4 model 2   (Northwood)	4
C P4 model 3-4 (Prescott)	4.5
d47 2
a48 2
define(`ap',     `%edx')
define(`n',      `%eax')
a49 1
ASM_START()
d105 4
a108 2
L(b2):	movd	-4(ap), %mm7		C rl
	punpckldq (ap), %mm7		C rh
d138 1
d140 1
a140 1
L(end):	pcmpeqd	%mm4, %mm4
d146 1
a179 1
	ALIGN(16)
a180 1
C CAUTION: This is the same code as in k7/mod_1_4.asm
d185 2
a186 2
	mov	20(%esp), %ebp		C FIXME: avoid bp for 0-idx
	mov	24(%esp), %ebx
d189 2
a190 1
	sal	%cl, %ebx		C b << cnt
d195 27
a221 43
	xor	%edi, %edi
	sub	%ebx, %edi
	mov	$1, %esi
	mov	%eax, (%ebp)		C store bi
	mov	%ecx, 4(%ebp)		C store cnt
	shld	%cl, %eax, %esi
	imul	%edi, %esi
	mov	%eax, %edi
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 8(%ebp)		C store B1modb

	not	%edx
	imul	%ebx, %edx
	lea	(%edx,%ebx), %esi
	cmp	%edx, %eax
	cmovnc(	%edx, %esi)
	mov	%edi, %eax
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 12(%ebp)		C store B2modb

	not	%edx
	imul	%ebx, %edx
	lea	(%edx,%ebx), %esi
	cmp	%edx, %eax
	cmovnc(	%edx, %esi)
	mov	%edi, %eax
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 16(%ebp)		C store B3modb

	not	%edx
	imul	%ebx, %edx
	lea	(%edx,%ebx), %esi
	cmp	%edx, %eax
	cmovnc(	%edx, %esi)
d223 10
a232 6
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 20(%ebp)		C store B4modb

d237 6
a242 2
	cmovnc(	%edx, %ebx)

d244 10
a253 2
	mov	%ebx, 24(%ebp)		C store B5modb

@


1.1.1.2
log
@initial import GMP 5.1.3 sources.  changes include:

fixes for:
- mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec
- mpz_powm_ui
- AMD family 11h
- mpz_powm_sec and mpn_powm_sec
- ASSERT() fixes
- gcd, gcdext, and invert function fixes
- some PPC division operations
@
text
@d1 1
a1 1
dnl  x86-32 mpn_mod_1s_4p for Pentium 4 and P6 models with SSE2 (i.e. 9,D,E,F).
d5 1
a5 1
dnl  Copyright 2009, 2010 Free Software Foundation, Inc.
a26 1
C  * Write a cps function that uses sse2 insns.
d28 7
a34 7
C			    cycles/limb
C P6 model 0-8,10-12		-
C P6 model 9   (Banias)		?
C P6 model 13  (Dothan)		3.4
C P4 model 0-1 (Willamette)	?
C P4 model 2   (Northwood)	4
C P4 model 3-4 (Prescott)	4.5
d47 2
a48 2
define(`ap',     `%edx')
define(`n',      `%eax')
a49 1
ASM_START()
d105 4
a108 2
L(b2):	movd	-4(ap), %mm7		C rl
	punpckldq (ap), %mm7		C rh
d138 1
d140 1
a140 1
L(end):	pcmpeqd	%mm4, %mm4
d146 1
a179 1
	ALIGN(16)
a180 1
C CAUTION: This is the same code as in k7/mod_1_4.asm
d185 2
a186 2
	mov	20(%esp), %ebp		C FIXME: avoid bp for 0-idx
	mov	24(%esp), %ebx
d189 2
a190 1
	sal	%cl, %ebx		C b << cnt
d195 27
a221 43
	xor	%edi, %edi
	sub	%ebx, %edi
	mov	$1, %esi
	mov	%eax, (%ebp)		C store bi
	mov	%ecx, 4(%ebp)		C store cnt
	shld	%cl, %eax, %esi
	imul	%edi, %esi
	mov	%eax, %edi
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 8(%ebp)		C store B1modb

	not	%edx
	imul	%ebx, %edx
	lea	(%edx,%ebx), %esi
	cmp	%edx, %eax
	cmovnc(	%edx, %esi)
	mov	%edi, %eax
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 12(%ebp)		C store B2modb

	not	%edx
	imul	%ebx, %edx
	lea	(%edx,%ebx), %esi
	cmp	%edx, %eax
	cmovnc(	%edx, %esi)
	mov	%edi, %eax
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 16(%ebp)		C store B3modb

	not	%edx
	imul	%ebx, %edx
	lea	(%edx,%ebx), %esi
	cmp	%edx, %eax
	cmovnc(	%edx, %esi)
d223 10
a232 6
	mul	%esi

	add	%esi, %edx
	shr	%cl, %esi
	mov	%esi, 20(%ebp)		C store B4modb

d237 6
a242 2
	cmovnc(	%edx, %ebx)

d244 10
a253 2
	mov	%ebx, 24(%ebp)		C store B5modb

@


1.1.1.3
log
@initial import of GMP 6.1.2.  main changes from 5.1.3 below.

notes:
 - support for thumb-less ARM chips was in our port of 5.1.3, but a
   similar method has been provided upstream now
 - someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

  FEATURES
  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
    on Skylake Pentiums).
  * Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

  BUGS FIXED
  * The public function mpn_com is now correctly declared in gmp.h.
  * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
    some obsolete CPUs.
  * Various problems related to precision for mpf have been fixed.
  * Fixed ABI incompatible stack alignment in calls from assembly code.
  * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
  SPEEDUPS
  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    new ADX instructions.
  * Square root is now faster when the remainder is not needed. Also the speed
    to compute the k-th root improved, for small sizes.
  FEATURES
  * New C++ functions gcd and lcm for mpz_class.
  * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
  * New public mpq_cmp_z function, to efficiently compare rationals with
    integers.
  * Support for more 32-bit arm processors.
  * Support for AVX-less modern x86 CPUs. (Such support might be missing either
    because the CPU vendor chose to disable AVX, or because the running kernel
    lacks AVX context switch support.)
  * Support for NetBSD under Xen; we switch off AVX unconditionally under
    NetBSD since a bug in NetBSD makes AVX fail under Xen.
  MISC
  * Tuned values for FFT multiplications are provided for larger number on
    many platforms.

Changes between GMP version 5.1.* and 6.0.0
  BUGS FIXED
  * The function mpz_invert now considers any number invertible in Z/1Z.
  * The mpn multiply code now handles operands of more than 2^31 limbs
    correctly.  (Note however that the mpz code is limited to 2^32 bits on
    32-bit hosts and 2^37 bits on 64-bit hosts.)
  SPEEDUPS
  * Plain division of large operands is faster and more monotonous in operand
    size.
  * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
    assembly.
  * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
    and vastly expanded assembly support.  Speedup also for the older Core 2
    and Nehalem.
  * Faster mixed arithmetic between mpq_class and double.
  FEATURES
  * Support for new Intel and AMD CPUs.
  * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
    silent multiplication and squaring.
  * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
    side-channel silent division.
  * New public functions mpn_cnd_add_n and mpn_cnd_sub_n.  Side-channel silent
    conditional addition and subtraction.
  * New public function mpn_sec_powm, implementing side-channel silent modexp.
  * New public function mpn_sec_invert, implementing side-channel silent
    modular inversion.
  * Better support for applications which use the mpz_t type, but nevertheless
    need to call some of the lower-level mpn functions.  See the documentation
    for mpz_limbs_read and related functions.
@
text
@d6 1
a6 1

d10 3
a12 13
dnl  it under the terms of either:
dnl
dnl    * the GNU Lesser General Public License as published by the Free
dnl      Software Foundation; either version 3 of the License, or (at your
dnl      option) any later version.
dnl
dnl  or
dnl
dnl    * the GNU General Public License as published by the Free Software
dnl      Foundation; either version 2 of the License, or (at your option) any
dnl      later version.
dnl
dnl  or both in parallel, as here.
d16 2
a17 2
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
dnl  for more details.
d19 2
a20 3
dnl  You should have received copies of the GNU General Public License and the
dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
dnl  see https://www.gnu.org/licenses/.
@