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locks; strict; comment @# @; 1.1 date 2011.06.20.05.54.42; author mrg; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2011.06.20.05.54.42; author mrg; state Exp; branches; next 1.1.1.2; 1.1.1.2 date 2017.08.22.09.40.49; author mrg; state Exp; branches; next ; commitid W5kmAIk8hwVpSb4A; desc @@ 1.1 log @Initial revision @ text @Copyright 2001 Free Software Foundation, Inc. This file is part of the GNU MP Library. The GNU MP Library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. The GNU MP Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. INTEL PENTIUM-4 MPN SUBROUTINES This directory contains mpn functions optimized for Intel Pentium-4. The mmx subdirectory has routines using MMX instructions, the sse2 subdirectory has routines using SSE2 instructions. All P4s have these, the separate directories are just so configure can omit that code if the assembler doesn't support it. STATUS cycles/limb mpn_add_n/sub_n 4 normal, 6 in-place mpn_mul_1 4 normal, 6 in-place mpn_addmul_1 6 mpn_submul_1 7 mpn_mul_basecase 6 cycles/crossproduct (approx) mpn_sqr_basecase 3.5 cycles/crossproduct (approx) or 7.0 cycles/triangleproduct (approx) mpn_l/rshift 1.75 The shifts ought to be able to go at 1.5 c/l, but not much effort has been applied to them yet. In-place operations, and all addmul, submul, mul_basecase and sqr_basecase calls, suffer from pipeline anomalies associated with write combining and movd reads and writes to the same or nearby locations. The movq instructions do not trigger the same hardware problems. Unfortunately, using movq and splitting/combining seems to require too many extra instructions to help. Perhaps future chip steppings will be better. NOTES The Pentium-4 pipeline "Netburst", provides for quite a number of surprises. Many traditional x86 instructions run very slowly, requiring use of alterative instructions for acceptable performance. adcl and sbbl are quite slow at 8 cycles for reg->reg. paddq of 32-bits within a 64-bit mmx register seems better, though the combination paddq/psrlq when propagating a carry is still a 4 cycle latency. incl and decl should be avoided, instead use add $1 and sub $1. Apparently the carry flag is not separately renamed, so incl and decl depend on all previous flags-setting instructions. shll and shrl have a 4 cycle latency, or 8 times the latency of the fastest integer instructions (addl, subl, orl, andl, and some more). shldl and shrdl seem to have 13 and 15 cycles latency, respectively. Bizarre. movq mmx -> mmx does have 6 cycle latency, as noted in the documentation. pxor/por or similar combination at 2 cycles latency can be used instead. The movq however executes in the float unit, thereby saving MMX execution resources. With the right juggling, data moves shouldn't be on a dependent chain. L1 is write-through, but the write-combining sounds like it does enough to not require explicit destination prefetching. xmm registers so far haven't found a use, but not much effort has been expended. A configure test for whether the operating system knows fxsave/fxrestor will be needed if they're used. REFERENCES Intel Pentium-4 processor manuals, http://developer.intel.com/design/pentium4/manuals "Intel Pentium 4 Processor Optimization Reference Manual", Intel, 2001, order number 248966. Available on-line: http://developer.intel.com/design/pentium4/manuals/248966.htm ---------------- Local variables: mode: text fill-column: 76 End: @ 1.1.1.1 log @initial import of GMP 5.0.2. GNU MP is a library for arbitrary precision arithmetic, operating on signed integers, rational numbers, and floating point numbers. It has a rich set of functions, and the functions have a regular interface. GMP is necessary for GCC >= 4.2. @ text @@ 1.1.1.2 log @initial import of GMP 6.1.2. main changes from 5.1.3 below. notes: - support for thumb-less ARM chips was in our port of 5.1.3, but a similar method has been provided upstream now - someone should look at the AVX failure reports, and fix them Changes between GMP version 6.1.0 and 6.1.1 FEATURES * Work around faulty cpuid on some recent Intel chips (this allows GMP to run on Skylake Pentiums). * Support thumb-less ARM chips. Changes between GMP version 6.0.* and 6.1.0 BUGS FIXED * The public function mpn_com is now correctly declared in gmp.h. * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for some obsolete CPUs. * Various problems related to precision for mpf have been fixed. * Fixed ABI incompatible stack alignment in calls from assembly code. * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI. SPEEDUPS * Speedup for Intel Broadwell and Skylake through assembly code making use of new ADX instructions. * Square root is now faster when the remainder is not needed. Also the speed to compute the k-th root improved, for small sizes. FEATURES * New C++ functions gcd and lcm for mpz_class. * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap. * New public mpq_cmp_z function, to efficiently compare rationals with integers. * Support for more 32-bit arm processors. * Support for AVX-less modern x86 CPUs. (Such support might be missing either because the CPU vendor chose to disable AVX, or because the running kernel lacks AVX context switch support.) * Support for NetBSD under Xen; we switch off AVX unconditionally under NetBSD since a bug in NetBSD makes AVX fail under Xen. MISC * Tuned values for FFT multiplications are provided for larger number on many platforms. Changes between GMP version 5.1.* and 6.0.0 BUGS FIXED * The function mpz_invert now considers any number invertible in Z/1Z. * The mpn multiply code now handles operands of more than 2^31 limbs correctly. (Note however that the mpz code is limited to 2^32 bits on 32-bit hosts and 2^37 bits on 64-bit hosts.) SPEEDUPS * Plain division of large operands is faster and more monotonous in operand size. * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved assembly. * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten and vastly expanded assembly support. Speedup also for the older Core 2 and Nehalem. * Faster mixed arithmetic between mpq_class and double. FEATURES * Support for new Intel and AMD CPUs. * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel silent multiplication and squaring. * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing side-channel silent division. * New public functions mpn_cnd_add_n and mpn_cnd_sub_n. Side-channel silent conditional addition and subtraction. * New public function mpn_sec_powm, implementing side-channel silent modexp. * New public function mpn_sec_invert, implementing side-channel silent modular inversion. * Better support for applications which use the mpz_t type, but nevertheless need to call some of the lower-level mpn functions. See the documentation for mpz_limbs_read and related functions. @ text @d6 3 a8 13 it under the terms of either: * the GNU Lesser General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. or * the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. or both in parallel, as here. d12 2 a13 2 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. d15 2 a16 3 You should have received copies of the GNU General Public License and the GNU Lesser General Public License along with the GNU MP Library. If not, see https://www.gnu.org/licenses/. @