head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC5:1.1.1.3 netbsd-11-0-RC4:1.1.1.3 netbsd-11-0-RC3:1.1.1.3 netbsd-11-0-RC2:1.1.1.3 netbsd-11-0-RC1:1.1.1.3 perseant-exfatfs-base-20250801:1.1.1.3 netbsd-11:1.1.1.3.0.18 netbsd-11-base:1.1.1.3 netbsd-10-1-RELEASE:1.1.1.3 perseant-exfatfs-base-20240630:1.1.1.3 perseant-exfatfs:1.1.1.3.0.16 perseant-exfatfs-base:1.1.1.3 netbsd-8-3-RELEASE:1.1.1.2 netbsd-9-4-RELEASE:1.1.1.3 netbsd-10-0-RELEASE:1.1.1.3 netbsd-10-0-RC6:1.1.1.3 netbsd-10-0-RC5:1.1.1.3 netbsd-10-0-RC4:1.1.1.3 netbsd-10-0-RC3:1.1.1.3 netbsd-10-0-RC2:1.1.1.3 netbsd-10-0-RC1:1.1.1.3 netbsd-10:1.1.1.3.0.14 netbsd-10-base:1.1.1.3 netbsd-9-3-RELEASE:1.1.1.3 gmp-6-2-1:1.1.1.3 cjep_sun2x-base1:1.1.1.3 cjep_sun2x:1.1.1.3.0.12 cjep_sun2x-base:1.1.1.3 cjep_staticlib_x-base1:1.1.1.3 netbsd-9-2-RELEASE:1.1.1.3 cjep_staticlib_x:1.1.1.3.0.10 cjep_staticlib_x-base:1.1.1.3 netbsd-9-1-RELEASE:1.1.1.3 gmp-6-2-0:1.1.1.3 phil-wifi-20200421:1.1.1.3 phil-wifi-20200411:1.1.1.3 is-mlppp:1.1.1.3.0.8 is-mlppp-base:1.1.1.3 phil-wifi-20200406:1.1.1.3 netbsd-8-2-RELEASE:1.1.1.2 netbsd-9-0-RELEASE:1.1.1.3 netbsd-9-0-RC2:1.1.1.3 netbsd-9-0-RC1:1.1.1.3 phil-wifi-20191119:1.1.1.3 netbsd-9:1.1.1.3.0.6 netbsd-9-base:1.1.1.3 phil-wifi-20190609:1.1.1.3 netbsd-8-1-RELEASE:1.1.1.2 netbsd-8-1-RC1:1.1.1.2 pgoyette-compat-merge-20190127:1.1.1.3 pgoyette-compat-20190127:1.1.1.3 pgoyette-compat-20190118:1.1.1.3 pgoyette-compat-1226:1.1.1.3 pgoyette-compat-1126:1.1.1.3 pgoyette-compat-1020:1.1.1.3 pgoyette-compat-0930:1.1.1.3 pgoyette-compat-0906:1.1.1.3 netbsd-7-2-RELEASE:1.1.1.2 pgoyette-compat-0728:1.1.1.3 netbsd-8-0-RELEASE:1.1.1.2 phil-wifi:1.1.1.3.0.4 phil-wifi-base:1.1.1.3 pgoyette-compat-0625:1.1.1.3 netbsd-8-0-RC2:1.1.1.2 pgoyette-compat-0521:1.1.1.3 pgoyette-compat-0502:1.1.1.3 pgoyette-compat-0422:1.1.1.3 netbsd-8-0-RC1:1.1.1.2 pgoyette-compat-0415:1.1.1.3 pgoyette-compat-0407:1.1.1.3 pgoyette-compat-0330:1.1.1.3 pgoyette-compat-0322:1.1.1.3 pgoyette-compat-0315:1.1.1.3 netbsd-7-1-2-RELEASE:1.1.1.2 pgoyette-compat:1.1.1.3.0.2 pgoyette-compat-base:1.1.1.3 netbsd-7-1-1-RELEASE:1.1.1.2 matt-nb8-mediatek:1.1.1.2.0.22 matt-nb8-mediatek-base:1.1.1.2 gmp-6-1-2:1.1.1.3 perseant-stdc-iso10646:1.1.1.2.0.20 perseant-stdc-iso10646-base:1.1.1.2 netbsd-8:1.1.1.2.0.18 netbsd-8-base:1.1.1.2 prg-localcount2-base3:1.1.1.2 prg-localcount2-base2:1.1.1.2 prg-localcount2-base1:1.1.1.2 prg-localcount2:1.1.1.2.0.16 prg-localcount2-base:1.1.1.2 pgoyette-localcount-20170426:1.1.1.2 bouyer-socketcan-base1:1.1.1.2 pgoyette-localcount-20170320:1.1.1.2 netbsd-7-1:1.1.1.2.0.14 netbsd-7-1-RELEASE:1.1.1.2 netbsd-7-1-RC2:1.1.1.2 netbsd-7-nhusb-base-20170116:1.1.1.2 bouyer-socketcan:1.1.1.2.0.12 bouyer-socketcan-base:1.1.1.2 pgoyette-localcount-20170107:1.1.1.2 netbsd-7-1-RC1:1.1.1.2 pgoyette-localcount-20161104:1.1.1.2 netbsd-7-0-2-RELEASE:1.1.1.2 localcount-20160914:1.1.1.2 netbsd-7-nhusb:1.1.1.2.0.10 netbsd-7-nhusb-base:1.1.1.2 pgoyette-localcount-20160806:1.1.1.2 pgoyette-localcount-20160726:1.1.1.2 pgoyette-localcount:1.1.1.2.0.8 pgoyette-localcount-base:1.1.1.2 netbsd-7-0-1-RELEASE:1.1.1.2 netbsd-7-0:1.1.1.2.0.6 netbsd-7-0-RELEASE:1.1.1.2 netbsd-7-0-RC3:1.1.1.2 netbsd-7-0-RC2:1.1.1.2 netbsd-7-0-RC1:1.1.1.2 netbsd-6-0-6-RELEASE:1.1.1.1 netbsd-6-1-5-RELEASE:1.1.1.1 netbsd-7:1.1.1.2.0.4 netbsd-7-base:1.1.1.2 yamt-pagecache-base9:1.1.1.2 yamt-pagecache-tag8:1.1.1.1 netbsd-6-1-4-RELEASE:1.1.1.1 netbsd-6-0-5-RELEASE:1.1.1.1 tls-earlyentropy:1.1.1.2.0.2 tls-earlyentropy-base:1.1.1.2 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.1.1.2 riastradh-drm2-base3:1.1.1.2 netbsd-6-1-3-RELEASE:1.1.1.1 netbsd-6-0-4-RELEASE:1.1.1.1 gmp-5-1-3:1.1.1.2 netbsd-6-1-2-RELEASE:1.1.1.1 netbsd-6-0-3-RELEASE:1.1.1.1 netbsd-6-1-1-RELEASE:1.1.1.1 riastradh-drm2-base2:1.1.1.1 riastradh-drm2-base1:1.1.1.1 riastradh-drm2:1.1.1.1.0.12 riastradh-drm2-base:1.1.1.1 netbsd-6-1:1.1.1.1.0.16 netbsd-6-0-2-RELEASE:1.1.1.1 netbsd-6-1-RELEASE:1.1.1.1 netbsd-6-1-RC4:1.1.1.1 netbsd-6-1-RC3:1.1.1.1 agc-symver:1.1.1.1.0.14 agc-symver-base:1.1.1.1 netbsd-6-1-RC2:1.1.1.1 netbsd-6-1-RC1:1.1.1.1 yamt-pagecache-base8:1.1.1.1 netbsd-6-0-1-RELEASE:1.1.1.1 yamt-pagecache-base7:1.1.1.1 matt-nb6-plus-nbase:1.1.1.1 yamt-pagecache-base6:1.1.1.1 netbsd-6-0:1.1.1.1.0.10 netbsd-6-0-RELEASE:1.1.1.1 netbsd-6-0-RC2:1.1.1.1 tls-maxphys:1.1.1.1.0.8 tls-maxphys-base:1.1.1.2 matt-nb6-plus:1.1.1.1.0.6 matt-nb6-plus-base:1.1.1.1 netbsd-6-0-RC1:1.1.1.1 yamt-pagecache-base5:1.1.1.1 yamt-pagecache-base4:1.1.1.1 netbsd-6:1.1.1.1.0.4 netbsd-6-base:1.1.1.1 yamt-pagecache-base3:1.1.1.1 yamt-pagecache-base2:1.1.1.1 yamt-pagecache:1.1.1.1.0.2 yamt-pagecache-base:1.1.1.1 gmp-5-0-2:1.1.1.1 gmp:1.1.1; locks; strict; comment @# @; 1.1 date 2011.06.20.05.54.45; author mrg; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2011.06.20.05.54.45; author mrg; state Exp; branches 1.1.1.1.2.1 1.1.1.1.8.1; next 1.1.1.2; 1.1.1.2 date 2013.11.29.07.49.49; author mrg; state Exp; branches; next 1.1.1.3; commitid L2Av4PuGmdoL39fx; 1.1.1.3 date 2017.08.22.09.40.49; author mrg; state Exp; branches; next ; commitid W5kmAIk8hwVpSb4A; 1.1.1.1.2.1 date 2014.05.22.14.09.04; author yamt; state Exp; branches; next ; commitid nx2BSsHy0NPeAxBx; 1.1.1.1.8.1 date 2014.08.19.23.59.53; author tls; state Exp; branches; next ; commitid jTnpym9Qu0o4R1Nx; desc @@ 1.1 log @Initial revision @ text @Copyright 1997, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. This file is part of the GNU MP Library. The GNU MP Library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. The GNU MP Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. This directory contains mpn functions for 64-bit V9 SPARC RELEVANT OPTIMIZATION ISSUES Notation: IANY = shift/add/sub/logical/sethi IADDLOG = add/sub/logical/sethi MEM = ld*/st* FA = fadd*/fsub*/f*to*/fmov* FM = fmul* UltraSPARC can issue four instructions per cycle, with these restrictions: * Two IANY instructions, but only one of these may be a shift. If there is a shift and an IANY instruction, the shift must precede the IANY instruction. * One FA. * One FM. * One branch. * One MEM. * IANY/IADDLOG/MEM must be insn 1, 2, or 3 in an issue bundle. Taken branches should not be in slot 4, since that makes the delay insn come from separate bundle. * If two IANY/IADDLOG instructions are to be executed in the same cycle and one of these is setting the condition codes, that instruction must be the second one. To summarize, ignoring branches, these are the bundles that can reach the peak execution speed: insn1 iany iany mem iany iany mem iany iany mem insn2 iaddlog mem iany mem iaddlog iany mem iaddlog iany insn3 mem iaddlog iaddlog fa fa fa fm fm fm insn4 fa/fm fa/fm fa/fm fm fm fm fa fa fa The 64-bit integer multiply instruction mulx takes from 5 cycles to 35 cycles, depending on the position of the most significant bit of the first source operand. When used for 32x32->64 multiplication, it needs 20 cycles. Furthermore, it stalls the processor while executing. We stay away from that instruction, and instead use floating-point operations. Floating-point add and multiply units are fully pipelined. The latency for UltraSPARC-1/2 is 3 cycles and for UltraSPARC-3 it is 4 cycles. Integer conditional move instructions cannot dual-issue with other integer instructions. No conditional move can issue 1-5 cycles after a load. (This might have been fixed for UltraSPARC-3.) The UltraSPARC-3 pipeline is very simular to he one of UltraSPARC-1/2 , but is somewhat slower. Branches execute slower, and there may be other new stalls. But integer multiply doesn't stall the entire CPU and also has a much lower latency. But it's still not pipelined, and thus useless for our needs. STATUS * mpn_lshift, mpn_rshift: The current code runs at 2.0 cycles/limb on UltraSPARC-1/2 and 2.65 on UltraSPARC-3. For UltraSPARC-1/2, the IEU0 functional unit is saturated with shifts. * mpn_add_n, mpn_sub_n: The current code runs at 4 cycles/limb on UltraSPARC-1/2 and 4.5 cycles/limb on UltraSPARC-3. The 4 instruction recurrency is the speed limiter. * mpn_addmul_1: The current code runs at 14 cycles/limb asymptotically on UltraSPARC-1/2 and 17.5 cycles/limb on UltraSPARC-3. On UltraSPARC-1/2, the code sustains 4 instructions/cycle. It might be possible to invent a better way of summing the intermediate 49-bit operands, but it is unlikely that it will save enough instructions to save an entire cycle. The load-use of the u operand is not enough scheduled for good L2 cache performance. The UltraSPARC-1/2 L1 cache is direct mapped, and since we use temporary stack slots that will conflict with the u and r operands, we miss to L2 very often. The load-use of the std/ldx pairs via the stack are perhaps over-scheduled. It would be possible to save two instructions: (1) The mov could be avoided if the std/ldx were less scheduled. (2) The ldx of the r operand could be split into two ld instructions, saving the shifts/masks. It should be possible to reach 14 cycles/limb for UltraSPARC-3 if the fp operations where rescheduled for this processor's 4-cycle latency. * mpn_mul_1: The current code is a straightforward edit of the mpn_addmul_1 code. It would be possible to shave one or two cycles from it, with some labour. * mpn_submul_1: Simpleminded code just calling mpn_mul_1 + mpn_sub_n. This means that it runs at 18 cycles/limb on UltraSPARC-1/2 and 23 cycles/limb on UltraSPARC-3. It would be possible to either match the mpn_addmul_1 performance, or in the worst case use one more instruction group. * US1/US2 cache conflict resolving. The direct mapped L1 date cache of US1/US2 is a problem for mul_1, addmul_1 (and a prospective submul_1). We should allocate a larger cache area, and put the stack temp area in a place that doesn't cause cache conflicts. @ 1.1.1.1 log @initial import of GMP 5.0.2. GNU MP is a library for arbitrary precision arithmetic, operating on signed integers, rational numbers, and floating point numbers. It has a rich set of functions, and the functions have a regular interface. GMP is necessary for GCC >= 4.2. @ text @@ 1.1.1.1.8.1 log @Rebase to HEAD as of a few days ago. @ text @d68 1 a68 1 The UltraSPARC-3 pipeline is very simular to the one of UltraSPARC-1/2 , but is @ 1.1.1.1.2.1 log @sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments") @ text @d68 1 a68 1 The UltraSPARC-3 pipeline is very simular to the one of UltraSPARC-1/2 , but is @ 1.1.1.2 log @initial import GMP 5.1.3 sources. changes include: fixes for: - mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec - mpz_powm_ui - AMD family 11h - mpz_powm_sec and mpn_powm_sec - ASSERT() fixes - gcd, gcdext, and invert function fixes - some PPC division operations @ text @d68 1 a68 1 The UltraSPARC-3 pipeline is very simular to the one of UltraSPARC-1/2 , but is @ 1.1.1.3 log @initial import of GMP 6.1.2. main changes from 5.1.3 below. notes: - support for thumb-less ARM chips was in our port of 5.1.3, but a similar method has been provided upstream now - someone should look at the AVX failure reports, and fix them Changes between GMP version 6.1.0 and 6.1.1 FEATURES * Work around faulty cpuid on some recent Intel chips (this allows GMP to run on Skylake Pentiums). * Support thumb-less ARM chips. Changes between GMP version 6.0.* and 6.1.0 BUGS FIXED * The public function mpn_com is now correctly declared in gmp.h. * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for some obsolete CPUs. * Various problems related to precision for mpf have been fixed. * Fixed ABI incompatible stack alignment in calls from assembly code. * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI. SPEEDUPS * Speedup for Intel Broadwell and Skylake through assembly code making use of new ADX instructions. * Square root is now faster when the remainder is not needed. Also the speed to compute the k-th root improved, for small sizes. FEATURES * New C++ functions gcd and lcm for mpz_class. * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap. * New public mpq_cmp_z function, to efficiently compare rationals with integers. * Support for more 32-bit arm processors. * Support for AVX-less modern x86 CPUs. (Such support might be missing either because the CPU vendor chose to disable AVX, or because the running kernel lacks AVX context switch support.) * Support for NetBSD under Xen; we switch off AVX unconditionally under NetBSD since a bug in NetBSD makes AVX fail under Xen. MISC * Tuned values for FFT multiplications are provided for larger number on many platforms. Changes between GMP version 5.1.* and 6.0.0 BUGS FIXED * The function mpz_invert now considers any number invertible in Z/1Z. * The mpn multiply code now handles operands of more than 2^31 limbs correctly. (Note however that the mpz code is limited to 2^32 bits on 32-bit hosts and 2^37 bits on 64-bit hosts.) SPEEDUPS * Plain division of large operands is faster and more monotonous in operand size. * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved assembly. * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten and vastly expanded assembly support. Speedup also for the older Core 2 and Nehalem. * Faster mixed arithmetic between mpq_class and double. FEATURES * Support for new Intel and AMD CPUs. * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel silent multiplication and squaring. * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing side-channel silent division. * New public functions mpn_cnd_add_n and mpn_cnd_sub_n. Side-channel silent conditional addition and subtraction. * New public function mpn_sec_powm, implementing side-channel silent modexp. * New public function mpn_sec_invert, implementing side-channel silent modular inversion. * Better support for applications which use the mpz_t type, but nevertheless need to call some of the lower-level mpn functions. See the documentation for mpz_limbs_read and related functions. @ text @d1 1 a1 1 Copyright 1997, 1999-2002 Free Software Foundation, Inc. d6 3 a8 13 it under the terms of either: * the GNU Lesser General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. or * the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. or both in parallel, as here. d12 2 a13 2 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. d15 2 a16 3 You should have received copies of the GNU General Public License and the GNU Lesser General Public License along with the GNU MP Library. If not, see https://www.gnu.org/licenses/. @