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desc
@@


1.1
log
@Initial revision
@
text
@dnl  IA-64 mpn_rsh1add_n/mpn_rsh1sub_n -- rp[] = (up[] +- vp[]) >> 1.

dnl  Copyright 2003, 2004, 2005 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C         cycles/limb
C Itanium:    2.5
C Itanium 2:  1.5

C TODO
C  * Rewrite function entry code using aorslsh1_n.asm style.
C  * Micro-optimize feed-in and wind-down code.

C INPUT PARAMETERS
define(`rp',`r32')
define(`up',`r33')
define(`vp',`r34')
define(`n',`r35')

ifdef(`OPERATION_rsh1add_n',`
  define(ADDSUB,       add)
  define(PRED,	       ltu)
  define(INCR,	       1)
  define(LIM,	       -1)
  define(func, mpn_rsh1add_n)
')
ifdef(`OPERATION_rsh1sub_n',`
  define(ADDSUB,       sub)
  define(PRED,	       gtu)
  define(INCR,	       -1)
  define(LIM,	       0)
  define(func, mpn_rsh1sub_n)
')

C Some useful aliases for registers we use
define(`u0',`r14') define(`u1',`r15') define(`u2',`r16') define(`u3',`r17')
define(`v0',`r18') define(`v1',`r19') define(`v2',`r20') define(`v3',`r21')
define(`w0',`r22') define(`w1',`r23') define(`w2',`r24') define(`w3',`r25')
define(`x0',`r26') define(`x1',`r9') define(`x2',`r30') define(`x3',`r31')

MULFUNC_PROLOGUE(mpn_rsh1add_n mpn_rsh1sub_n)

ASM_START()
PROLOGUE(func)
	.prologue
	.save	ar.lc, r2
	.body
ifdef(`HAVE_ABI_32',`
	addp4		rp = 0, rp		C			M I
	addp4		up = 0, up		C			M I
	addp4		vp = 0, vp		C			M I
	zxt4		n = n			C			I
	;;
')
 {.mmi;	ld8		r11 = [vp], 8		C			M01
	ld8		r10 = [up], 8		C			M01
	mov.i		r2 = ar.lc		C			I0
}{.mmi;	and		r14 = 3, n		C			M I
	cmp.lt		p15, p0 = 4, n		C			M I
	add		n = -4, n		C			M I
	;;
}{.mmi;	cmp.eq		p6, p0 = 1, r14		C			M I
	cmp.eq		p7, p0 = 2, r14		C			M I
	cmp.eq		p8, p0 = 3, r14		C			M I
}{.bbb
  (p6)	br.dptk		.Lb01			C			B
  (p7)	br.dptk		.Lb10			C			B
  (p8)	br.dptk		.Lb11			C			B
}

.Lb00:	ld8		v0 = [vp], 8		C			M01
	ld8		u0 = [up], 8		C			M01
	shr.u		n = n, 2		C			I0
	;;
	ld8		v1 = [vp], 8		C			M01
	ld8		u1 = [up], 8		C			M01
	ADDSUB		w3 = r10, r11		C			M I
	;;
	ld8		v2 = [vp], 8		C			M01
	ld8		u2 = [up], 8		C			M01
  (p15)	br.dpnt		.grt4			C			B
	;;

	cmp.PRED	p7, p0 = w3, r10	C			M I
	and		r8 = 1, w3		C			M I
	ADDSUB		w0 = u0, v0		C			M I
	;;
	cmp.PRED	p8, p0 = w0, u0		C			M I
	ADDSUB		w1 = u1, v1		C			M I
	;;
	cmp.PRED	p9, p0 = w1, u1		C			M I
   (p7)	cmp.eq.or	p8, p0 = LIM, w0	C			M I
   (p7)	add		w0 = INCR, w0		C			M I
	;;
	shrp		x3 = w0, w3, 1		C			I0
	ADDSUB		w2 = u2, v2		C			M I
   (p8)	cmp.eq.or	p9, p0 = LIM, w1	C			M I
   (p8)	add		w1 = INCR, w1		C			M I
	br		.Lcj4			C			B

.grt4:	ld8		v3 = [vp], 8		C			M01
	cmp.PRED	p7, p0 = w3, r10	C			M I
	ld8		u3 = [up], 8		C			M01
	and		r8 = 1, w3		C			M I
	;;
	ADDSUB		w0 = u0, v0		C			M I
	ld8		v0 = [vp], 8		C			M01
	add		n = -1, n
	;;
	cmp.PRED	p8, p0 = w0, u0		C			M I
	ld8		u0 = [up], 8		C			M01
	ADDSUB		w1 = u1, v1		C			M I
	;;
	ld8		v1 = [vp], 8		C			M01
	mov.i		ar.lc = n		C			I0
	cmp.PRED	p9, p0 = w1, u1		C			M I
	ld8		u1 = [up], 8		C			M01
   (p7)	cmp.eq.or	p8, p0 = LIM, w0	C			M I
   (p7)	add		w0 = INCR, w0		C			M I
	;;
	ADDSUB		w2 = u2, v2		C			M I
	ld8		v2 = [vp], 8		C			M01
	shrp		x3 = w0, w3, 1		C			I0
   (p8)	cmp.eq.or	p9, p0 = LIM, w1	C			M I
   (p8)	add		w1 = INCR, w1		C			M I
	br		.LL00			C			B


.Lb01:	ADDSUB		w2 = r10, r11		C			M I
	shr.u		n = n, 2		C			I0
  (p15)	br.dpnt		.grt1			C			B
	;;

	cmp.PRED	p6, p7 = w2, r10	C			M I
	shr.u		x2 = w2, 1		C			I0
	and		r8 = 1, w2		C			M I
	;;
   (p6)	dep		x2 = -1, x2, 63, 1	C			I0
	br		.Lcj1			C			B

.grt1:	ld8		v3 = [vp], 8		C			M01
	ld8		u3 = [up], 8		C			M01
	;;
	ld8		v0 = [vp], 8		C			M01
	ld8		u0 = [up], 8		C			M01
	mov.i		ar.lc = n		C FIXME swap with next	I0
	;;
	ld8		v1 = [vp], 8		C			M01
	ld8		u1 = [up], 8		C			M01
	;;
	ld8		v2 = [vp], 8		C			M01
	ld8		u2 = [up], 8		C			M01
	cmp.PRED	p6, p0 = w2, r10	C			M I
	and		r8 = 1, w2		C			M I
	ADDSUB		w3 = u3, v3		C			M I
	br.cloop.dptk	.grt5			C			B
	;;

	cmp.PRED	p7, p0 = w3, u3		C			M I
	;;
	ADDSUB		w0 = u0, v0		C			M I
   (p6)	cmp.eq.or	p7, p0 = LIM, w3	C			M I
   (p6)	add		w3 = INCR, w3		C			M I
	;;
	cmp.PRED	p8, p0 = w0, u0		C			M I
	shrp		x2 = w3, w2, 1		C			I0
	ADDSUB		w1 = u1, v1		C			M I
	;;
	cmp.PRED	p9, p0 = w1, u1		C			M I
   (p7)	cmp.eq.or	p8, p0 = LIM, w0	C			M I
   (p7)	add		w0 = INCR, w0		C			M I
	br		.Lcj5			C			B

.grt5:	ld8		v3 = [vp], 8		C			M01
	cmp.PRED	p7, p0 = w3, u3		C			M I
	ld8		u3 = [up], 8		C			M01
	;;
	ADDSUB		w0 = u0, v0		C			M I
	ld8		v0 = [vp], 8		C			M01
   (p6)	cmp.eq.or	p7, p0 = LIM, w3	C			M I
   (p6)	add		w3 = INCR, w3		C			M I
	;;
	cmp.PRED	p8, p0 = w0, u0		C			M I
	shrp		x2 = w3, w2, 1		C			I0
	ld8		u0 = [up], 8		C			M01
	ADDSUB		w1 = u1, v1		C			M I
	;;
	ld8		v1 = [vp], 8		C			M01
	cmp.PRED	p9, p0 = w1, u1		C			M I
	ld8		u1 = [up], 8		C			M01
   (p7)	cmp.eq.or	p8, p0 = LIM, w0	C			M I
   (p7)	add		w0 = INCR, w0		C			M I
	br		.LL01			C			B


.Lb10:	ld8		v2 = [vp], 8		C			M01
	ld8		u2 = [up], 8		C			M01
	shr.u		n = n, 2		C			I0
	ADDSUB		w1 = r10, r11		C			M I
  (p15)	br.dpnt		.grt2			C			B
	;;

	cmp.PRED	p9, p0 = w1, r10	C			M I
	and		r8 = 1, w1		C			M I
	ADDSUB		w2 = u2, v2		C			M I
	;;
	cmp.PRED	p6, p0 = w2, u2		C			M I
	;;
   (p9)	cmp.eq.or	p6, p0 = LIM, w2	C			M I
   (p9)	add		w2 = INCR, w2		C			M I
	;;
	shrp		x1 = w2, w1, 1		C			I0
	shr.u		x2 = w2, 1		C			I0
	br		.Lcj2			C			B

.grt2:	ld8		v3 = [vp], 8		C			M01
	ld8		u3 = [up], 8		C			M01
	;;
	ld8		v0 = [vp], 8		C			M01
	ld8		u0 = [up], 8		C			M01
	mov.i		ar.lc = n		C			I0
	;;
	ld8		v1 = [vp], 8		C			M01
	cmp.PRED	p9, p0 = w1, r10	C			M I
	ld8		u1 = [up], 8		C			M01
	and		r8 = 1, w1		C			M I
	;;
	ADDSUB		w2 = u2, v2		C			M I
	ld8		v2 = [vp], 8		C			M01
	;;
	cmp.PRED	p6, p0 = w2, u2		C			M I
	ld8		u2 = [up], 8		C			M01
	ADDSUB		w3 = u3, v3		C			M I
	br.cloop.dptk	.grt6			C			B
	;;

	cmp.PRED	p7, p0 = w3, u3		C			M I
   (p9)	cmp.eq.or	p6, p0 = LIM, w2	C			M I
   (p9)	add		w2 = INCR, w2		C			M I
	;;
	shrp		x1 = w2, w1, 1		C			I0
	ADDSUB		w0 = u0, v0		C			M I
   (p6)	cmp.eq.or	p7, p0 = LIM, w3	C			M I
   (p6)	add		w3 = INCR, w3		C			M I
	br		.Lcj6			C			B

.grt6:	ld8		v3 = [vp], 8		C			M01
	cmp.PRED	p7, p0 = w3, u3		C			M I
	ld8		u3 = [up], 8		C			M01
   (p9)	cmp.eq.or	p6, p0 = LIM, w2	C			M I
   (p9)	add		w2 = INCR, w2		C			M I
	;;
	shrp		x1 = w2, w1, 1		C			I0
	ADDSUB		w0 = u0, v0		C			M I
	ld8		v0 = [vp], 8		C			M01
   (p6)	cmp.eq.or	p7, p0 = LIM, w3	C			M I
   (p6)	add		w3 = INCR, w3		C			M I
	br		.LL10			C			B


.Lb11:	ld8		v1 = [vp], 8		C			M01
	ld8		u1 = [up], 8		C			M01
	shr.u		n = n, 2		C			I0
	;;
	ld8		v2 = [vp], 8		C			M01
	ld8		u2 = [up], 8		C			M01
	ADDSUB		w0 = r10, r11		C			M I
  (p15)	br.dpnt		.grt3			C			B
	;;

	cmp.PRED	p8, p0 = w0, r10	C			M I
	ADDSUB		w1 = u1, v1		C			M I
	and		r8 = 1, w0		C			M I
	;;
	cmp.PRED	p9, p0 = w1, u1		C			M I
	;;
	ADDSUB		w2 = u2, v2		C			M I
   (p8)	cmp.eq.or	p9, p0 = LIM, w1	C			M I
   (p8)	add		w1 = INCR, w1		C			M I
	;;
	cmp.PRED	p6, p0 = w2, u2		C			M I
	shrp		x0 = w1, w0, 1		C			I0
	;;
   (p9)	cmp.eq.or	p6, p0 = LIM, w2	C			M I
   (p9)	add		w2 = INCR, w2		C			M I
	br		.Lcj3			C			B

.grt3:	ld8		v3 = [vp], 8		C			M01
	ld8		u3 = [up], 8		C			M01
	;;
	ld8		v0 = [vp], 8		C			M01
	mov.i		ar.lc = n		C			I0
	cmp.PRED	p8, p0 = w0, r10	C			M I
	ld8		u0 = [up], 8		C			M01
	ADDSUB		w1 = u1, v1		C			M I
	and		r8 = 1, w0		C			M I
	;;
	ld8		v1 = [vp], 8		C			M01
	cmp.PRED	p9, p0 = w1, u1		C			M I
	ld8		u1 = [up], 8		C			M01
	;;
	ADDSUB		w2 = u2, v2		C			M I
	ld8		v2 = [vp], 8		C			M01
   (p8)	cmp.eq.or	p9, p0 = LIM, w1	C			M I
   (p8)	add		w1 = INCR, w1		C			M I
	;;
	cmp.PRED	p6, p0 = w2, u2		C			M I
	shrp		x0 = w1, w0, 1		C			I0
	ld8		u2 = [up], 8		C			M01
	ADDSUB		w3 = u3, v3		C			M I
	br.cloop.dptk	.grt7			C			B
	;;

	cmp.PRED	p7, p0 = w3, u3		C			M I
   (p9)	cmp.eq.or	p6, p0 = LIM, w2	C			M I
   (p9)	add		w2 = INCR, w2		C			M I
	br		.Lcj7			C			B

.grt7:	ld8		v3 = [vp], 8		C			M01
	cmp.PRED	p7, p0 = w3, u3		C			M I
	ld8		u3 = [up], 8		C			M01
   (p9)	cmp.eq.or	p6, p0 = LIM, w2	C			M I
   (p9)	add		w2 = INCR, w2		C			M I
	br		.LL11			C			B


C *** MAIN LOOP START ***
	ALIGN(32)
.Loop:	st8		[rp] = x3, 8		C			M23
	ld8		v3 = [vp], 8		C			M01
	cmp.PRED	p7, p0 = w3, u3		C			M I
	ld8		u3 = [up], 8		C			M01
   (p9)	cmp.eq.or	p6, p0 = LIM, w2	C			M I
   (p9)	add		w2 = INCR, w2		C			M I
	;;
.LL11:	st8		[rp] = x0, 8		C			M23
	shrp		x1 = w2, w1, 1		C			I0
	ADDSUB		w0 = u0, v0		C			M I
	ld8		v0 = [vp], 8		C			M01
   (p6)	cmp.eq.or	p7, p0 = LIM, w3	C			M I
   (p6)	add		w3 = INCR, w3		C			M I
	;;
.LL10:	cmp.PRED	p8, p0 = w0, u0		C			M I
	shrp		x2 = w3, w2, 1		C			I0
	nop.b		0
	ld8		u0 = [up], 8		C			M01
	ADDSUB		w1 = u1, v1		C			M I
	nop.b		0
	;;
	st8		[rp] = x1, 8		C			M23
	ld8		v1 = [vp], 8		C			M01
	cmp.PRED	p9, p0 = w1, u1		C			M I
	ld8		u1 = [up], 8		C			M01
   (p7)	cmp.eq.or	p8, p0 = LIM, w0	C			M I
   (p7)	add		w0 = INCR, w0		C			M I
	;;
.LL01:	st8		[rp] = x2, 8		C			M23
	shrp		x3 = w0, w3, 1		C			I0
	ADDSUB		w2 = u2, v2		C			M I
	ld8		v2 = [vp], 8		C			M01
   (p8)	cmp.eq.or	p9, p0 = LIM, w1	C			M I
   (p8)	add		w1 = INCR, w1		C			M I
	;;
.LL00:	cmp.PRED	p6, p0 = w2, u2		C			M I
	shrp		x0 = w1, w0, 1		C			I0
	nop.b		0
	ld8		u2 = [up], 8		C			M01
	ADDSUB		w3 = u3, v3		C			M I
	br.cloop.dptk	.Loop			C			B
	;;
C *** MAIN LOOP END ***

.Lskip:	st8		[rp] = x3, 8		C			M23
	cmp.PRED	p7, p0 = w3, u3		C			M I
   (p9)	cmp.eq.or	p6, p0 = LIM, w2	C			M I
   (p9)	add		w2 = INCR, w2		C			M I
	;;
.Lcj7:	st8		[rp] = x0, 8		C			M23
	shrp		x1 = w2, w1, 1		C			I0
	ADDSUB		w0 = u0, v0		C			M I
   (p6)	cmp.eq.or	p7, p0 = LIM, w3	C			M I
   (p6)	add		w3 = INCR, w3		C			M I
	;;
.Lcj6:	cmp.PRED	p8, p0 = w0, u0		C			M I
	shrp		x2 = w3, w2, 1		C			I0
	ADDSUB		w1 = u1, v1		C			M I
	;;
	st8		[rp] = x1, 8		C			M23
	cmp.PRED	p9, p0 = w1, u1		C			M I
   (p7)	cmp.eq.or	p8, p0 = LIM, w0	C			M I
   (p7)	add		w0 = INCR, w0		C			M I
	;;
.Lcj5:	st8		[rp] = x2, 8		C			M23
	shrp		x3 = w0, w3, 1		C			I0
	ADDSUB		w2 = u2, v2		C			M I
   (p8)	cmp.eq.or	p9, p0 = LIM, w1	C			M I
   (p8)	add		w1 = INCR, w1		C			M I
	;;
.Lcj4:	cmp.PRED	p6, p0 = w2, u2		C			M I
	shrp		x0 = w1, w0, 1		C			I0
	;;
	st8		[rp] = x3, 8		C			M23
   (p9)	cmp.eq.or	p6, p0 = LIM, w2	C			M I
   (p9)	add		w2 = INCR, w2		C			M I
	;;
.Lcj3:	st8		[rp] = x0, 8		C			M23
	shrp		x1 = w2, w1, 1		C			I0
	shr.u		x2 = w2, 1		C			I0
	;;
.Lcj2:	st8		[rp] = x1, 8		C			M23
   (p6)	dep		x2 = -1, x2, 63, 1	C			I0
	;;
.Lcj1:	st8		[rp] = x2		C			M23
	mov.i		ar.lc = r2		C			I0
	br.ret.sptk.many b0			C			B
EPILOGUE()
@


1.1.1.1
log
@initial import of GMP 5.0.2.

GNU MP is a library for arbitrary precision arithmetic, operating on signed
integers, rational numbers, and floating point numbers.  It has a rich set
of functions, and the functions have a regular interface.

GMP is necessary for GCC >= 4.2.
@
text
@@


1.1.1.1.8.1
log
@Rebase to HEAD as of a few days ago.
@
text
@a2 2
dnl  Contributed to the GNU project by Torbjorn Granlund.

@


1.1.1.1.2.1
log
@sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")
@
text
@a2 2
dnl  Contributed to the GNU project by Torbjorn Granlund.

@


1.1.1.2
log
@initial import GMP 5.1.3 sources.  changes include:

fixes for:
- mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec
- mpz_powm_ui
- AMD family 11h
- mpz_powm_sec and mpn_powm_sec
- ASSERT() fixes
- gcd, gcdext, and invert function fixes
- some PPC division operations
@
text
@a2 2
dnl  Contributed to the GNU project by Torbjorn Granlund.

@


1.1.1.3
log
@initial import of GMP 6.1.2.  main changes from 5.1.3 below.

notes:
 - support for thumb-less ARM chips was in our port of 5.1.3, but a
   similar method has been provided upstream now
 - someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

  FEATURES
  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
    on Skylake Pentiums).
  * Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

  BUGS FIXED
  * The public function mpn_com is now correctly declared in gmp.h.
  * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
    some obsolete CPUs.
  * Various problems related to precision for mpf have been fixed.
  * Fixed ABI incompatible stack alignment in calls from assembly code.
  * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
  SPEEDUPS
  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    new ADX instructions.
  * Square root is now faster when the remainder is not needed. Also the speed
    to compute the k-th root improved, for small sizes.
  FEATURES
  * New C++ functions gcd and lcm for mpz_class.
  * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
  * New public mpq_cmp_z function, to efficiently compare rationals with
    integers.
  * Support for more 32-bit arm processors.
  * Support for AVX-less modern x86 CPUs. (Such support might be missing either
    because the CPU vendor chose to disable AVX, or because the running kernel
    lacks AVX context switch support.)
  * Support for NetBSD under Xen; we switch off AVX unconditionally under
    NetBSD since a bug in NetBSD makes AVX fail under Xen.
  MISC
  * Tuned values for FFT multiplications are provided for larger number on
    many platforms.

Changes between GMP version 5.1.* and 6.0.0
  BUGS FIXED
  * The function mpz_invert now considers any number invertible in Z/1Z.
  * The mpn multiply code now handles operands of more than 2^31 limbs
    correctly.  (Note however that the mpz code is limited to 2^32 bits on
    32-bit hosts and 2^37 bits on 64-bit hosts.)
  SPEEDUPS
  * Plain division of large operands is faster and more monotonous in operand
    size.
  * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
    assembly.
  * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
    and vastly expanded assembly support.  Speedup also for the older Core 2
    and Nehalem.
  * Faster mixed arithmetic between mpq_class and double.
  FEATURES
  * Support for new Intel and AMD CPUs.
  * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
    silent multiplication and squaring.
  * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
    side-channel silent division.
  * New public functions mpn_cnd_add_n and mpn_cnd_sub_n.  Side-channel silent
    conditional addition and subtraction.
  * New public function mpn_sec_powm, implementing side-channel silent modexp.
  * New public function mpn_sec_invert, implementing side-channel silent
    modular inversion.
  * Better support for applications which use the mpz_t type, but nevertheless
    need to call some of the lower-level mpn functions.  See the documentation
    for mpz_limbs_read and related functions.
@
text
@d5 1
a5 1
dnl  Copyright 2003-2005 Free Software Foundation, Inc.
d8 1
a8 1
dnl
d10 4
a13 14
dnl  it under the terms of either:
dnl
dnl    * the GNU Lesser General Public License as published by the Free
dnl      Software Foundation; either version 3 of the License, or (at your
dnl      option) any later version.
dnl
dnl  or
dnl
dnl    * the GNU General Public License as published by the Free Software
dnl      Foundation; either version 2 of the License, or (at your option) any
dnl      later version.
dnl
dnl  or both in parallel, as here.
dnl
d16 5
a20 6
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
dnl  for more details.
dnl
dnl  You should have received copies of the GNU General Public License and the
dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
dnl  see https://www.gnu.org/licenses/.
a69 2
	nop.m		0
	nop.m		0
@