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	netbsd-11-0-RC5:1.1.1.3
	netbsd-11-0-RC4:1.1.1.3
	netbsd-11-0-RC3:1.1.1.3
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	pgoyette-compat-20190127:1.1.1.1
	pgoyette-compat-20190118:1.1.1.1
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	pgoyette-compat-0502:1.1.1.1
	pgoyette-compat-0422:1.1.1.1
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	gmp-6-1-2:1.1.1.1
	gmp:1.1.1;
locks; strict;
comment	@;; @;


1.1
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1.1.1.3
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desc
@@


1.1
log
@Initial revision
@
text
@dnl  ARM64 mpn_lshift.

dnl  Copyright 2013, 2014 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C	     cycles/limb
C Cortex-A53	 ?
C Cortex-A57	 ?

changecom(@@&*$)

define(`rp_arg', `x0')
define(`up',     `x1')
define(`n',      `x2')
define(`cnt',    `x3')

define(`rp',     `x16')

define(`tnc',`x8')

ASM_START()
PROLOGUE(mpn_lshift)
	add	rp, rp_arg, n, lsl #3
	add	up, up, n, lsl #3
	sub	tnc, xzr, cnt
	tbz	n, #0, L(bx0)

L(bx1):	ldr	x4, [up,#-8]
	tbnz	n, #1, L(b11)

L(b01):	lsr	x0, x4, tnc
	lsl	x18, x4, cnt
	sub	n, n, #1
	cbnz	n, L(gt1)
	str	x18, [rp,#-8]
	ret
L(gt1):	ldp	x4, x5, [up,#-24]
	sub	up, up, #8
	add	rp, rp, #16
	b	L(lo2)

L(b11):	lsr	x0, x4, tnc
	lsl	x9, x4, cnt
	ldp	x6, x7, [up,#-24]
	add	n, n, #1
	add	up, up, #8
	add	rp, rp, #32
	b	L(lo0)

L(bx0):	ldp	x4, x5, [up,#-16]
	tbz	n, #1, L(b00)

L(b10):	lsr	x0, x5, tnc
	lsl	x13, x5, cnt
	lsr	x10, x4, tnc
	lsl	x18, x4, cnt
	sub	n, n, #2
	cbnz	n, L(gt2)
	orr	x10, x10, x13
	stp	x18, x10, [rp,#-16]
	ret
L(gt2):	ldp	x4, x5, [up,#-32]
	orr	x10, x10, x13
	str	x10, [rp,#-8]
	sub	up, up, #16
	add	rp, rp, #8
	b	L(lo2)

L(b00):	lsr	x0, x5, tnc
	lsl	x13, x5, cnt
	lsr	x10, x4, tnc
	lsl	x9, x4, cnt
	ldp	x6, x7, [up,#-32]
	orr	x10, x10, x13
	str	x10, [rp,#-8]
	add	rp, rp, #24
	b	L(lo0)

	ALIGN(16)
L(top):	ldp	x4, x5, [up,#-48]
	sub	rp, rp, #32		C integrate with stp?
	sub	up, up, #32		C integrate with ldp?
	orr	x11, x11, x9
	orr	x10, x10, x13
	stp	x10, x11, [rp,#-16]
L(lo2):	lsr	x11, x5, tnc
	lsl	x13, x5, cnt
	lsr	x10, x4, tnc
	lsl	x9, x4, cnt
	ldp	x6, x7, [up,#-32]
	orr	x11, x11, x18
	orr	x10, x10, x13
	stp	x10, x11, [rp,#-32]
L(lo0):	sub	n, n, #4
	lsr	x11, x7, tnc
	lsl	x13, x7, cnt
	lsr	x10, x6, tnc
	lsl	x18, x6, cnt
	cbnz	n, L(top)

L(end):	orr	x11, x11, x9
	orr	x10, x10, x13
	stp	x10, x11, [rp,#-48]
	str	x18, [rp,#-56]
	ret
EPILOGUE()
@


1.1.1.1
log
@initial import of GMP 6.1.2.  main changes from 5.1.3 below.

notes:
 - support for thumb-less ARM chips was in our port of 5.1.3, but a
   similar method has been provided upstream now
 - someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

  FEATURES
  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
    on Skylake Pentiums).
  * Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

  BUGS FIXED
  * The public function mpn_com is now correctly declared in gmp.h.
  * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
    some obsolete CPUs.
  * Various problems related to precision for mpf have been fixed.
  * Fixed ABI incompatible stack alignment in calls from assembly code.
  * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
  SPEEDUPS
  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    new ADX instructions.
  * Square root is now faster when the remainder is not needed. Also the speed
    to compute the k-th root improved, for small sizes.
  FEATURES
  * New C++ functions gcd and lcm for mpz_class.
  * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
  * New public mpq_cmp_z function, to efficiently compare rationals with
    integers.
  * Support for more 32-bit arm processors.
  * Support for AVX-less modern x86 CPUs. (Such support might be missing either
    because the CPU vendor chose to disable AVX, or because the running kernel
    lacks AVX context switch support.)
  * Support for NetBSD under Xen; we switch off AVX unconditionally under
    NetBSD since a bug in NetBSD makes AVX fail under Xen.
  MISC
  * Tuned values for FFT multiplications are provided for larger number on
    many platforms.

Changes between GMP version 5.1.* and 6.0.0
  BUGS FIXED
  * The function mpz_invert now considers any number invertible in Z/1Z.
  * The mpn multiply code now handles operands of more than 2^31 limbs
    correctly.  (Note however that the mpz code is limited to 2^32 bits on
    32-bit hosts and 2^37 bits on 64-bit hosts.)
  SPEEDUPS
  * Plain division of large operands is faster and more monotonous in operand
    size.
  * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
    assembly.
  * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
    and vastly expanded assembly support.  Speedup also for the older Core 2
    and Nehalem.
  * Faster mixed arithmetic between mpq_class and double.
  FEATURES
  * Support for new Intel and AMD CPUs.
  * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
    silent multiplication and squaring.
  * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
    side-channel silent division.
  * New public functions mpn_cnd_add_n and mpn_cnd_sub_n.  Side-channel silent
    conditional addition and subtraction.
  * New public function mpn_sec_powm, implementing side-channel silent modexp.
  * New public function mpn_sec_invert, implementing side-channel silent
    modular inversion.
  * Better support for applications which use the mpz_t type, but nevertheless
    need to call some of the lower-level mpn functions.  See the documentation
    for mpz_limbs_read and related functions.
@
text
@@


1.1.1.2
log
@initial import of GMP 6.2.0.  changes include:

- Bug fixes to gmp_snprintf, conversion to double, mpz_powm,
  and mpf_set_str.
- New functions for factorial, primorial, fibonacci, mpz_2fac_ui,
  and mpz_mfac_uiui.
- MIPS r6 cores are now supported.
- Various speeds ups.
@
text
@d3 1
a3 1
dnl  Copyright 2013, 2014, 2017 Free Software Foundation, Inc.
d22 3
a24 11
C	     cycles/limb   assumed optimal c/l
C Cortex-A53	3.5-4.0		 3.25
C Cortex-A57	 2.0		 2.0
C X-Gene	 2.67		 2.5

C TODO
C  * The feed-in code used 1 ldr for odd sized and 2 ldr for even sizes.  These
C    numbers should be 1 and 0, respectively.  The str in wind-down should also
C    go.
C  * Using extr and with 63 separate loops we might reach 1.25 c/l on A57.
C  * A53's speed depends on alignment, tune/speed -w1 gives 3.5, -w0 gives 4.0.
d26 1
a26 1
changecom(blah)
a36 3
define(`PSHIFT', lsl)
define(`NSHIFT', lsr)

a41 1
	lsr	x18, n, #2
d47 5
a51 4
L(b01):	NSHIFT	x0, x4, tnc
	PSHIFT	x2, x4, cnt
	cbnz	x18, L(gt1)
	str	x2, [rp,#-8]
d58 7
a64 4
L(b11):	NSHIFT	x0, x4, tnc
	PSHIFT	x2, x4, cnt
	ldp	x6, x7, [up,#-24]!
	b	L(lo3)
d69 6
a74 5
L(b10):	NSHIFT	x0, x5, tnc
	PSHIFT	x13, x5, cnt
	NSHIFT	x10, x4, tnc
	PSHIFT	x2, x4, cnt
	cbnz	x18, L(gt2)
d76 1
a76 1
	stp	x2, x10, [rp,#-16]
d85 5
a89 5
L(b00):	NSHIFT	x0, x5, tnc
	PSHIFT	x13, x5, cnt
	NSHIFT	x10, x4, tnc
	PSHIFT	x2, x4, cnt
	ldp	x6, x7, [up,#-32]!
d91 2
a92 1
	str	x10, [rp,#-8]!
d96 4
a99 1
L(top):	ldp	x4, x5, [up,#-16]
a100 1
	orr	x11, x12, x2
d102 19
a120 20
	PSHIFT	x2, x6, cnt
L(lo2):	NSHIFT	x10, x4, tnc
	PSHIFT	x13, x5, cnt
	NSHIFT	x12, x5, tnc
	ldp	x6, x7, [up,#-32]!
	orr	x10, x10, x13
	orr	x11, x12, x2
	stp	x10, x11, [rp,#-32]!
	PSHIFT	x2, x4, cnt
L(lo0):	sub	x18, x18, #1
L(lo3):	NSHIFT	x10, x6, tnc
	PSHIFT	x13, x7, cnt
	NSHIFT	x12, x7, tnc
	cbnz	x18, L(top)

L(end):	orr	x10, x10, x13
	orr	x11, x12, x2
	PSHIFT	x2, x6, cnt
	stp	x10, x11, [rp,#-16]
	str	x2, [rp,#-24]
@


1.1.1.3
log
@initial import of GMP 6.2.1.  from their NEWS:

Changes between GMP version 6.2.0 and 6.2.1

  BUGS FIXED
  * A possible overflow of type int is avoided for mpz_cmp on huge operands.
  * Overflows are more carefully detected and reported for mpz_pow_ui.
  * A bug in longlong.h for aarch64 sub_ddmmss, not affecting GMP, was healed.

  FEATURES
  * C90 compliance.
  * Initial support for Darwin on arm64, and improved portability.
  * Support for more processors.
@
text
@d6 1
a6 1
dnl
d8 4
a11 14
dnl  it under the terms of either:
dnl
dnl    * the GNU Lesser General Public License as published by the Free
dnl      Software Foundation; either version 3 of the License, or (at your
dnl      option) any later version.
dnl
dnl  or
dnl
dnl    * the GNU General Public License as published by the Free Software
dnl      Foundation; either version 2 of the License, or (at your option) any
dnl      later version.
dnl
dnl  or both in parallel, as here.
dnl
d14 5
a18 6
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
dnl  for more details.
dnl
dnl  You should have received copies of the GNU General Public License and the
dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
dnl  see https://www.gnu.org/licenses/.
@