head	1.1;
branch	1.1.1;
access;
symbols
	netbsd-11-0-RC5:1.1.1.2
	netbsd-11-0-RC4:1.1.1.2
	netbsd-11-0-RC3:1.1.1.2
	netbsd-11-0-RC2:1.1.1.2
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	yamt-pagecache-base7:1.1.1.1
	matt-nb6-plus-nbase:1.1.1.1
	yamt-pagecache-base6:1.1.1.1
	netbsd-6-0:1.1.1.1.0.10
	netbsd-6-0-RELEASE:1.1.1.1
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	tls-maxphys:1.1.1.1.0.8
	tls-maxphys-base:1.1.1.1
	matt-nb6-plus:1.1.1.1.0.6
	matt-nb6-plus-base:1.1.1.1
	netbsd-6-0-RC1:1.1.1.1
	yamt-pagecache-base5:1.1.1.1
	yamt-pagecache-base4:1.1.1.1
	netbsd-6:1.1.1.1.0.4
	netbsd-6-base:1.1.1.1
	yamt-pagecache-base3:1.1.1.1
	yamt-pagecache-base2:1.1.1.1
	yamt-pagecache:1.1.1.1.0.2
	yamt-pagecache-base:1.1.1.1
	gmp-5-0-2:1.1.1.1
	gmp:1.1.1;
locks; strict;
comment	@;; @;


1.1
date	2011.06.20.05.54.44;	author mrg;	state Exp;
branches
	1.1.1.1;
next	;

1.1.1.1
date	2011.06.20.05.54.44;	author mrg;	state Exp;
branches;
next	1.1.1.2;

1.1.1.2
date	2017.08.22.09.40.48;	author mrg;	state Exp;
branches;
next	;
commitid	W5kmAIk8hwVpSb4A;


desc
@@


1.1
log
@Initial revision
@
text
@dnl  Alpha mpn_addlsh1_n/mpn_sublsh1_n -- rp[] = up[] +- (vp[] << 1).

dnl  Copyright 2003 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C      cycles/limb
C EV4:    12.5
C EV5:     6.25
C EV6:     4.375 (i.e., worse than separate mpn_lshift and mpn_add_n at 3.875)

C TODO
C  * Write special version for ev6, as this is a slowdown for 100 < n < 2200
C    compared to separate mpn_lshift and mpn_add_n.
C  * Use addq instead of sll for left shift, and similarly cmplt instead of srl
C    for right shift.

dnl  INPUT PARAMETERS
define(`rp',`r16')
define(`up',`r17')
define(`vp',`r18')
define(`n', `r19')

define(`u0', `r8')
define(`u1', `r1')
define(`u2', `r2')
define(`u3', `r3')
define(`v0', `r4')
define(`v1', `r5')
define(`v2', `r6')
define(`v3', `r7')

define(`cy0', `r0')
define(`cy1', `r20')
define(`cy', `r22')
define(`rr', `r24')
define(`ps', `r25')
define(`sl', `r28')

ifdef(`OPERATION_addlsh1_n',`
  define(ADDSUB,       addq)
  define(CARRY,       `cmpult $1,$2,$3')
  define(func, mpn_addlsh1_n)
')
ifdef(`OPERATION_sublsh1_n',`
  define(ADDSUB,       subq)
  define(CARRY,       `cmpult $2,$1,$3')
  define(func, mpn_sublsh1_n)
')

MULFUNC_PROLOGUE(mpn_addlsh1_n mpn_sublsh1_n)

ASM_START()
PROLOGUE(func)
	lda	n, -4(n)
	bis	r31, r31, cy1
	and	n, 3, r1
	beq	r1, $Lb00
	cmpeq	r1, 1, r2
	bne	r2, $Lb01
	cmpeq	r1, 2, r2
	bne	r2, $Lb10
$Lb11:	C n = 3, 7, 11, ...
	ldq	v0, 0(vp)
	ldq	u0, 0(up)
	ldq	v1, 8(vp)
	ldq	u1, 8(up)
	ldq	v2, 16(vp)
	ldq	u2, 16(up)
	lda	vp, 24(vp)
	lda	up, 24(up)
	bge	n, $Loop
	br	r31, $Lcj3
$Lb10:	C n = 2, 6, 10, ...
	bis	r31, r31, cy0
	ldq	v1, 0(vp)
	ldq	u1, 0(up)
	ldq	v2, 8(vp)
	ldq	u2, 8(up)
	lda	rp, -8(rp)
	blt	n, $Lcj2
	ldq	v3, 16(vp)
	ldq	u3, 16(up)
	lda	vp, 48(vp)
	lda	up, 16(up)
	br	r31, $LL10
$Lb01:	C n = 1, 5, 9, ...
	ldq	v2, 0(vp)
	ldq	u2, 0(up)
	lda	rp, -16(rp)
	blt	n, $Lcj1
	ldq	v3, 8(vp)
	ldq	u3, 8(up)
	ldq	v0, 16(vp)
	ldq	u0, 16(up)
	lda	vp, 40(vp)
	lda	up, 8(up)
	lda	rp, 32(rp)
	br	r31, $LL01
$Lb00:	C n = 4, 8, 12, ...
	bis	r31, r31, cy0
	ldq	v3, 0(vp)
	ldq	u3, 0(up)
	ldq	v0, 8(vp)
	ldq	u0, 8(up)
	ldq	v1, 16(vp)
	ldq	u1, 16(up)
	lda	vp, 32(vp)
	lda	rp, 8(rp)
	br	r31, $LL00x
	ALIGN(16)
C 0
$Loop:	sll	v0, 1, sl	C left shift vlimb
	ldq	v3, 0(vp)
C 1
	ADDSUB	u0, sl, ps	C ulimb + (vlimb << 1)
	ldq	u3, 0(up)
C 2
	ADDSUB	ps, cy1, rr	C consume carry from previous operation
	srl	v0, 63, cy0	C carry out #1
C 3
	CARRY(	ps, u0, cy)	C carry out #2
	stq	rr, 0(rp)
C 4
	addq	cy, cy0, cy0	C combine carry out #1 and #2
	CARRY(	rr, ps, cy)	C carry out #3
C 5
	addq	cy, cy0, cy0	C final carry out
	lda	vp, 32(vp)	C bookkeeping
C 6
$LL10:	sll	v1, 1, sl
	ldq	v0, -24(vp)
C 7
	ADDSUB	u1, sl, ps
	ldq	u0, 8(up)
C 8
	ADDSUB	ps, cy0, rr
	srl	v1, 63, cy1
C 9
	CARRY(	ps, u1, cy)
	stq	rr, 8(rp)
C 10
	addq	cy, cy1, cy1
	CARRY(	rr, ps, cy)
C 11
	addq	cy, cy1, cy1
	lda	rp, 32(rp)	C bookkeeping
C 12
$LL01:	sll	v2, 1, sl
	ldq	v1, -16(vp)
C 13
	ADDSUB	u2, sl, ps
	ldq	u1, 16(up)
C 14
	ADDSUB	ps, cy1, rr
	srl	v2, 63, cy0
C 15
	CARRY(	ps, u2, cy)
	stq	rr, -16(rp)
C 16
	addq	cy, cy0, cy0
	CARRY(	rr, ps, cy)
C 17
	addq	cy, cy0, cy0
$LL00x:	lda	up, 32(up)	C bookkeeping
C 18
	sll	v3, 1, sl
	ldq	v2, -8(vp)
C 19
	ADDSUB	u3, sl, ps
	ldq	u2, -8(up)
C 20
	ADDSUB	ps, cy0, rr
	srl	v3, 63, cy1
C 21
	CARRY(	ps, u3, cy)
	stq	rr, -8(rp)
C 22
	addq	cy, cy1, cy1
	CARRY(	rr, ps, cy)
C 23
	addq	cy, cy1, cy1
	lda	n, -4(n)	C bookkeeping
C 24
	bge	n, $Loop

$Lcj3:	sll	v0, 1, sl
	ADDSUB	u0, sl, ps
	ADDSUB	ps, cy1, rr
	srl	v0, 63, cy0
	CARRY(	ps, u0, cy)
	stq	rr, 0(rp)
	addq	cy, cy0, cy0
	CARRY(	rr, ps, cy)
	addq	cy, cy0, cy0

$Lcj2:	sll	v1, 1, sl
	ADDSUB	u1, sl, ps
	ADDSUB	ps, cy0, rr
	srl	v1, 63, cy1
	CARRY(	ps, u1, cy)
	stq	rr, 8(rp)
	addq	cy, cy1, cy1
	CARRY(	rr, ps, cy)
	addq	cy, cy1, cy1

$Lcj1:	sll	v2, 1, sl
	ADDSUB	u2, sl, ps
	ADDSUB	ps, cy1, rr
	srl	v2, 63, cy0
	CARRY(	ps, u2, cy)
	stq	rr, 16(rp)
	addq	cy, cy0, cy0
	CARRY(	rr, ps, cy)
	addq	cy, cy0, cy0

	ret	r31,(r26),1
EPILOGUE()
ASM_END()
@


1.1.1.1
log
@initial import of GMP 5.0.2.

GNU MP is a library for arbitrary precision arithmetic, operating on signed
integers, rational numbers, and floating point numbers.  It has a rich set
of functions, and the functions have a regular interface.

GMP is necessary for GCC >= 4.2.
@
text
@@


1.1.1.2
log
@initial import of GMP 6.1.2.  main changes from 5.1.3 below.

notes:
 - support for thumb-less ARM chips was in our port of 5.1.3, but a
   similar method has been provided upstream now
 - someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

  FEATURES
  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
    on Skylake Pentiums).
  * Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

  BUGS FIXED
  * The public function mpn_com is now correctly declared in gmp.h.
  * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
    some obsolete CPUs.
  * Various problems related to precision for mpf have been fixed.
  * Fixed ABI incompatible stack alignment in calls from assembly code.
  * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
  SPEEDUPS
  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    new ADX instructions.
  * Square root is now faster when the remainder is not needed. Also the speed
    to compute the k-th root improved, for small sizes.
  FEATURES
  * New C++ functions gcd and lcm for mpz_class.
  * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
  * New public mpq_cmp_z function, to efficiently compare rationals with
    integers.
  * Support for more 32-bit arm processors.
  * Support for AVX-less modern x86 CPUs. (Such support might be missing either
    because the CPU vendor chose to disable AVX, or because the running kernel
    lacks AVX context switch support.)
  * Support for NetBSD under Xen; we switch off AVX unconditionally under
    NetBSD since a bug in NetBSD makes AVX fail under Xen.
  MISC
  * Tuned values for FFT multiplications are provided for larger number on
    many platforms.

Changes between GMP version 5.1.* and 6.0.0
  BUGS FIXED
  * The function mpz_invert now considers any number invertible in Z/1Z.
  * The mpn multiply code now handles operands of more than 2^31 limbs
    correctly.  (Note however that the mpz code is limited to 2^32 bits on
    32-bit hosts and 2^37 bits on 64-bit hosts.)
  SPEEDUPS
  * Plain division of large operands is faster and more monotonous in operand
    size.
  * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
    assembly.
  * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
    and vastly expanded assembly support.  Speedup also for the older Core 2
    and Nehalem.
  * Faster mixed arithmetic between mpq_class and double.
  FEATURES
  * Support for new Intel and AMD CPUs.
  * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
    silent multiplication and squaring.
  * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
    side-channel silent division.
  * New public functions mpn_cnd_add_n and mpn_cnd_sub_n.  Side-channel silent
    conditional addition and subtraction.
  * New public function mpn_sec_powm, implementing side-channel silent modexp.
  * New public function mpn_sec_invert, implementing side-channel silent
    modular inversion.
  * Better support for applications which use the mpz_t type, but nevertheless
    need to call some of the lower-level mpn functions.  See the documentation
    for mpz_limbs_read and related functions.
@
text
@d3 1
a3 1
dnl  Copyright 2003, 2013 Free Software Foundation, Inc.
d6 1
a6 1
dnl
d8 4
a11 14
dnl  it under the terms of either:
dnl
dnl    * the GNU Lesser General Public License as published by the Free
dnl      Software Foundation; either version 3 of the License, or (at your
dnl      option) any later version.
dnl
dnl  or
dnl
dnl    * the GNU General Public License as published by the Free Software
dnl      Foundation; either version 2 of the License, or (at your option) any
dnl      later version.
dnl
dnl  or both in parallel, as here.
dnl
d14 5
a18 6
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
dnl  for more details.
dnl
dnl  You should have received copies of the GNU General Public License and the
dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
dnl  see https://www.gnu.org/licenses/.
d23 1
a23 1
C EV4:     ?
d25 1
a25 1
C EV6:     4.5
d27 7
d41 2
d45 2
d70 22
a91 3
	and	n, 2, cy0
	blbs	n, L(bx1)
L(bx0):	ldq	v1, 0(vp)
d93 2
a94 5
	nop
	bne	cy0, L(b10)

L(b00):	lda	vp, 48(vp)
	lda	up, -16(up)
d96 28
a123 3
	br	r31, L(lo0)

L(b10):	lda	vp, 32(vp)
d125 1
a125 18
	lda	cy0, 0(r31)
	br	r31, L(lo2)

L(bx1):	ldq	v0, 0(vp)
	ldq	u0, 0(up)
	lda	cy1, 0(r31)
	beq	cy0, L(b01)

L(b11):	lda	vp, 40(vp)
	lda	up, -24(up)
	lda	rp, 16(rp)
	br	r31, L(lo3)

L(b01):	lda	n, -4(n)
	ble	n, L(end)
	lda	vp, 24(vp)
	lda	up, -8(up)

d127 4
a130 2
L(top):	addq	v0, v0, sl	C left shift vlimb
	ldq	v1, -16(vp)
d132 2
a133 2
	cmplt	v0, r31, cy0	C carry out #1
	ldq	u1, 16(up)
d135 2
d139 1
d142 1
d145 4
a148 2
L(lo0):	addq	v1, v1, sl
	ldq	v0, -40(vp)
d150 2
a151 2
	cmplt	v1, r31, cy1
	ldq	u0, 24(up)
d153 2
d157 1
d160 1
d163 7
a169 5
L(lo3):	addq	v0, v0, sl
	ldq	v1, -32(vp)
	ADDSUB	u0, sl, ps
	cmplt	v0, r31, cy0
	ldq	u1, 32(up)
d171 3
a173 1
	CARRY(	ps, u0, cy)
d175 1
d178 1
d180 8
a187 6
	lda	up, 32(up)	C bookkeeping
L(lo2):	addq	v1, v1, sl
	ldq	v0, -24(vp)
	ADDSUB	u1, sl, ps
	cmplt	v1, r31, cy1
	ldq	u0, 8(up)
d189 3
a191 1
	CARRY(	ps, u1, cy)
d193 1
d196 1
d199 2
a200 1
	bgt	n, L(top)
d202 1
a202 1
L(end):	addq	v0, v0, sl
d205 1
a205 1
	cmplt	v0, r31, cy0
d210 22
a231 1
	addq	cy, cy0, r0
@