head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC5:1.1.1.2 netbsd-11-0-RC4:1.1.1.2 netbsd-11-0-RC3:1.1.1.2 netbsd-11-0-RC2:1.1.1.2 netbsd-11-0-RC1:1.1.1.2 gcc-14-3-0:1.1.1.3 perseant-exfatfs-base-20250801:1.1.1.2 netbsd-11:1.1.1.2.0.2 netbsd-11-base:1.1.1.2 gcc-12-5-0:1.1.1.2 perseant-exfatfs-base-20240630:1.1.1.2 gcc-12-4-0:1.1.1.2 perseant-exfatfs:1.1.1.1.0.2 perseant-exfatfs-base:1.1.1.1 gcc-12-3-0:1.1.1.1 FSF:1.1.1; locks; strict; comment @ * @; 1.1 date 2023.07.30.05.21.21; author mrg; state Exp; branches 1.1.1.1; next ; commitid tk6nV4mbc9nVEMyE; 1.1.1.1 date 2023.07.30.05.21.21; author mrg; state Exp; branches 1.1.1.1.2.1; next 1.1.1.2; commitid tk6nV4mbc9nVEMyE; 1.1.1.2 date 2024.06.30.07.35.40; author mrg; state Exp; branches; next 1.1.1.3; commitid m7BwZsPdfJvuHYfF; 1.1.1.3 date 2025.09.13.23.45.49; author mrg; state Exp; branches; next ; commitid KwhwN4krNWa6XBaG; 1.1.1.1.2.1 date 2024.07.01.01.00.58; author perseant; state Exp; branches; next ; commitid NkoYLLCQWWw9v4gF; desc @@ 1.1 log @Initial revision @ text @// Internal macros for the simd implementation -*- C++ -*- // Copyright (C) 2020-2022 Free Software Foundation, Inc. // // This file is part of the GNU ISO C++ Library. This library is free // software; you can redistribute it and/or modify it under the // terms of the GNU General Public License as published by the // Free Software Foundation; either version 3, or (at your option) // any later version. // This library is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // Under Section 7 of GPL version 3, you are granted additional // permissions described in the GCC Runtime Library Exception, version // 3.1, as published by the Free Software Foundation. // You should have received a copy of the GNU General Public License and // a copy of the GCC Runtime Library Exception along with this program; // see the files COPYING3 and COPYING.RUNTIME respectively. If not, see // . #ifndef _GLIBCXX_EXPERIMENTAL_SIMD_DETAIL_H_ #define _GLIBCXX_EXPERIMENTAL_SIMD_DETAIL_H_ #if __cplusplus >= 201703L #include #include /// @@cond undocumented #define _GLIBCXX_SIMD_BEGIN_NAMESPACE \ namespace std _GLIBCXX_VISIBILITY(default) \ { \ _GLIBCXX_BEGIN_NAMESPACE_VERSION \ namespace experimental { \ inline namespace parallelism_v2 { #define _GLIBCXX_SIMD_END_NAMESPACE \ } \ } \ _GLIBCXX_END_NAMESPACE_VERSION \ } // ISA extension detection. The following defines all the _GLIBCXX_SIMD_HAVE_XXX // macros ARM{{{ #if defined __ARM_NEON #define _GLIBCXX_SIMD_HAVE_NEON 1 #else #define _GLIBCXX_SIMD_HAVE_NEON 0 #endif #if defined __ARM_NEON && (__ARM_ARCH >= 8 || defined __aarch64__) #define _GLIBCXX_SIMD_HAVE_NEON_A32 1 #else #define _GLIBCXX_SIMD_HAVE_NEON_A32 0 #endif #if defined __ARM_NEON && defined __aarch64__ #define _GLIBCXX_SIMD_HAVE_NEON_A64 1 #else #define _GLIBCXX_SIMD_HAVE_NEON_A64 0 #endif //}}} // x86{{{ #ifdef __MMX__ #define _GLIBCXX_SIMD_HAVE_MMX 1 #else #define _GLIBCXX_SIMD_HAVE_MMX 0 #endif #if defined __SSE__ || defined __x86_64__ #define _GLIBCXX_SIMD_HAVE_SSE 1 #else #define _GLIBCXX_SIMD_HAVE_SSE 0 #endif #if defined __SSE2__ || defined __x86_64__ #define _GLIBCXX_SIMD_HAVE_SSE2 1 #else #define _GLIBCXX_SIMD_HAVE_SSE2 0 #endif #ifdef __SSE3__ #define _GLIBCXX_SIMD_HAVE_SSE3 1 #else #define _GLIBCXX_SIMD_HAVE_SSE3 0 #endif #ifdef __SSSE3__ #define _GLIBCXX_SIMD_HAVE_SSSE3 1 #else #define _GLIBCXX_SIMD_HAVE_SSSE3 0 #endif #ifdef __SSE4_1__ #define _GLIBCXX_SIMD_HAVE_SSE4_1 1 #else #define _GLIBCXX_SIMD_HAVE_SSE4_1 0 #endif #ifdef __SSE4_2__ #define _GLIBCXX_SIMD_HAVE_SSE4_2 1 #else #define _GLIBCXX_SIMD_HAVE_SSE4_2 0 #endif #ifdef __XOP__ #define _GLIBCXX_SIMD_HAVE_XOP 1 #else #define _GLIBCXX_SIMD_HAVE_XOP 0 #endif #ifdef __AVX__ #define _GLIBCXX_SIMD_HAVE_AVX 1 #else #define _GLIBCXX_SIMD_HAVE_AVX 0 #endif #ifdef __AVX2__ #define _GLIBCXX_SIMD_HAVE_AVX2 1 #else #define _GLIBCXX_SIMD_HAVE_AVX2 0 #endif #ifdef __BMI__ #define _GLIBCXX_SIMD_HAVE_BMI1 1 #else #define _GLIBCXX_SIMD_HAVE_BMI1 0 #endif #ifdef __BMI2__ #define _GLIBCXX_SIMD_HAVE_BMI2 1 #else #define _GLIBCXX_SIMD_HAVE_BMI2 0 #endif #ifdef __LZCNT__ #define _GLIBCXX_SIMD_HAVE_LZCNT 1 #else #define _GLIBCXX_SIMD_HAVE_LZCNT 0 #endif #ifdef __SSE4A__ #define _GLIBCXX_SIMD_HAVE_SSE4A 1 #else #define _GLIBCXX_SIMD_HAVE_SSE4A 0 #endif #ifdef __FMA__ #define _GLIBCXX_SIMD_HAVE_FMA 1 #else #define _GLIBCXX_SIMD_HAVE_FMA 0 #endif #ifdef __FMA4__ #define _GLIBCXX_SIMD_HAVE_FMA4 1 #else #define _GLIBCXX_SIMD_HAVE_FMA4 0 #endif #ifdef __F16C__ #define _GLIBCXX_SIMD_HAVE_F16C 1 #else #define _GLIBCXX_SIMD_HAVE_F16C 0 #endif #ifdef __POPCNT__ #define _GLIBCXX_SIMD_HAVE_POPCNT 1 #else #define _GLIBCXX_SIMD_HAVE_POPCNT 0 #endif #ifdef __AVX512F__ #define _GLIBCXX_SIMD_HAVE_AVX512F 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512F 0 #endif #ifdef __AVX512DQ__ #define _GLIBCXX_SIMD_HAVE_AVX512DQ 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512DQ 0 #endif #ifdef __AVX512VL__ #define _GLIBCXX_SIMD_HAVE_AVX512VL 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512VL 0 #endif #ifdef __AVX512BW__ #define _GLIBCXX_SIMD_HAVE_AVX512BW 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512BW 0 #endif #ifdef __AVX512BITALG__ #define _GLIBCXX_SIMD_HAVE_AVX512BITALG 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512BITALG 0 #endif #ifdef __AVX512VBMI2__ #define _GLIBCXX_SIMD_HAVE_AVX512VBMI2 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512VBMI2 0 #endif #ifdef __AVX512VBMI__ #define _GLIBCXX_SIMD_HAVE_AVX512VBMI 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512VBMI 0 #endif #ifdef __AVX512IFMA__ #define _GLIBCXX_SIMD_HAVE_AVX512IFMA 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512IFMA 0 #endif #ifdef __AVX512CD__ #define _GLIBCXX_SIMD_HAVE_AVX512CD 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512CD 0 #endif #ifdef __AVX512VNNI__ #define _GLIBCXX_SIMD_HAVE_AVX512VNNI 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512VNNI 0 #endif #ifdef __AVX512VPOPCNTDQ__ #define _GLIBCXX_SIMD_HAVE_AVX512VPOPCNTDQ 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512VPOPCNTDQ 0 #endif #ifdef __AVX512VP2INTERSECT__ #define _GLIBCXX_SIMD_HAVE_AVX512VP2INTERSECT 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512VP2INTERSECT 0 #endif #if _GLIBCXX_SIMD_HAVE_SSE #define _GLIBCXX_SIMD_HAVE_SSE_ABI 1 #else #define _GLIBCXX_SIMD_HAVE_SSE_ABI 0 #endif #if _GLIBCXX_SIMD_HAVE_SSE2 #define _GLIBCXX_SIMD_HAVE_FULL_SSE_ABI 1 #else #define _GLIBCXX_SIMD_HAVE_FULL_SSE_ABI 0 #endif #if _GLIBCXX_SIMD_HAVE_AVX #define _GLIBCXX_SIMD_HAVE_AVX_ABI 1 #else #define _GLIBCXX_SIMD_HAVE_AVX_ABI 0 #endif #if _GLIBCXX_SIMD_HAVE_AVX2 #define _GLIBCXX_SIMD_HAVE_FULL_AVX_ABI 1 #else #define _GLIBCXX_SIMD_HAVE_FULL_AVX_ABI 0 #endif #if _GLIBCXX_SIMD_HAVE_AVX512F #define _GLIBCXX_SIMD_HAVE_AVX512_ABI 1 #else #define _GLIBCXX_SIMD_HAVE_AVX512_ABI 0 #endif #if _GLIBCXX_SIMD_HAVE_AVX512BW #define _GLIBCXX_SIMD_HAVE_FULL_AVX512_ABI 1 #else #define _GLIBCXX_SIMD_HAVE_FULL_AVX512_ABI 0 #endif #if defined __x86_64__ && !_GLIBCXX_SIMD_HAVE_SSE2 #error "Use of SSE2 is required on AMD64" #endif //}}} #ifdef __clang__ #define _GLIBCXX_SIMD_NORMAL_MATH #else #define _GLIBCXX_SIMD_NORMAL_MATH \ [[__gnu__::__optimize__("finite-math-only,no-signed-zeros")]] #endif #define _GLIBCXX_SIMD_NEVER_INLINE [[__gnu__::__noinline__]] #define _GLIBCXX_SIMD_INTRINSIC \ [[__gnu__::__always_inline__, __gnu__::__artificial__]] inline #define _GLIBCXX_SIMD_ALWAYS_INLINE [[__gnu__::__always_inline__]] inline #define _GLIBCXX_SIMD_IS_UNLIKELY(__x) __builtin_expect(__x, 0) #define _GLIBCXX_SIMD_IS_LIKELY(__x) __builtin_expect(__x, 1) #if defined __STRICT_ANSI__ && __STRICT_ANSI__ #define _GLIBCXX_SIMD_CONSTEXPR #define _GLIBCXX_SIMD_USE_CONSTEXPR_API const #else #define _GLIBCXX_SIMD_CONSTEXPR constexpr #define _GLIBCXX_SIMD_USE_CONSTEXPR_API constexpr #endif #if defined __clang__ #define _GLIBCXX_SIMD_USE_CONSTEXPR const #else #define _GLIBCXX_SIMD_USE_CONSTEXPR constexpr #endif #define _GLIBCXX_SIMD_LIST_BINARY(__macro) __macro(|) __macro(&) __macro(^) #define _GLIBCXX_SIMD_LIST_SHIFTS(__macro) __macro(<<) __macro(>>) #define _GLIBCXX_SIMD_LIST_ARITHMETICS(__macro) \ __macro(+) __macro(-) __macro(*) __macro(/) __macro(%) #define _GLIBCXX_SIMD_ALL_BINARY(__macro) \ _GLIBCXX_SIMD_LIST_BINARY(__macro) static_assert(true) #define _GLIBCXX_SIMD_ALL_SHIFTS(__macro) \ _GLIBCXX_SIMD_LIST_SHIFTS(__macro) static_assert(true) #define _GLIBCXX_SIMD_ALL_ARITHMETICS(__macro) \ _GLIBCXX_SIMD_LIST_ARITHMETICS(__macro) static_assert(true) #ifdef _GLIBCXX_SIMD_NO_ALWAYS_INLINE #undef _GLIBCXX_SIMD_ALWAYS_INLINE #define _GLIBCXX_SIMD_ALWAYS_INLINE inline #undef _GLIBCXX_SIMD_INTRINSIC #define _GLIBCXX_SIMD_INTRINSIC inline #endif #if _GLIBCXX_SIMD_HAVE_SSE || _GLIBCXX_SIMD_HAVE_MMX #define _GLIBCXX_SIMD_X86INTRIN 1 #else #define _GLIBCXX_SIMD_X86INTRIN 0 #endif // workaround macros {{{ // use aliasing loads to help GCC understand the data accesses better // This also seems to hide a miscompilation on swap(x[i], x[i + 1]) with // fixed_size_simd x. #define _GLIBCXX_SIMD_USE_ALIASING_LOADS 1 // vector conversions on x86 not optimized: #if _GLIBCXX_SIMD_X86INTRIN #define _GLIBCXX_SIMD_WORKAROUND_PR85048 1 #endif // integer division not optimized #ifndef __clang__ #define _GLIBCXX_SIMD_WORKAROUND_PR90993 1 #endif // very bad codegen for extraction and concatenation of 128/256 "subregisters" // with sizeof(element type) < 8: https://godbolt.org/g/mqUsgM #if _GLIBCXX_SIMD_X86INTRIN #define _GLIBCXX_SIMD_WORKAROUND_XXX_1 1 #endif // bad codegen for 8 Byte memcpy to __vector_type_t #define _GLIBCXX_SIMD_WORKAROUND_PR90424 1 // bad codegen for zero-extend using simple concat(__x, 0) #if _GLIBCXX_SIMD_X86INTRIN #define _GLIBCXX_SIMD_WORKAROUND_XXX_3 1 #endif // https://github.com/cplusplus/parallelism-ts/issues/65 (incorrect return type // of static_simd_cast) #define _GLIBCXX_SIMD_FIX_P2TS_ISSUE65 1 // https://github.com/cplusplus/parallelism-ts/issues/66 (incorrect SFINAE // constraint on (static)_simd_cast) #define _GLIBCXX_SIMD_FIX_P2TS_ISSUE66 1 // }}} /// @@endcond #endif // __cplusplus >= 201703L #endif // _GLIBCXX_EXPERIMENTAL_SIMD_DETAIL_H_ // vim: foldmethod=marker @ 1.1.1.1 log @initial import of GCC 12.3.0. major changes in GCC 11 included: - The default mode for C++ is now -std=gnu++17 instead of -std=gnu++14. - When building GCC itself, the host compiler must now support C++11, rather than C++98. - Some short options of the gcov tool have been renamed: -i to -j and -j to -H. - ThreadSanitizer improvements. - Introduce Hardware-assisted AddressSanitizer support. - For targets that produce DWARF debugging information GCC now defaults to DWARF version 5. This can produce up to 25% more compact debug information compared to earlier versions. - Many optimisations. - The existing malloc attribute has been extended so that it can be used to identify allocator/deallocator API pairs. A pair of new -Wmismatched-dealloc and -Wmismatched-new-delete warnings are added. - Other new warnings: -Wsizeof-array-div, enabled by -Wall, warns about divisions of two sizeof operators when the first one is applied to an array and the divisor does not equal the size of the array element. -Wstringop-overread, enabled by default, warns about calls to string functions reading past the end of the arrays passed to them as arguments. -Wtsan, enabled by default, warns about unsupported features in ThreadSanitizer (currently std::atomic_thread_fence). - Enchanced warnings: -Wfree-nonheap-object detects many more instances of calls to deallocation functions with pointers not returned from a dynamic memory allocation function. -Wmaybe-uninitialized diagnoses passing pointers or references to uninitialized memory to functions taking const-qualified arguments. -Wuninitialized detects reads from uninitialized dynamically allocated memory. -Warray-parameter warns about functions with inconsistent array forms. -Wvla-parameter warns about functions with inconsistent VLA forms. - Several new features from the upcoming C2X revision of the ISO C standard are supported with -std=c2x and -std=gnu2x. - Several C++20 features have been implemented. - The C++ front end has experimental support for some of the upcoming C++23 draft. - Several new C++ warnings. - Enhanced Arm, AArch64, x86, and RISC-V CPU support. - The implementation of how program state is tracked within -fanalyzer has been completely rewritten with many enhancements. see https://gcc.gnu.org/gcc-11/changes.html for a full list. major changes in GCC 12 include: - An ABI incompatibility between C and C++ when passing or returning by value certain aggregates containing zero width bit-fields has been discovered on various targets. x86-64, ARM and AArch64 will always ignore them (so there is a C ABI incompatibility between GCC 11 and earlier with GCC 12 or later), PowerPC64 ELFv2 always take them into account (so there is a C++ ABI incompatibility, GCC 4.4 and earlier compatible with GCC 12 or later, incompatible with GCC 4.5 through GCC 11). RISC-V has changed the handling of these already starting with GCC 10. As the ABI requires, MIPS takes them into account handling function return values so there is a C++ ABI incompatibility with GCC 4.5 through 11. - STABS: Support for emitting the STABS debugging format is deprecated and will be removed in the next release. All ports now default to emit DWARF (version 2 or later) debugging info or are obsoleted. - Vectorization is enabled at -O2 which is now equivalent to the original -O2 -ftree-vectorize -fvect-cost-model=very-cheap. - GCC now supports the ShadowCallStack sanitizer. - Support for __builtin_shufflevector compatible with the clang language extension was added. - Support for attribute unavailable was added. - Support for __builtin_dynamic_object_size compatible with the clang language extension was added. - New warnings: -Wbidi-chars warns about potentially misleading UTF-8 bidirectional control characters. -Warray-compare warns about comparisons between two operands of array type. - Some new features from the upcoming C2X revision of the ISO C standard are supported with -std=c2x and -std=gnu2x. - Several C++23 features have been implemented. - Many C++ enhancements across warnings and -f options. see https://gcc.gnu.org/gcc-12/changes.html for a full list. @ text @@ 1.1.1.1.2.1 log @Sync with HEAD. @ text @a256 1 #define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA a259 1 #define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA __attribute__((__always_inline__)) d268 1 a268 1 #if __STRICT_ANSI__ || defined __clang__ a296 2 #undef _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA #define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA @ 1.1.1.2 log @import GCC 12.4.0. this includes at least 85 GCC PRs fixed, 2 C, 17 C++, 16 libstdc++-v3, at least 13 target-specific (x86, arm64, riscv mostly), and at least 24 optimisation PRs. @ text @a256 1 #define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA a259 1 #define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA __attribute__((__always_inline__)) d268 1 a268 1 #if __STRICT_ANSI__ || defined __clang__ a296 2 #undef _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA #define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA @ 1.1.1.3 log @initial import of GCC 14.3.0. major changes in GCC 13: - improved sanitizer - zstd debug info compression - LTO improvements - SARIF based diagnostic support - new warnings: -Wxor-used-as-pow, -Wenum-int-mismatch, -Wself-move, -Wdangling-reference - many new -Wanalyzer* specific warnings - enhanced warnings: -Wpessimizing-move, -Wredundant-move - new attributes to mark file descriptors, c++23 "assume" - several C23 features added - several C++23 features added - many new features for Arm, x86, RISC-V major changes in GCC 14: - more strict C99 or newer support - ia64* marked deprecated (but seemingly still in GCC 15.) - several new hardening features - support for "hardbool", which can have user supplied values of true/false - explicit support for stack scrubbing upon function exit - better auto-vectorisation support - added clang-compatible __has_feature and __has_extension - more C23, including -std=c23 - several C++26 features added - better diagnostics in C++ templates - new warnings: -Wnrvo, Welaborated-enum-base - many new features for Arm, x86, RISC-V - possible ABI breaking change for SPARC64 and small structures with arrays of floats. @ text @d3 1 a3 1 // Copyright (C) 2020-2024 Free Software Foundation, Inc. a63 10 #if (__ARM_FEATURE_SVE_BITS > 0 && __ARM_FEATURE_SVE_VECTOR_OPERATORS==1) #define _GLIBCXX_SIMD_HAVE_SVE 1 #else #define _GLIBCXX_SIMD_HAVE_SVE 0 #endif #ifdef __ARM_FEATURE_SVE2 #define _GLIBCXX_SIMD_HAVE_SVE2 1 #else #define _GLIBCXX_SIMD_HAVE_SVE2 0 #endif d270 1 a270 1 #if _GLIBCXX_SIMD_HAVE_SVE || __STRICT_ANSI__ || defined __clang__ @