head 1.6; access; symbols pkgsrc-2018Q4:1.5.0.8 pkgsrc-2018Q4-base:1.5 pkgsrc-2018Q3:1.5.0.6 pkgsrc-2018Q3-base:1.5 pkgsrc-2018Q2:1.5.0.4 pkgsrc-2018Q2-base:1.5 pkgsrc-2018Q1:1.5.0.2 pkgsrc-2018Q1-base:1.5 pkgsrc-2017Q4:1.4.0.8 pkgsrc-2017Q4-base:1.4 pkgsrc-2017Q3:1.4.0.6 pkgsrc-2017Q3-base:1.4 pkgsrc-2017Q2:1.4.0.2 pkgsrc-2017Q2-base:1.4 pkgsrc-2017Q1:1.3.0.20 pkgsrc-2017Q1-base:1.3 pkgsrc-2016Q4:1.3.0.18 pkgsrc-2016Q4-base:1.3 pkgsrc-2016Q3:1.3.0.16 pkgsrc-2016Q3-base:1.3 pkgsrc-2016Q2:1.3.0.14 pkgsrc-2016Q2-base:1.3 pkgsrc-2016Q1:1.3.0.12 pkgsrc-2016Q1-base:1.3 pkgsrc-2015Q4:1.3.0.10 pkgsrc-2015Q4-base:1.3 pkgsrc-2015Q3:1.3.0.8 pkgsrc-2015Q3-base:1.3 pkgsrc-2015Q2:1.3.0.6 pkgsrc-2015Q2-base:1.3 pkgsrc-2015Q1:1.3.0.4 pkgsrc-2015Q1-base:1.3 pkgsrc-2014Q4:1.3.0.2 pkgsrc-2014Q4-base:1.3 pkgsrc-2014Q3:1.2.0.12 pkgsrc-2014Q3-base:1.2 pkgsrc-2014Q2:1.2.0.10 pkgsrc-2014Q2-base:1.2 pkgsrc-2014Q1:1.2.0.8 pkgsrc-2014Q1-base:1.2 pkgsrc-2013Q4:1.2.0.6 pkgsrc-2013Q4-base:1.2 pkgsrc-2013Q3:1.2.0.4 pkgsrc-2013Q3-base:1.2 pkgsrc-2013Q2:1.2.0.2 pkgsrc-2013Q2-base:1.2 pkgsrc-2013Q1:1.1.0.10 pkgsrc-2013Q1-base:1.1 pkgsrc-2012Q4:1.1.0.8 pkgsrc-2012Q4-base:1.1 pkgsrc-2012Q3:1.1.0.6 pkgsrc-2012Q3-base:1.1 pkgsrc-2012Q2:1.1.0.4 pkgsrc-2012Q2-base:1.1 pkgsrc-2012Q1:1.1.0.2 pkgsrc-2012Q1-base:1.1; locks; strict; comment @# @; 1.6 date 2019.01.04.13.35.16; author ryoon; state dead; branches; next 1.5; commitid 9UGgsXAcvjGK8t6B; 1.5 date 2018.03.21.17.39.42; author kamil; state Exp; branches; next 1.4; commitid dw9VIWi1Ykh8MlvA; 1.4 date 2017.05.11.12.38.30; author christos; state Exp; branches; next 1.3; commitid LqSYQR0DOcNScYQz; 1.3 date 2014.12.08.20.55.19; author ryoon; state Exp; branches; next 1.2; commitid 2DoxWZqBKFg8ph1y; 1.2 date 2013.06.29.08.24.53; author mrg; state Exp; branches; next 1.1; commitid 3tX4cUMvgWPGbuVw; 1.1 date 2012.02.06.05.37.40; author matt; state Exp; branches; next ; desc @@ 1.6 log @Update to 0.6.1 * Update MASTER_SITES and HOMEPAGE Changelog: * Support OpenBSD/sgi 6.4 * Add luna-88k and luna-88k2 emulations * Add i960 emulation stub @ text @$NetBSD: patch-ag,v 1.5 2018/03/21 17:39:42 kamil Exp $ - enable all CPSR->SPSR copy values, instead of hard coding 3 out of 15. - allow immediate to be zero with a non-zero shift. caused by: ebf61a60: e28fc600 add ip,pc,#0 - Fix C++11 literals. --- src/cpus/cpu_arm_instr.cc.orig 2014-08-17 08:45:15.000000000 +0000 +++ src/cpus/cpu_arm_instr.cc @@@@ -215,7 +215,7 @@@@ X(invalid) { fatal("FATAL ERROR: An internal error occured in the ARM" " dyntrans code. Please contact the author with detailed" - " repro steps on how to trigger this bug. pc = 0x%08"PRIx32"\n", + " repro steps on how to trigger this bug. pc = 0x%08" PRIx32 "\n", (uint32_t)cpu->pc); cpu->cd.arm.next_ic = ¬hing_call; @@@@ -803,7 +803,7 @@@@ X(msr_imm_spsr) cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT); cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); old_pc = cpu->pc; - printf("msr_spsr: old pc = 0x%08"PRIx32"\n", old_pc); + printf("msr_spsr: old pc = 0x%08" PRIx32 "\n", old_pc); } exit(1); } @@@@ -2670,6 +2670,7 @@@@ X(to_be_translated) ic->f = cond_instr(bx); } ic->arg[0] = (size_t)(&cpu->cd.arm.r[rm]); + ic->arg[2] = (addr & 0xffc) + 4; break; } if ((iword & 0x0fb00ff0) == 0x1000090) { @@@@ -2888,7 +2889,7 @@@@ X(to_be_translated) while (r8-- > 0) imm = (imm >> 2) | ((imm & 3) << 30); - if (steps != 0 && imm < 256) { + if (steps != 0 && imm < 256 && imm != 0) { if (!cpu->translation_readahead) fatal("TODO: see cpu_arm_instr_dpi; non-zero steps but still under 256 is not implemented yet\n"); goto bad; @@@@ -3205,4 +3206,3 @@@@ okay: #include "cpu_dyntrans.cc" #undef DYNTRANS_TO_BE_TRANSLATED_TAIL } - @ 1.5 log @gxemul: Fix build with clang 7svn Fix C++11 literals, they are now fatal. Reverting to C++98 does not work as it is, as this code uses C++11 extensions like 'PRIx32' macros. Extend one int to long in order to handle all values in a switch() case. No functional change intended. @ text @d1 1 a1 1 $NetBSD: patch-ag,v 1.4 2017/05/11 12:38:30 christos Exp $ @ 1.4 log @fix cats kernel: TODO: see cpu_arm_instr_dpi; non-zero steps but still under 256 is not implemented yet to_be_translated(): TODO: unimplemented instruction: ebf61a60: e28fc600 add ip,pc,#0 @ text @d1 1 a1 1 $NetBSD: patch-ag,v 1.3 2014/12/08 20:55:19 ryoon Exp $ d6 1 d8 21 a28 3 --- src/cpus/cpu_arm_instr.cc.orig 2014-08-17 04:45:15.000000000 -0400 +++ src/cpus/cpu_arm_instr.cc 2017-05-11 08:36:16.634585212 -0400 @@@@ -2670,6 +2670,7 @@@@ d36 1 a36 1 @@@@ -2888,7 +2889,7 @@@@ d45 5 @ 1.3 log @Update to 0.6.0.1 Changelog: [20140817] Release 0.6.0.1. It has been a while since the last release, and the SVN repository mirror at Sourceforge seems to be broken, so it felt reasonable to package the current code into a patch release. Not much has happened feature-wise since 0.6.0. [20140816] On FreeBSD/amd64 with GCC 4.2.1 as the default compiler, you may need to install GCC 4.8.4 and run the configure script like this to avoid triggering a bug in the default compiler: CXX=c++48 CXXFLAGS=-Wl,-rpath,/usr/local/lib/gcc48 ./configure [20110820] Not much coding lately. The only thing worth mentioning is that the Dreamcast emulation mode now gets further when running Marcus Comstedt's test programs, and also shows "something" when booting the PROM from my real Dreamcast. (This was in the legacy Dreamcast mode, for fun. I haven't had time to work on the new framework at all.) [20100729] Uploaded a clip to YouTube, showing the NetBSD/pmax install procedure in GXemul. @ text @d1 1 a1 1 $NetBSD: patch-ag,v 1.2 2013/06/29 08:24:53 mrg Exp $ d3 3 a5 1 enable all CPSR->SPSR copy values, instead of hard coding 3 out of 15. d7 3 a9 4 --- src/cpus/cpu_arm_instr.cc.orig 2014-08-17 08:45:15.000000000 +0000 +++ src/cpus/cpu_arm_instr.cc @@@@ -2670,6 +2670,7 @@@@ X(to_be_translated) d17 9 @ 1.2 log @add support for more ways of writing to arm SPSR, as needed by netbsd/arm32 ports since about 6 or so months ago. bump pkg version. ok agc. @ text @d1 1 a1 1 $NetBSD: patch-ag,v 1.1 2012/02/06 05:37:40 matt Exp $ d6 3 a8 3 --- src/cpus/cpu_arm_instr.cc.orig 2010-02-14 09:33:54.000000000 +0000 +++ src/cpus/cpu_arm_instr.cc 2013-06-29 07:03:52.000000000 +0000 @@@@ -2631,6 +2631,7 @@@@ a15 33 @@@@ -2682,6 +2683,7 @@@@ (iword & 0x0fb0f000) == 0x0320f000) { /* msr: move to [S|C]PSR from a register or immediate value */ + uint32_t mask; if (iword & 0x02000000) { if (iword & 0x00400000) ic->f = cond_instr(msr_imm_spsr); @@@@ -2703,14 +2705,16 @@@@ imm = (imm >> 2) | ((imm & 3) << 30); ic->arg[0] = imm; ic->arg[2] = (size_t)(&cpu->cd.arm.r[rm]); - switch ((iword >> 16) & 15) { - case 1: ic->arg[1] = 0x000000ff; break; - case 8: ic->arg[1] = 0xff000000; break; - case 9: ic->arg[1] = 0xff0000ff; break; - default:if (!cpu->translation_readahead) - fatal("unimpl a: msr regform\n"); - goto bad; - } + ic->arg[1] = 0; + mask = (iword >> 16) & 15; + if (mask & 1) + ic->arg[1] |= 0x000000ff; + if (mask & 2) + ic->arg[1] |= 0x0000ff00; + if (mask & 4) + ic->arg[1] |= 0x00ff0000; + if (mask & 8) + ic->arg[1] |= 0xff000000; break; } if ((iword & 0x0fbf0fff) == 0x010f0000) { @ 1.1 log @Fix a bug in blx rM register emulation on arm. @ text @d1 1 a1 1 $NetBSD$ d3 6 a8 3 --- src/cpus/cpu_arm_instr.cc.orig 2012-02-06 05:14:31.000000000 +0000 +++ src/cpus/cpu_arm_instr.cc @@@@ -2631,6 +2631,7 @@@@ X(to_be_translated) d16 33 @