head	1.3;
access;
symbols
	netbsd-11-0-RC4:1.3
	netbsd-11-0-RC3:1.3
	netbsd-11-0-RC2:1.3
	netbsd-11-0-RC1:1.3
	perseant-exfatfs-base-20250801:1.3
	netbsd-11:1.3.0.12
	netbsd-11-base:1.3
	netbsd-10-1-RELEASE:1.3
	perseant-exfatfs-base-20240630:1.3
	perseant-exfatfs:1.3.0.10
	perseant-exfatfs-base:1.3
	netbsd-9-4-RELEASE:1.2
	netbsd-10-0-RELEASE:1.3
	netbsd-10-0-RC6:1.3
	netbsd-10-0-RC5:1.3
	netbsd-10-0-RC4:1.3
	netbsd-10-0-RC3:1.3
	netbsd-10-0-RC2:1.3
	thorpej-ifq:1.3.0.8
	thorpej-ifq-base:1.3
	thorpej-altq-separation:1.3.0.6
	thorpej-altq-separation-base:1.3
	netbsd-10-0-RC1:1.3
	netbsd-10:1.3.0.4
	netbsd-10-base:1.3
	bouyer-sunxi-drm:1.3.0.2
	bouyer-sunxi-drm-base:1.3
	netbsd-9-3-RELEASE:1.2
	linux-drm-v5-6-rc3:1.1.1.2
	thorpej-i2c-spi-conf2:1.2.0.30
	thorpej-i2c-spi-conf2-base:1.2
	thorpej-futex2:1.2.0.28
	thorpej-futex2-base:1.2
	thorpej-cfargs2:1.2.0.26
	thorpej-cfargs2-base:1.2
	cjep_sun2x-base1:1.2
	cjep_sun2x:1.2.0.24
	cjep_sun2x-base:1.2
	cjep_staticlib_x-base1:1.2
	netbsd-9-2-RELEASE:1.2
	cjep_staticlib_x:1.2.0.22
	cjep_staticlib_x-base:1.2
	thorpej-i2c-spi-conf:1.2.0.20
	thorpej-i2c-spi-conf-base:1.2
	thorpej-cfargs:1.2.0.18
	thorpej-cfargs-base:1.2
	thorpej-futex:1.2.0.16
	thorpej-futex-base:1.2
	netbsd-9-1-RELEASE:1.2
	bouyer-xenpvh-base2:1.2
	phil-wifi-20200421:1.2
	bouyer-xenpvh-base1:1.2
	phil-wifi-20200411:1.2
	bouyer-xenpvh:1.2.0.14
	bouyer-xenpvh-base:1.2
	is-mlppp:1.2.0.12
	is-mlppp-base:1.2
	phil-wifi-20200406:1.2
	ad-namecache-base3:1.2
	netbsd-9-0-RELEASE:1.2
	netbsd-9-0-RC2:1.2
	ad-namecache-base2:1.2
	ad-namecache-base1:1.2
	ad-namecache:1.2.0.10
	ad-namecache-base:1.2
	netbsd-9-0-RC1:1.2
	phil-wifi-20191119:1.2
	netbsd-9:1.2.0.8
	netbsd-9-base:1.2
	phil-wifi:1.2.0.6
	phil-wifi-20190609:1.2
	isaki-audio2:1.2.0.4
	isaki-audio2-base:1.2
	pgoyette-compat-merge-20190127:1.2.2.2
	pgoyette-compat-20190127:1.2
	pgoyette-compat-20190118:1.2
	pgoyette-compat-1226:1.2
	pgoyette-compat-1126:1.2
	pgoyette-compat-1020:1.2
	pgoyette-compat-0930:1.2
	pgoyette-compat:1.2.0.2
	pgoyette-compat-0906:1.2
	linux-drm-v4-4-143:1.1.1.1
	LINUX:1.1.1;
locks; strict;
comment	@# @;


1.3
date	2021.12.18.23.45.36;	author riastradh;	state Exp;
branches;
next	1.2;
commitid	Zzh9v7Bb24ydPblD;

1.2
date	2018.08.27.04.58.32;	author riastradh;	state Exp;
branches
	1.2.2.1
	1.2.6.1;
next	1.1;
commitid	SZZre9lWvwC1sIPA;

1.1
date	2018.08.27.01.34.56;	author riastradh;	state Exp;
branches
	1.1.1.1;
next	;
commitid	J8kFZ57DI7RmkHPA;

1.2.2.1
date	2018.08.27.04.58.32;	author pgoyette;	state dead;
branches;
next	1.2.2.2;
commitid	HCi1bXD317XIK0RA;

1.2.2.2
date	2018.09.06.06.56.26;	author pgoyette;	state Exp;
branches;
next	;
commitid	HCi1bXD317XIK0RA;

1.2.6.1
date	2018.08.27.04.58.32;	author christos;	state dead;
branches;
next	1.2.6.2;
commitid	jtc8rnCzWiEEHGqB;

1.2.6.2
date	2019.06.10.22.08.18;	author christos;	state Exp;
branches;
next	;
commitid	jtc8rnCzWiEEHGqB;

1.1.1.1
date	2018.08.27.01.34.56;	author riastradh;	state Exp;
branches;
next	1.1.1.2;
commitid	J8kFZ57DI7RmkHPA;

1.1.1.2
date	2021.12.18.20.15.39;	author riastradh;	state Exp;
branches;
next	;
commitid	Qm9wp54q2SRJDalD;


desc
@@


1.3
log
@Merge linux-drm-v5-6-rc3
@
text
@/* fuc microcode for gf100 PGRAPH/GPC
 *
 * Copyright 2011 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

/* TODO
 * - bracket certain functions with scratch writes, useful for debugging
 * - watchdog timer around ctx operations
 */

#ifdef INCLUDE_DATA
gpc_mmio_list_head:	.b32 #mmio_list_base
gpc_mmio_list_tail:
tpc_mmio_list_head:	.b32 #mmio_list_base
tpc_mmio_list_tail:
unk_mmio_list_head:	.b32 #mmio_list_base
unk_mmio_list_tail:	.b32 #mmio_list_base

gpc_id:			.b32 0

tpc_count:		.b32 0
tpc_mask:		.b32 0

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
unk_count:		.b32 0
unk_mask:		.b32 0
#endif

cmd_queue:		queue_init

mmio_list_base:
#endif

#ifdef INCLUDE_CODE
#define gpc_addr(reg,addr)                                                    /*
*/	imm32(reg,addr)                                                       /*
*/	or reg NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE
#define gpc_wr32(addr,reg)                                                    /*
*/	gpc_addr($r14,addr)                                                   /*
*/	mov b32 $r15 reg                                                      /*
*/	call(nv_wr32)

// reports an exception to the host
//
// In: $r15 error code (see os.h)
//
error:
	push $r14
	nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15)
	mov $r15 1
	nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15)
	pop $r14
	ret

#if CHIPSET >= GM107
tpc_strand_wait:
	push $r9
	trace_set(T_STRTPC)
	tpc_strand_busy:
		nv_iord($r9, NV_PGRAPH_GPCX_GPCCS_TPC_STATUS, 0)
		bra b32 $r9 0x0 ne #tpc_strand_busy
	trace_clr(T_STRTPC)
	pop $r9
	ret

#define tpc_strand_wait() call(tpc_strand_wait)
#define tpc_strand_enable()                                                   /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_ENABLE                        /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	tpc_strand_wait()
#define tpc_strand_disable()                                                  /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_DISABLE                       /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	tpc_strand_wait()
#define tpc_strand_seek(p)                                                    /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL                         /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)                      /*
*/	mov $r15 p                                                            /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_SELECT, $r15)                     /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SEEK                          /*
*/	tpc_strand_wait()
#define tpc_strand_info(m)                                                    /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	mov $r15 m                                                            /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_DATA, $r15)                       /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_GET_INFO                      /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	tpc_strand_wait()
#endif


// GPC fuc initialisation, executed by triggering ucode start, will
// fall through to main loop after completion.
//
// Input:
//   CC_SCRATCH[1]: context base
//
// Output:
//   CC_SCRATCH[0]:
//	     31:31: set to signal completion
//   CC_SCRATCH[1]:
//	      31:0: GPC context size
//
init:
	clear b32 $r0

	// setup stack
	nv_iord($r1, NV_PGRAPH_GPCX_GPCCS_CAPS, 0)
	extr $r1 $r1 9:17
	shl b32 $r1 8
	mov $sp $r1

	// enable fifo access
	mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2)

	// setup i0 handler, and route all interrupts to it
	mov $r1 #ih
	mov $iv0 $r1
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0)

	// enable fifo interrupt
	mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2)

	// enable interrupts
	bset $flags ie0

	// how many TPCs do we have?
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
	mov $r3 1
	and $r2 0x1f
	shl b32 $r3 $r2
	sub b32 $r3 1
	st b32 D[$r0 + #tpc_count] $r2
	st b32 D[$r0 + #tpc_mask] $r3

	// determine which GPC we are, setup (optional) mmio access offset
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
	st b32 D[$r0 + #gpc_id] $r2
	shl b32 $r2 15
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMIO_BASE, 0, $r2)

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// figure out which, and how many, UNKs are actually present
	gpc_addr($r14, 0x500c30)
	clear b32 $r2
	clear b32 $r3
	clear b32 $r4
	init_unk_loop:
		call(nv_rd32)
		cmp b32 $r15 0
		bra z #init_unk_next
			mov $r15 1
			shl b32 $r15 $r2
			or $r4 $r15
			add b32 $r3 1
		init_unk_next:
		add b32 $r2 1
		add b32 $r14 4
		cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
		bra ne #init_unk_loop
	init_unk_done:
	st b32 D[$r0 + #unk_count] $r3
	st b32 D[$r0 + #unk_mask] $r4
#endif

	// initialise context base, and size tracking
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0)
	clear b32 $r3		// track GPC context size here

	// set mmctx base addresses now so we don't have to do it later,
	// they don't currently ever change
	shr b32 $r5 $r2 8
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5)
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5)

	// calculate GPC mmio context size
	ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
	ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
	call(mmctx_size)
	add b32 $r2 $r15
	add b32 $r3 $r15

	// calculate per-TPC mmio context size
	ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
	ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
	call(mmctx_size)
	ld b32 $r14 D[$r0 + #tpc_count]
	mulu $r14 $r15
	add b32 $r2 $r14
	add b32 $r3 $r14

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// calculate per-UNK mmio context size
	ld b32 $r14 D[$r0 + #unk_mmio_list_head]
	ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
	call(mmctx_size)
	ld b32 $r14 D[$r0 + #unk_count]
	mulu $r14 $r15
	add b32 $r2 $r14
	add b32 $r3 $r14
#endif

	// round up base/size to 256 byte boundary (for strand SWBASE)
	shr b32 $r3 2
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?!
	shr b32 $r2 8
	shr b32 $r3 6
	add b32 $r2 1
	add b32 $r3 1
	shl b32 $r2 8
	shl b32 $r3 8

	// calculate size of strand context data
	mov b32 $r15 $r2
	call(strand_ctx_init)
	add b32 $r2 $r15
	add b32 $r3 $r15

#if CHIPSET >= GM107
	// calculate size of tpc strand context data
	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
	tpc_strand_enable();
	tpc_strand_seek(0);
	tpc_strand_info(-1);

	ld b32 $r4 D[$r0 + #tpc_count]
	gpc_addr($r5, NV_PGRAPH_GPC0_TPC0)
	tpc_strand_init_tpc_loop:
		add b32 $r14 $r5 NV_TPC_STRAND_CNT
		call(nv_rd32)
		mov b32 $r6 $r15
		clear b32 $r7
		tpc_strand_init_idx_loop:
			add b32 $r14 $r5 NV_TPC_STRAND_INDEX
			mov b32 $r15 $r7
			call(nv_wr32)
			add b32 $r14 $r5 NV_TPC_STRAND_SAVE_SWBASE
			shr b32 $r15 $r2 8
			call(nv_wr32)
			add b32 $r14 $r5 NV_TPC_STRAND_LOAD_SWBASE
			shr b32 $r15 $r2 8
			call(nv_wr32)
			add b32 $r14 $r5 NV_TPC_STRAND_WORDS
			call(nv_rd32)
			shr b32 $r15 6
			add b32 $r15 1
			shl b32 $r15 8
			add b32 $r2 $r15
			add b32 $r3 $r15
			add b32 $r7 1
			sub b32 $r6 1
			bra nz #tpc_strand_init_idx_loop
		add b32 $r5 NV_PGRAPH_GPC0_TPC0__SIZE
		sub b32 $r4 1
		bra nz #tpc_strand_init_tpc_loop

	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
	tpc_strand_disable();
#endif

	// save context size, and tell HUB we're done
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
	clear b32 $r2
	bset $r2 31
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2)

// Main program loop, very simple, sleeps until woken up by the interrupt
// handler, pulls a command from the queue and executes its handler
//
wait:
	sleep $p0
	bset $flags $p0
main:
	mov $r13 #cmd_queue
	call(queue_get)
	bra $p1 #wait

	// 0x0000-0x0003 are all context transfers
	cmpu b32 $r14 0x04
	bra nc #main_not_ctx_xfer
		// fetch $flags and mask off $p1/$p2
		mov $r1 $flags
		mov $r2 0x0006
		not b32 $r2
		and $r1 $r2
		// set $p1/$p2 according to transfer type
		shl b32 $r14 1
		or $r1 $r14
		mov $flags $r1
		// transfer context data
		call(ctx_xfer)
		bra #main

	main_not_ctx_xfer:
	shl b32 $r15 $r14 16
	or $r15 E_BAD_COMMAND
	call(error)
	bra #main

// interrupt handler
ih:
	push $r0
	push $r8
	mov $r8 $flags
	push $r8
	push $r9
	push $r10
	push $r11
	push $r13
	push $r14
	push $r15
	clear b32 $r0

	// incoming fifo command?
	nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0)
	and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO
	bra e #ih_no_fifo
		// queue incoming fifo command for later processing
		mov $r13 #cmd_queue
		nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0)
		nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0)
		call(queue_put)
		mov $r14 1
		nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14)

	// ack, and wake up main()
	ih_no_fifo:
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10)

	pop $r15
	pop $r14
	pop $r13
	pop $r11
	pop $r10
	pop $r9
	pop $r8
	mov $flags $r8
	pop $r8
	pop $r0
	bclr $flags $p0
	iret

// Set this GPC's bit in HUB_BAR, used to signal completion of various
// activities to the HUB fuc
//
hub_barrier_done:
	mov $r15 1
	ld b32 $r14 D[$r0 + #gpc_id]
	shl b32 $r15 $r14
	nv_wr32(0x409418, $r15)	// 0x409418 - HUB_BAR_SET
	ret

// Disables various things, waits a bit, and re-enables them..
//
// Not sure how exactly this helps, perhaps "ENABLE" is not such a
// good description for the bits we turn off?  Anyways, without this,
// funny things happen.
//
ctx_redswitch:
	mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
	mov $r14 8
	ctx_redswitch_delay:
		sub b32 $r14 1
		bra ne #ctx_redswitch_delay
	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11
	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
	ret

// Transfer GPC context data between GPU and storage area
//
// In: $r15 context base address
//     $p1 clear on save, set on load
//     $p2 set if opposite direction done/will be done, so:
//		on save it means: "a load will follow this save"
//		on load it means: "a save preceeded this load"
//
ctx_xfer:
	// set context base address
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15)
#if CHIPSET >= GM107
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_MEM_BASE, $r15)
#endif
	bra not $p1 #ctx_xfer_not_load
		call(ctx_redswitch)
	ctx_xfer_not_load:

	// strands
	call(strand_pre)
	clear b32 $r2
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2)
	xbit $r2 $flags $p1	// SAVE/LOAD
	add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2)

#if CHIPSET >= GM107
	tpc_strand_enable();
	tpc_strand_seek(0);
	xbit $r15 $flags $p1	// SAVE/LOAD
	add b32 $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SAVE
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)
#endif

	// mmio context
	xbit $r10 $flags $p1	// direction
	or $r10 2		// first
	imm32($r11,0x500000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn
	ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
	ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
	mov $r14 0		// not multi
	call(mmctx_xfer)

	// per-TPC mmio context
	xbit $r10 $flags $p1	// direction
#if !NV_PGRAPH_GPCX_UNK__SIZE
	or $r10 4		// last
#endif
	imm32($r11, 0x504000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_TPC0
	ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
	ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
	ld b32 $r15 D[$r0 + #tpc_mask]
	mov $r14 0x800		// stride = 0x800
	call(mmctx_xfer)

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// per-UNK mmio context
	xbit $r10 $flags $p1	// direction
	or $r10 4		// last
	imm32($r11, 0x503000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_UNK0
	ld b32 $r12 D[$r0 + #unk_mmio_list_head]
	ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
	ld b32 $r15 D[$r0 + #unk_mask]
	mov $r14 0x200		// stride = 0x200
	call(mmctx_xfer)
#endif

	// wait for strands to finish
	call(strand_wait)
#if CHIPSET >= GM107
	tpc_strand_wait()
#endif

	// if load, or a save without a load following, do some
	// unknown stuff that's done after finishing a block of
	// strand commands
	bra $p1 #ctx_xfer_post
	bra not $p2 #ctx_xfer_done
	ctx_xfer_post:
		call(strand_post)
#if CHIPSET >= GM107
		tpc_strand_disable()
#endif

	// mark completion in HUB's barrier
	ctx_xfer_done:
	call(hub_barrier_done)
	ret
#endif
@


1.2
log
@merge linux-drm-v4-4-143
@
text
@d250 1
a250 4
	mov $r5 NV_PGRAPH_GPC0_TPC0
	ld b32 $r6 D[$r0 + #gpc_id]
	shl b32 $r6 15
	add b32 $r5 $r6
d294 3
a297 2
	bset $flags $p0
	sleep $p0
d300 1
a300 1
	bra $p1 #main
d326 1
d363 1
@


1.2.6.1
log
@file gpc.fuc was added on branch phil-wifi on 2019-06-10 22:08:18 +0000
@
text
@d1 492
@


1.2.6.2
log
@Sync with HEAD
@
text
@a0 492
/* fuc microcode for gf100 PGRAPH/GPC
 *
 * Copyright 2011 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

/* TODO
 * - bracket certain functions with scratch writes, useful for debugging
 * - watchdog timer around ctx operations
 */

#ifdef INCLUDE_DATA
gpc_mmio_list_head:	.b32 #mmio_list_base
gpc_mmio_list_tail:
tpc_mmio_list_head:	.b32 #mmio_list_base
tpc_mmio_list_tail:
unk_mmio_list_head:	.b32 #mmio_list_base
unk_mmio_list_tail:	.b32 #mmio_list_base

gpc_id:			.b32 0

tpc_count:		.b32 0
tpc_mask:		.b32 0

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
unk_count:		.b32 0
unk_mask:		.b32 0
#endif

cmd_queue:		queue_init

mmio_list_base:
#endif

#ifdef INCLUDE_CODE
#define gpc_addr(reg,addr)                                                    /*
*/	imm32(reg,addr)                                                       /*
*/	or reg NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE
#define gpc_wr32(addr,reg)                                                    /*
*/	gpc_addr($r14,addr)                                                   /*
*/	mov b32 $r15 reg                                                      /*
*/	call(nv_wr32)

// reports an exception to the host
//
// In: $r15 error code (see os.h)
//
error:
	push $r14
	nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15)
	mov $r15 1
	nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15)
	pop $r14
	ret

#if CHIPSET >= GM107
tpc_strand_wait:
	push $r9
	trace_set(T_STRTPC)
	tpc_strand_busy:
		nv_iord($r9, NV_PGRAPH_GPCX_GPCCS_TPC_STATUS, 0)
		bra b32 $r9 0x0 ne #tpc_strand_busy
	trace_clr(T_STRTPC)
	pop $r9
	ret

#define tpc_strand_wait() call(tpc_strand_wait)
#define tpc_strand_enable()                                                   /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_ENABLE                        /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	tpc_strand_wait()
#define tpc_strand_disable()                                                  /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_DISABLE                       /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	tpc_strand_wait()
#define tpc_strand_seek(p)                                                    /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL                         /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)                      /*
*/	mov $r15 p                                                            /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_SELECT, $r15)                     /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SEEK                          /*
*/	tpc_strand_wait()
#define tpc_strand_info(m)                                                    /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	mov $r15 m                                                            /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_DATA, $r15)                       /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_GET_INFO                      /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	tpc_strand_wait()
#endif


// GPC fuc initialisation, executed by triggering ucode start, will
// fall through to main loop after completion.
//
// Input:
//   CC_SCRATCH[1]: context base
//
// Output:
//   CC_SCRATCH[0]:
//	     31:31: set to signal completion
//   CC_SCRATCH[1]:
//	      31:0: GPC context size
//
init:
	clear b32 $r0

	// setup stack
	nv_iord($r1, NV_PGRAPH_GPCX_GPCCS_CAPS, 0)
	extr $r1 $r1 9:17
	shl b32 $r1 8
	mov $sp $r1

	// enable fifo access
	mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2)

	// setup i0 handler, and route all interrupts to it
	mov $r1 #ih
	mov $iv0 $r1
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0)

	// enable fifo interrupt
	mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2)

	// enable interrupts
	bset $flags ie0

	// how many TPCs do we have?
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
	mov $r3 1
	and $r2 0x1f
	shl b32 $r3 $r2
	sub b32 $r3 1
	st b32 D[$r0 + #tpc_count] $r2
	st b32 D[$r0 + #tpc_mask] $r3

	// determine which GPC we are, setup (optional) mmio access offset
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
	st b32 D[$r0 + #gpc_id] $r2
	shl b32 $r2 15
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMIO_BASE, 0, $r2)

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// figure out which, and how many, UNKs are actually present
	gpc_addr($r14, 0x500c30)
	clear b32 $r2
	clear b32 $r3
	clear b32 $r4
	init_unk_loop:
		call(nv_rd32)
		cmp b32 $r15 0
		bra z #init_unk_next
			mov $r15 1
			shl b32 $r15 $r2
			or $r4 $r15
			add b32 $r3 1
		init_unk_next:
		add b32 $r2 1
		add b32 $r14 4
		cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
		bra ne #init_unk_loop
	init_unk_done:
	st b32 D[$r0 + #unk_count] $r3
	st b32 D[$r0 + #unk_mask] $r4
#endif

	// initialise context base, and size tracking
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0)
	clear b32 $r3		// track GPC context size here

	// set mmctx base addresses now so we don't have to do it later,
	// they don't currently ever change
	shr b32 $r5 $r2 8
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5)
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5)

	// calculate GPC mmio context size
	ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
	ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
	call(mmctx_size)
	add b32 $r2 $r15
	add b32 $r3 $r15

	// calculate per-TPC mmio context size
	ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
	ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
	call(mmctx_size)
	ld b32 $r14 D[$r0 + #tpc_count]
	mulu $r14 $r15
	add b32 $r2 $r14
	add b32 $r3 $r14

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// calculate per-UNK mmio context size
	ld b32 $r14 D[$r0 + #unk_mmio_list_head]
	ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
	call(mmctx_size)
	ld b32 $r14 D[$r0 + #unk_count]
	mulu $r14 $r15
	add b32 $r2 $r14
	add b32 $r3 $r14
#endif

	// round up base/size to 256 byte boundary (for strand SWBASE)
	shr b32 $r3 2
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?!
	shr b32 $r2 8
	shr b32 $r3 6
	add b32 $r2 1
	add b32 $r3 1
	shl b32 $r2 8
	shl b32 $r3 8

	// calculate size of strand context data
	mov b32 $r15 $r2
	call(strand_ctx_init)
	add b32 $r2 $r15
	add b32 $r3 $r15

#if CHIPSET >= GM107
	// calculate size of tpc strand context data
	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
	tpc_strand_enable();
	tpc_strand_seek(0);
	tpc_strand_info(-1);

	ld b32 $r4 D[$r0 + #tpc_count]
	mov $r5 NV_PGRAPH_GPC0_TPC0
	ld b32 $r6 D[$r0 + #gpc_id]
	shl b32 $r6 15
	add b32 $r5 $r6
	tpc_strand_init_tpc_loop:
		add b32 $r14 $r5 NV_TPC_STRAND_CNT
		call(nv_rd32)
		mov b32 $r6 $r15
		clear b32 $r7
		tpc_strand_init_idx_loop:
			add b32 $r14 $r5 NV_TPC_STRAND_INDEX
			mov b32 $r15 $r7
			call(nv_wr32)
			add b32 $r14 $r5 NV_TPC_STRAND_SAVE_SWBASE
			shr b32 $r15 $r2 8
			call(nv_wr32)
			add b32 $r14 $r5 NV_TPC_STRAND_LOAD_SWBASE
			shr b32 $r15 $r2 8
			call(nv_wr32)
			add b32 $r14 $r5 NV_TPC_STRAND_WORDS
			call(nv_rd32)
			shr b32 $r15 6
			add b32 $r15 1
			shl b32 $r15 8
			add b32 $r2 $r15
			add b32 $r3 $r15
			add b32 $r7 1
			sub b32 $r6 1
			bra nz #tpc_strand_init_idx_loop
		add b32 $r5 NV_PGRAPH_GPC0_TPC0__SIZE
		sub b32 $r4 1
		bra nz #tpc_strand_init_tpc_loop

	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
	tpc_strand_disable();
#endif

	// save context size, and tell HUB we're done
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
	clear b32 $r2
	bset $r2 31
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2)

// Main program loop, very simple, sleeps until woken up by the interrupt
// handler, pulls a command from the queue and executes its handler
//
main:
	bset $flags $p0
	sleep $p0
	mov $r13 #cmd_queue
	call(queue_get)
	bra $p1 #main

	// 0x0000-0x0003 are all context transfers
	cmpu b32 $r14 0x04
	bra nc #main_not_ctx_xfer
		// fetch $flags and mask off $p1/$p2
		mov $r1 $flags
		mov $r2 0x0006
		not b32 $r2
		and $r1 $r2
		// set $p1/$p2 according to transfer type
		shl b32 $r14 1
		or $r1 $r14
		mov $flags $r1
		// transfer context data
		call(ctx_xfer)
		bra #main

	main_not_ctx_xfer:
	shl b32 $r15 $r14 16
	or $r15 E_BAD_COMMAND
	call(error)
	bra #main

// interrupt handler
ih:
	push $r8
	mov $r8 $flags
	push $r8
	push $r9
	push $r10
	push $r11
	push $r13
	push $r14
	push $r15
	clear b32 $r0

	// incoming fifo command?
	nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0)
	and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO
	bra e #ih_no_fifo
		// queue incoming fifo command for later processing
		mov $r13 #cmd_queue
		nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0)
		nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0)
		call(queue_put)
		mov $r14 1
		nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14)

	// ack, and wake up main()
	ih_no_fifo:
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10)

	pop $r15
	pop $r14
	pop $r13
	pop $r11
	pop $r10
	pop $r9
	pop $r8
	mov $flags $r8
	pop $r8
	bclr $flags $p0
	iret

// Set this GPC's bit in HUB_BAR, used to signal completion of various
// activities to the HUB fuc
//
hub_barrier_done:
	mov $r15 1
	ld b32 $r14 D[$r0 + #gpc_id]
	shl b32 $r15 $r14
	nv_wr32(0x409418, $r15)	// 0x409418 - HUB_BAR_SET
	ret

// Disables various things, waits a bit, and re-enables them..
//
// Not sure how exactly this helps, perhaps "ENABLE" is not such a
// good description for the bits we turn off?  Anyways, without this,
// funny things happen.
//
ctx_redswitch:
	mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
	mov $r14 8
	ctx_redswitch_delay:
		sub b32 $r14 1
		bra ne #ctx_redswitch_delay
	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11
	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
	ret

// Transfer GPC context data between GPU and storage area
//
// In: $r15 context base address
//     $p1 clear on save, set on load
//     $p2 set if opposite direction done/will be done, so:
//		on save it means: "a load will follow this save"
//		on load it means: "a save preceeded this load"
//
ctx_xfer:
	// set context base address
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15)
#if CHIPSET >= GM107
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_MEM_BASE, $r15)
#endif
	bra not $p1 #ctx_xfer_not_load
		call(ctx_redswitch)
	ctx_xfer_not_load:

	// strands
	call(strand_pre)
	clear b32 $r2
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2)
	xbit $r2 $flags $p1	// SAVE/LOAD
	add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2)

#if CHIPSET >= GM107
	tpc_strand_enable();
	tpc_strand_seek(0);
	xbit $r15 $flags $p1	// SAVE/LOAD
	add b32 $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SAVE
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)
#endif

	// mmio context
	xbit $r10 $flags $p1	// direction
	or $r10 2		// first
	imm32($r11,0x500000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn
	ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
	ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
	mov $r14 0		// not multi
	call(mmctx_xfer)

	// per-TPC mmio context
	xbit $r10 $flags $p1	// direction
#if !NV_PGRAPH_GPCX_UNK__SIZE
	or $r10 4		// last
#endif
	imm32($r11, 0x504000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_TPC0
	ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
	ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
	ld b32 $r15 D[$r0 + #tpc_mask]
	mov $r14 0x800		// stride = 0x800
	call(mmctx_xfer)

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// per-UNK mmio context
	xbit $r10 $flags $p1	// direction
	or $r10 4		// last
	imm32($r11, 0x503000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_UNK0
	ld b32 $r12 D[$r0 + #unk_mmio_list_head]
	ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
	ld b32 $r15 D[$r0 + #unk_mask]
	mov $r14 0x200		// stride = 0x200
	call(mmctx_xfer)
#endif

	// wait for strands to finish
	call(strand_wait)
#if CHIPSET >= GM107
	tpc_strand_wait()
#endif

	// if load, or a save without a load following, do some
	// unknown stuff that's done after finishing a block of
	// strand commands
	bra $p1 #ctx_xfer_post
	bra not $p2 #ctx_xfer_done
	ctx_xfer_post:
		call(strand_post)
#if CHIPSET >= GM107
		tpc_strand_disable()
#endif

	// mark completion in HUB's barrier
	ctx_xfer_done:
	call(hub_barrier_done)
	ret
#endif
@


1.2.2.1
log
@file gpc.fuc was added on branch pgoyette-compat on 2018-09-06 06:56:26 +0000
@
text
@d1 492
@


1.2.2.2
log
@Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
@
text
@a0 492
/* fuc microcode for gf100 PGRAPH/GPC
 *
 * Copyright 2011 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

/* TODO
 * - bracket certain functions with scratch writes, useful for debugging
 * - watchdog timer around ctx operations
 */

#ifdef INCLUDE_DATA
gpc_mmio_list_head:	.b32 #mmio_list_base
gpc_mmio_list_tail:
tpc_mmio_list_head:	.b32 #mmio_list_base
tpc_mmio_list_tail:
unk_mmio_list_head:	.b32 #mmio_list_base
unk_mmio_list_tail:	.b32 #mmio_list_base

gpc_id:			.b32 0

tpc_count:		.b32 0
tpc_mask:		.b32 0

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
unk_count:		.b32 0
unk_mask:		.b32 0
#endif

cmd_queue:		queue_init

mmio_list_base:
#endif

#ifdef INCLUDE_CODE
#define gpc_addr(reg,addr)                                                    /*
*/	imm32(reg,addr)                                                       /*
*/	or reg NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE
#define gpc_wr32(addr,reg)                                                    /*
*/	gpc_addr($r14,addr)                                                   /*
*/	mov b32 $r15 reg                                                      /*
*/	call(nv_wr32)

// reports an exception to the host
//
// In: $r15 error code (see os.h)
//
error:
	push $r14
	nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15)
	mov $r15 1
	nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15)
	pop $r14
	ret

#if CHIPSET >= GM107
tpc_strand_wait:
	push $r9
	trace_set(T_STRTPC)
	tpc_strand_busy:
		nv_iord($r9, NV_PGRAPH_GPCX_GPCCS_TPC_STATUS, 0)
		bra b32 $r9 0x0 ne #tpc_strand_busy
	trace_clr(T_STRTPC)
	pop $r9
	ret

#define tpc_strand_wait() call(tpc_strand_wait)
#define tpc_strand_enable()                                                   /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_ENABLE                        /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	tpc_strand_wait()
#define tpc_strand_disable()                                                  /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_DISABLE                       /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	tpc_strand_wait()
#define tpc_strand_seek(p)                                                    /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL                         /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)                      /*
*/	mov $r15 p                                                            /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_SELECT, $r15)                     /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SEEK                          /*
*/	tpc_strand_wait()
#define tpc_strand_info(m)                                                    /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	mov $r15 m                                                            /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_DATA, $r15)                       /*
*/	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_GET_INFO                      /*
*/	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)                        /*
*/	tpc_strand_wait()
#endif


// GPC fuc initialisation, executed by triggering ucode start, will
// fall through to main loop after completion.
//
// Input:
//   CC_SCRATCH[1]: context base
//
// Output:
//   CC_SCRATCH[0]:
//	     31:31: set to signal completion
//   CC_SCRATCH[1]:
//	      31:0: GPC context size
//
init:
	clear b32 $r0

	// setup stack
	nv_iord($r1, NV_PGRAPH_GPCX_GPCCS_CAPS, 0)
	extr $r1 $r1 9:17
	shl b32 $r1 8
	mov $sp $r1

	// enable fifo access
	mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2)

	// setup i0 handler, and route all interrupts to it
	mov $r1 #ih
	mov $iv0 $r1
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0)

	// enable fifo interrupt
	mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2)

	// enable interrupts
	bset $flags ie0

	// how many TPCs do we have?
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
	mov $r3 1
	and $r2 0x1f
	shl b32 $r3 $r2
	sub b32 $r3 1
	st b32 D[$r0 + #tpc_count] $r2
	st b32 D[$r0 + #tpc_mask] $r3

	// determine which GPC we are, setup (optional) mmio access offset
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
	st b32 D[$r0 + #gpc_id] $r2
	shl b32 $r2 15
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMIO_BASE, 0, $r2)

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// figure out which, and how many, UNKs are actually present
	gpc_addr($r14, 0x500c30)
	clear b32 $r2
	clear b32 $r3
	clear b32 $r4
	init_unk_loop:
		call(nv_rd32)
		cmp b32 $r15 0
		bra z #init_unk_next
			mov $r15 1
			shl b32 $r15 $r2
			or $r4 $r15
			add b32 $r3 1
		init_unk_next:
		add b32 $r2 1
		add b32 $r14 4
		cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
		bra ne #init_unk_loop
	init_unk_done:
	st b32 D[$r0 + #unk_count] $r3
	st b32 D[$r0 + #unk_mask] $r4
#endif

	// initialise context base, and size tracking
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0)
	clear b32 $r3		// track GPC context size here

	// set mmctx base addresses now so we don't have to do it later,
	// they don't currently ever change
	shr b32 $r5 $r2 8
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5)
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5)

	// calculate GPC mmio context size
	ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
	ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
	call(mmctx_size)
	add b32 $r2 $r15
	add b32 $r3 $r15

	// calculate per-TPC mmio context size
	ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
	ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
	call(mmctx_size)
	ld b32 $r14 D[$r0 + #tpc_count]
	mulu $r14 $r15
	add b32 $r2 $r14
	add b32 $r3 $r14

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// calculate per-UNK mmio context size
	ld b32 $r14 D[$r0 + #unk_mmio_list_head]
	ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
	call(mmctx_size)
	ld b32 $r14 D[$r0 + #unk_count]
	mulu $r14 $r15
	add b32 $r2 $r14
	add b32 $r3 $r14
#endif

	// round up base/size to 256 byte boundary (for strand SWBASE)
	shr b32 $r3 2
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?!
	shr b32 $r2 8
	shr b32 $r3 6
	add b32 $r2 1
	add b32 $r3 1
	shl b32 $r2 8
	shl b32 $r3 8

	// calculate size of strand context data
	mov b32 $r15 $r2
	call(strand_ctx_init)
	add b32 $r2 $r15
	add b32 $r3 $r15

#if CHIPSET >= GM107
	// calculate size of tpc strand context data
	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
	tpc_strand_enable();
	tpc_strand_seek(0);
	tpc_strand_info(-1);

	ld b32 $r4 D[$r0 + #tpc_count]
	mov $r5 NV_PGRAPH_GPC0_TPC0
	ld b32 $r6 D[$r0 + #gpc_id]
	shl b32 $r6 15
	add b32 $r5 $r6
	tpc_strand_init_tpc_loop:
		add b32 $r14 $r5 NV_TPC_STRAND_CNT
		call(nv_rd32)
		mov b32 $r6 $r15
		clear b32 $r7
		tpc_strand_init_idx_loop:
			add b32 $r14 $r5 NV_TPC_STRAND_INDEX
			mov b32 $r15 $r7
			call(nv_wr32)
			add b32 $r14 $r5 NV_TPC_STRAND_SAVE_SWBASE
			shr b32 $r15 $r2 8
			call(nv_wr32)
			add b32 $r14 $r5 NV_TPC_STRAND_LOAD_SWBASE
			shr b32 $r15 $r2 8
			call(nv_wr32)
			add b32 $r14 $r5 NV_TPC_STRAND_WORDS
			call(nv_rd32)
			shr b32 $r15 6
			add b32 $r15 1
			shl b32 $r15 8
			add b32 $r2 $r15
			add b32 $r3 $r15
			add b32 $r7 1
			sub b32 $r6 1
			bra nz #tpc_strand_init_idx_loop
		add b32 $r5 NV_PGRAPH_GPC0_TPC0__SIZE
		sub b32 $r4 1
		bra nz #tpc_strand_init_tpc_loop

	mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
	tpc_strand_disable();
#endif

	// save context size, and tell HUB we're done
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
	clear b32 $r2
	bset $r2 31
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2)

// Main program loop, very simple, sleeps until woken up by the interrupt
// handler, pulls a command from the queue and executes its handler
//
main:
	bset $flags $p0
	sleep $p0
	mov $r13 #cmd_queue
	call(queue_get)
	bra $p1 #main

	// 0x0000-0x0003 are all context transfers
	cmpu b32 $r14 0x04
	bra nc #main_not_ctx_xfer
		// fetch $flags and mask off $p1/$p2
		mov $r1 $flags
		mov $r2 0x0006
		not b32 $r2
		and $r1 $r2
		// set $p1/$p2 according to transfer type
		shl b32 $r14 1
		or $r1 $r14
		mov $flags $r1
		// transfer context data
		call(ctx_xfer)
		bra #main

	main_not_ctx_xfer:
	shl b32 $r15 $r14 16
	or $r15 E_BAD_COMMAND
	call(error)
	bra #main

// interrupt handler
ih:
	push $r8
	mov $r8 $flags
	push $r8
	push $r9
	push $r10
	push $r11
	push $r13
	push $r14
	push $r15
	clear b32 $r0

	// incoming fifo command?
	nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0)
	and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO
	bra e #ih_no_fifo
		// queue incoming fifo command for later processing
		mov $r13 #cmd_queue
		nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0)
		nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0)
		call(queue_put)
		mov $r14 1
		nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14)

	// ack, and wake up main()
	ih_no_fifo:
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10)

	pop $r15
	pop $r14
	pop $r13
	pop $r11
	pop $r10
	pop $r9
	pop $r8
	mov $flags $r8
	pop $r8
	bclr $flags $p0
	iret

// Set this GPC's bit in HUB_BAR, used to signal completion of various
// activities to the HUB fuc
//
hub_barrier_done:
	mov $r15 1
	ld b32 $r14 D[$r0 + #gpc_id]
	shl b32 $r15 $r14
	nv_wr32(0x409418, $r15)	// 0x409418 - HUB_BAR_SET
	ret

// Disables various things, waits a bit, and re-enables them..
//
// Not sure how exactly this helps, perhaps "ENABLE" is not such a
// good description for the bits we turn off?  Anyways, without this,
// funny things happen.
//
ctx_redswitch:
	mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
	mov $r14 8
	ctx_redswitch_delay:
		sub b32 $r14 1
		bra ne #ctx_redswitch_delay
	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11
	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
	ret

// Transfer GPC context data between GPU and storage area
//
// In: $r15 context base address
//     $p1 clear on save, set on load
//     $p2 set if opposite direction done/will be done, so:
//		on save it means: "a load will follow this save"
//		on load it means: "a save preceeded this load"
//
ctx_xfer:
	// set context base address
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15)
#if CHIPSET >= GM107
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_MEM_BASE, $r15)
#endif
	bra not $p1 #ctx_xfer_not_load
		call(ctx_redswitch)
	ctx_xfer_not_load:

	// strands
	call(strand_pre)
	clear b32 $r2
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2)
	xbit $r2 $flags $p1	// SAVE/LOAD
	add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2)

#if CHIPSET >= GM107
	tpc_strand_enable();
	tpc_strand_seek(0);
	xbit $r15 $flags $p1	// SAVE/LOAD
	add b32 $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SAVE
	gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)
#endif

	// mmio context
	xbit $r10 $flags $p1	// direction
	or $r10 2		// first
	imm32($r11,0x500000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn
	ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
	ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
	mov $r14 0		// not multi
	call(mmctx_xfer)

	// per-TPC mmio context
	xbit $r10 $flags $p1	// direction
#if !NV_PGRAPH_GPCX_UNK__SIZE
	or $r10 4		// last
#endif
	imm32($r11, 0x504000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_TPC0
	ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
	ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
	ld b32 $r15 D[$r0 + #tpc_mask]
	mov $r14 0x800		// stride = 0x800
	call(mmctx_xfer)

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// per-UNK mmio context
	xbit $r10 $flags $p1	// direction
	or $r10 4		// last
	imm32($r11, 0x503000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_UNK0
	ld b32 $r12 D[$r0 + #unk_mmio_list_head]
	ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
	ld b32 $r15 D[$r0 + #unk_mask]
	mov $r14 0x200		// stride = 0x200
	call(mmctx_xfer)
#endif

	// wait for strands to finish
	call(strand_wait)
#if CHIPSET >= GM107
	tpc_strand_wait()
#endif

	// if load, or a save without a load following, do some
	// unknown stuff that's done after finishing a block of
	// strand commands
	bra $p1 #ctx_xfer_post
	bra not $p2 #ctx_xfer_done
	ctx_xfer_post:
		call(strand_post)
#if CHIPSET >= GM107
		tpc_strand_disable()
#endif

	// mark completion in HUB's barrier
	ctx_xfer_done:
	call(hub_barrier_done)
	ret
#endif
@


1.1
log
@Initial revision
@
text
@@


1.1.1.1
log
@Import drm from Linux v4.4.143 (commit a8ea6276d00555387deaaa5eaeb380cd5c17bdc9).

   drivers/gpu/drm      -> sys/external/bsd/drm2/dist/drm
   include/drm          -> sys/external/bsd/drm2/dist/include/drm
   include/uapi/drm     -> sys/external/bsd/drm2/dist/uapi/drm

GPL sources excluded.
@
text
@@


1.1.1.2
log
@Import drm from Linux v5.6-rc3 (commit f8788d86ab28f61f7b46eb6be375f8a726783636)

    drivers/gpu/drm     -> sys/external/bsd/drm2/dist/drm
    include/drm         -> sys/external/bsd/drm2/dist/include/drm
    include/uapi/drm    -> sys/external/bsd/drm2/dist/include/uapi/drm

GPL exclusions in dist/drm:

- amd/amdgpu/amdgpu_atpx_handler.c
- arc/
- arm/
- armada/
- aspeed/
- atmel-hlcdc/
- bochs/
- bridge/
- cirrus/
- drm_dp_cec.c
- drm_dp_mst_topology_internal.h
- drm_edid_load.c
- drm_format_helper.c
- drm_gem_cma_helper.c
- drm_gem_framebuffer_helper.c
- drm_gem_shmem_helper.c
- drm_gem_ttm_helper.c
- drm_gem_vram_helper.c
- drm_hdcp.c
- drm_lease.c
- drm_mipi_dbi.c
- drm_simple_kms_helper.c
- drm_sysfs.c
- drm_trace.h
- drm_vram_helper_common.c
- drm_writeback.c
- etnaviv/
- exynos/
- fsl-dcu/
- gma500/
- hisilicon/
- i2c/tda9950.c
- i2c/tda998x_drv.c
- i915/gt/selftest_context.c
- i915/gt/selftest_engine.c
- i915/gt/selftest_engine.h
- i915/gt/selftest_engine_cs.c
- i915/gt/selftest_engine_pm.c
- i915/i915_trace.h
- i915/selftests/i915_live_selftests.h
- i915/selftests/i915_mock_selftests.h
- i915/selftests/i915_perf_selftests.h
- i915/selftests/lib_sw_fence.h
- imx/
- ingenic/
- lima/
- mcde/
- mediatek/
- meson/
- mgag200/
- msm/
- mxsfb/
- omapdrm/
- panel/
- panfrost/
- pl111/
- radeon/radeon_atpx_handler.c
- rcar-du/
- rockchip/
- selftests/drm_cmdline_selftests.h
- selftests/drm_modeset_selftests.h
- selftests/test-drm_cmdline_parser.c
- selftests/test-drm_damage_helper.c
- selftests/test-drm_dp_mst_helper.c
- selftests/test-drm_format.c
- selftests/test-drm_framebuffer.c
- selftests/test-drm_modeset_common.c
- selftests/test-drm_modeset_common.h
- selftests/test-drm_plane_helper.c
- selftests/test-drm_rect.c
- shmobile/
- sti/
- stm/
- sun4i/
- tegra/
- tilcdc/
- tiny/
- tve200/
- udl/
- v3d/
- vc4/
- virtio/virtgpu_trace.h
- virtio/virtgpu_trace_points.c
- vkms/
- vmwgfx/device_include/vmware_pack_begin.h
- vmwgfx/device_include/vmware_pack_end.h
- zte/

  Exceptions -- these all appear to be files to which someone added
  an SPDX license header automatically by a script that is not aware
  of the default MIT licensing under drivers/gpu/drm:

  - ast/ast_dp501.c
  - ast/ast_dram_tables.h
  - lib/drm_random.c
  - lib/drm_random.h
  - i915/display/intel_acpi.c
  - i915/selftests/mock_gem_device.h
  - i915/selftests/i915_mock_selftests.h
  - i915/selftests/i915_live_selftests.h
  - r128/ati_pcigart.h
  - selftests/drm_mm_selftests.h
  - selftests/test-drm_mm.c
  - vmwgfx/device_include/vm_basic_types.h

GPL exclusions in dist/include/drm:

- bridge
- drm_client.h
- drm_fb_cma_helper.h
- drm_format_helper.h
- drm_gem_cma_helper.h
- drm_gem_shmem_helper.h
- drm_gem_ttm_helper.h
- drm_gem_vram_helper.h
- drm_lease.h
- drm_mipi_dbi.h
- drm_mipi_dsi.h
- drm_of.h
- drm_simple_kms_helper.h
- drm_sysfs.h
- drm_writeback.h
- gma_drm.h
- i2c/tda998x.h
- i915_mei_hdcp_interface.h
- intel-gtt.h

  Exceptions:
  - drm_agpsupport.h - was in original drm; wrong spdx header auto-added

GPL exclusions in dist/include/uapi/drm:

- armada_drm.h
- etnaviv_drm.h
- exynos_drm.h
- lima_drm.h
- omap_drm.h

  Exceptions:
  - i810_drm.h - was in original drm; spdx header is wrong
@
text
@d250 4
a253 1
	gpc_addr($r5, NV_PGRAPH_GPC0_TPC0)
d297 2
a298 1
wait:
a299 2
	bset $flags $p0
main:
d302 1
a302 1
	bra $p1 #wait
a327 1
	push $r0
a363 1
	pop $r0
@