head	1.18;
access;
symbols
	netbsd-11-0-RC4:1.17.2.1
	netbsd-11-0-RC3:1.17.2.1
	netbsd-11-0-RC2:1.17
	netbsd-11-0-RC1:1.17
	perseant-exfatfs-base-20250801:1.17
	netbsd-11:1.17.0.2
	netbsd-11-base:1.17
	netbsd-10-1-RELEASE:1.11
	perseant-exfatfs-base-20240630:1.15
	perseant-exfatfs:1.15.0.2
	perseant-exfatfs-base:1.15
	netbsd-8-3-RELEASE:1.1
	netbsd-9-4-RELEASE:1.3
	netbsd-10-0-RELEASE:1.11
	netbsd-10-0-RC6:1.11
	netbsd-10-0-RC5:1.11
	netbsd-10-0-RC4:1.11
	netbsd-10-0-RC3:1.11
	netbsd-10-0-RC2:1.11
	thorpej-ifq:1.14.0.4
	thorpej-ifq-base:1.14
	thorpej-altq-separation:1.14.0.2
	thorpej-altq-separation-base:1.14
	netbsd-10-0-RC1:1.11
	netbsd-10:1.11.0.2
	netbsd-10-base:1.11
	bouyer-sunxi-drm:1.10.0.2
	bouyer-sunxi-drm-base:1.10
	netbsd-9-3-RELEASE:1.3
	thorpej-i2c-spi-conf2:1.7.0.14
	thorpej-i2c-spi-conf2-base:1.7
	thorpej-futex2:1.7.0.12
	thorpej-futex2-base:1.7
	thorpej-cfargs2:1.7.0.10
	thorpej-cfargs2-base:1.7
	cjep_sun2x-base1:1.7
	cjep_sun2x:1.7.0.8
	cjep_sun2x-base:1.7
	cjep_staticlib_x-base1:1.7
	netbsd-9-2-RELEASE:1.3
	cjep_staticlib_x:1.7.0.6
	cjep_staticlib_x-base:1.7
	thorpej-i2c-spi-conf:1.7.0.4
	thorpej-i2c-spi-conf-base:1.7
	thorpej-cfargs:1.7.0.2
	thorpej-cfargs-base:1.7
	thorpej-futex:1.6.0.2
	thorpej-futex-base:1.7
	netbsd-9-1-RELEASE:1.3
	bouyer-xenpvh-base2:1.4
	phil-wifi-20200421:1.4
	bouyer-xenpvh-base1:1.4
	phil-wifi-20200411:1.4
	bouyer-xenpvh:1.4.0.6
	bouyer-xenpvh-base:1.4
	is-mlppp:1.4.0.4
	is-mlppp-base:1.4
	phil-wifi-20200406:1.4
	netbsd-8-2-RELEASE:1.1
	ad-namecache-base3:1.4
	netbsd-9-0-RELEASE:1.3
	netbsd-9-0-RC2:1.3
	ad-namecache-base2:1.4
	ad-namecache-base1:1.4
	ad-namecache:1.4.0.2
	ad-namecache-base:1.4
	netbsd-9-0-RC1:1.3
	phil-wifi-20191119:1.3
	netbsd-9:1.3.0.2
	netbsd-9-base:1.3
	phil-wifi-20190609:1.2
	netbsd-8-1-RELEASE:1.1
	netbsd-8-1-RC1:1.1
	isaki-audio2:1.1.0.24
	isaki-audio2-base:1.1
	pgoyette-compat-merge-20190127:1.1
	pgoyette-compat-20190127:1.1
	pgoyette-compat-20190118:1.1
	pgoyette-compat-1226:1.1
	pgoyette-compat-1126:1.1
	pgoyette-compat-1020:1.1
	pgoyette-compat-0930:1.1
	pgoyette-compat-0906:1.1
	pgoyette-compat-0728:1.1
	netbsd-8-0-RELEASE:1.1
	phil-wifi:1.1.0.22
	phil-wifi-base:1.1
	pgoyette-compat-0625:1.1
	netbsd-8-0-RC2:1.1
	pgoyette-compat-0521:1.1
	pgoyette-compat-0502:1.1
	pgoyette-compat-0422:1.1
	netbsd-8-0-RC1:1.1
	pgoyette-compat-0415:1.1
	pgoyette-compat-0407:1.1
	pgoyette-compat-0330:1.1
	pgoyette-compat-0322:1.1
	pgoyette-compat-0315:1.1
	pgoyette-compat:1.1.0.20
	pgoyette-compat-base:1.1
	tls-maxphys:1.1.0.18
	tls-maxphys-base-20171202:1.1
	matt-nb8-mediatek:1.1.0.16
	matt-nb8-mediatek-base:1.1
	nick-nhusb-base-20170825:1.1
	perseant-stdc-iso10646:1.1.0.14
	perseant-stdc-iso10646-base:1.1
	netbsd-8:1.1.0.12
	netbsd-8-base:1.1
	prg-localcount2-base3:1.1
	prg-localcount2-base2:1.1
	prg-localcount2-base1:1.1
	prg-localcount2:1.1.0.10
	prg-localcount2-base:1.1
	pgoyette-localcount-20170426:1.1
	bouyer-socketcan-base1:1.1
	jdolecek-ncq:1.1.0.8
	jdolecek-ncq-base:1.1
	pgoyette-localcount-20170320:1.1
	nick-nhusb-base-20170204:1.1
	bouyer-socketcan:1.1.0.6
	bouyer-socketcan-base:1.1
	pgoyette-localcount-20170107:1.1
	nick-nhusb-base-20161204:1.1
	pgoyette-localcount-20161104:1.1
	nick-nhusb-base-20161004:1.1
	localcount-20160914:1.1
	pgoyette-localcount-20160806:1.1
	pgoyette-localcount-20160726:1.1
	pgoyette-localcount:1.1.0.4
	pgoyette-localcount-base:1.1
	nick-nhusb-base-20160907:1.1
	nick-nhusb-base-20160529:1.1
	nick-nhusb-base-20160422:1.1
	nick-nhusb-base-20160319:1.1
	nick-nhusb-base-20151226:1.1
	nick-nhusb-base-20150921:1.1
	nick-nhusb-base-20150606:1.1
	nick-nhusb:1.1.0.2
	nick-nhusb-base-20150406:1.1;
locks; strict;
comment	@# @;


1.18
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desc
@@


1.18
log
@risc-v: handle T-Head L1 caches

Provide and use hooks for L1 cache operations on the T-Head processors.

Re-worked from diffs provided by Rui-Xiang Guo via port-riscv.
@
text
@#	$NetBSD: files.riscv,v 1.17 2025/01/01 17:53:07 skrll Exp $
#

maxpartitions	16
maxusers	8 32 64

# Console options
defparam opt_console.h		CONSADDR

# RISC-V specific debug options
defflag  opt_riscv_debug.h	VERBOSE_INIT_RISCV

defflag	opt_ddb.h		DDB_TRACE

device	mainbus {}: fdt
attach	mainbus at root
file	arch/riscv/riscv/mainbus.c		mainbus

device cpu {}: fdt

file	arch/riscv/riscv/autoconf.c
file	arch/riscv/riscv/bus_dma.c
file	arch/riscv/riscv/bus_space.c
file	arch/riscv/riscv/bus_space_generic.S
file	arch/riscv/riscv/bus_space_notimpl.S
file	arch/riscv/riscv/bus_stubs.c
file	arch/riscv/riscv/clock_machdep.c
file	arch/riscv/riscv/copy.S
file	arch/riscv/riscv/core_machdep.c		coredump
file	arch/riscv/riscv/cpu.c			cpu
file	arch/riscv/riscv/cpufunc.c
file	arch/riscv/riscv/cpu_subr.c
file	arch/riscv/riscv/cpu_switch.S
file	arch/riscv/riscv/db_interface.c		ddb
file	arch/riscv/riscv/db_disasm.c		ddb
file	arch/riscv/riscv/db_machdep.c		ddb | kgdb
file	arch/riscv/riscv/db_memrw.c		ddb | kgdb
file	arch/riscv/riscv/db_trace.c		ddb
file	arch/riscv/riscv/exec_machdep.c
file	arch/riscv/riscv/fixup.c
file	arch/riscv/riscv/fpu.c			fpe
file	arch/riscv/riscv/ipifuncs.c		multiprocessor
file	arch/riscv/riscv/interrupt.c
file	arch/riscv/riscv/kgdb_machdep.c		kgdb
file	arch/riscv/riscv/kobj_machdep.c		modular
file	arch/riscv/riscv/pmap_machdep.c
file	arch/riscv/riscv/process_machdep.c
file	arch/riscv/riscv/procfs_machdep.c	procfs
file	arch/riscv/riscv/riscv_tlb.c
file	arch/riscv/riscv/riscv_generic_dma.c
file	arch/riscv/riscv/riscv_machdep.c
file	arch/riscv/riscv/sbi.c			# SBI
file	arch/riscv/riscv/sig_machdep.c		# signal delivery
file	arch/riscv/riscv/softint_machdep.c
file	arch/riscv/riscv/spl.S
file	arch/riscv/riscv/stubs.c
file	arch/riscv/riscv/syscall.c		# syscall handler
file	arch/riscv/riscv/sys_machdep.c
file	arch/riscv/riscv/trap.c			# trap handlers
file	arch/riscv/riscv/vm_machdep.c

file	dev/cons.c
file	dev/md_root.c				memory_disk_hooks

file	kern/subr_disk_mbr.c			disk

file	uvm/pmap/pmap.c
file	uvm/pmap/pmap_devmap.c
file	uvm/pmap/pmap_segtab.c
file	uvm/pmap/pmap_tlb.c

device  plic
file	arch/riscv/dev/plic.c			plic
attach  plic at fdt with plic_fdt
file	arch/riscv/dev/plic_fdt.c		plic & fdt

#
# Binary compatibility with 32bit NetBSD (COMPAT_NETBSD32)
#
file	arch/riscv/riscv/core32_machdep.c	compat_netbsd32 & coredump
file	arch/riscv/riscv/netbsd32_machdep.c	compat_netbsd32
file	arch/riscv/riscv/sig32_machdep.c	compat_netbsd32
include "compat/netbsd32/files.netbsd32"

include "arch/riscv/fdt/files.fdt"

#
# Machine-independent drivers
#
include "dev/ata/files.ata"			# ATA drivers
include "dev/bluetooth/files.bluetooth"		# Bluetooth devices
include "dev/i2o/files.i2o"			# I2O drivers.
include "dev/sdmmc/files.sdmmc"			# SD/MMC devices
include "dev/scsipi/files.scsipi"
include "dev/usb/files.usb"			# USB device support
include "dev/pci/files.pci"			# PCI device support

#
# Machine-dependent drivers
#
include "arch/riscv/conf/majors.riscv"
@


1.17
log
@risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.16 2024/11/23 12:03:55 skrll Exp $
d31 1
@


1.17.2.1
log
@Pull up following revision(s) (requested by skrll in ticket #221):

	sys/arch/riscv/riscv/cpufunc.c: revision 1.1
	sys/arch/riscv/riscv/cpufunc.c: revision 1.2
	sys/arch/riscv/conf/files.riscv: revision 1.18
	sys/arch/riscv/include/pmap.h: revision 1.26
	sys/arch/riscv/include/cpufunc.h: revision 1.2
	sys/arch/riscv/riscv/pmap_machdep.c: revision 1.24
	sys/arch/riscv/riscv/cpu.c: revision 1.11
	sys/arch/riscv/riscv/riscv_machdep.c: revision 1.48

risc-v: handle T-Head L1 caches

Provide and use hooks for L1 cache operations on the T-Head processors.
Re-worked from diffs provided by Rui-Xiang Guo via port-riscv.

Fix primary cache function prototypes to fix build on rv32
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.17 2025/01/01 17:53:07 skrll Exp $
a30 1
file	arch/riscv/riscv/cpufunc.c
@


1.16
log
@risc-v: split db_{read,write}_bytes from db_machdep.c

Another step towards crash(8) support
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.15 2024/04/06 10:08:54 skrll Exp $
d76 1
d78 1
d86 1
d88 1
d97 3
@


1.15
log
@Provide and use _ucas_{32,64} implementations
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.14 2023/09/03 08:48:19 skrll Exp $
d36 1
@


1.15.2.1
log
@Sync with HEAD
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.17 2025/01/01 17:53:07 skrll Exp $
a35 1
file	arch/riscv/riscv/db_memrw.c		ddb | kgdb
a74 1
#
a75 1
#
a82 1
#
a83 1
#
a91 3
#
# Machine-dependent drivers
#
@


1.14
log
@Fix and enable MULTIPROCESSOR
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.13 2023/06/12 19:04:13 skrll Exp $
d28 1
@


1.13
log
@risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.12 2023/05/07 12:41:48 skrll Exp $
a66 1
file	uvm/pmap/pmap_synci.c
@


1.12
log
@RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.11 2022/10/14 07:58:30 skrll Exp $
d46 1
d67 1
@


1.11
log
@Split out a bunch of functions from locore.S into cpu_switch.S

NFC
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.10 2022/09/27 08:18:21 skrll Exp $
d15 5
a19 1
file	arch/riscv/fdt/fdt_dma_machdep.c
d22 1
d26 1
d29 1
d40 1
d46 1
d48 1
d64 1
d68 5
d79 1
a79 2
device	mainbus {}: fdt
attach	mainbus at root
d81 5
a85 6
file	arch/riscv/riscv/mainbus.c		mainbus

# Machine-independent I2O drivers.
include "dev/i2o/files.i2o"

# Machine-independent SCSI drivers
d87 2
a88 9

# Machine-independent ATA drivers
include "dev/ata/files.ata"

# Machine-independent USB device support
include "dev/usb/files.usb"

# Machine-independent PCI device support
#include "dev/pci/files.pci"
@


1.10
log
@Basic ddb and backtrace support.

[   1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[   1.0000000] cpu0: Begin traceback...
[   1.0000000] trace fp ffffffc000801dd0
[   1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[   1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[   1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[   1.0000000] cpu0: End traceback...
[   1.0000000] Trapframe @@ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[   1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp =                 0
[   1.0000000] s0 =0xffffffc000600ac0, s1 =            0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[   1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[   1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[   1.0000000] a0 =              0x17, a1 =               0xa, a2 =                 0, a3 =0xffffffc00041f658
[   1.0000000] a4 =                 0, a5 =               0x1, a5 =                 0, a7 =               0x1
[   1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 =              0x75
[   1.0000000] t4 =                 0, t5 =              0x63, t6 =               0x1
[   1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at  ffffffc0000007e4:       c.ebreak
db>
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.9 2022/09/19 09:15:01 skrll Exp $
d24 1
@


1.9
log
@Sort. NFC.
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.8 2022/09/11 15:31:11 skrll Exp $
d24 1
@


1.8
log
@Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.7 2020/11/04 06:56:56 skrll Exp $
d17 1
a17 2
file	arch/riscv/riscv/spl.S

d21 2
a22 2

file	arch/riscv/riscv/autoconf.c
d25 1
d27 1
a30 8
file	arch/riscv/riscv/stubs.c
file	arch/riscv/riscv/syscall.c		# syscall handler
file	arch/riscv/riscv/trap.c			# trap handlers

file	arch/riscv/riscv/core_machdep.c		coredump
file	arch/riscv/riscv/clock_machdep.c
file	arch/riscv/riscv/db_machdep.c		ddb | kgdb
file	arch/riscv/riscv/exec_machdep.c
d39 3
d43 1
@


1.7
log
@Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@@
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.6 2020/10/21 13:31:51 christos Exp $
d7 6
d15 2
a16 1
#file	arch/riscv/riscv/locore.S
d19 4
d64 1
a64 1
device	mainbus { [instance=-1] }
d66 1
d69 14
a82 16
device	cpu
attach	cpu at mainbus with cpu_mainbus
file	arch/riscv/riscv/cpu_mainbus.c		cpu_mainbus

device	htif { }
attach	htif at mainbus with htif_mainbus
file	arch/riscv/htif/htif.c			htif_mainbus

device	htifcons { } : tty
attach	htifcons at htif with htif_cons
file	arch/riscv/htif/htif_cons.c		htif_cons

device	htifdisk { } : disk
attach	htifdisk at htif with htif_disk
attach	ld at htifdisk with ld_htifdisk
file	arch/riscv/htif/htif_disk.c		htif_disk
@


1.6
log
@make process_machdep.c included always since it provides register i/o used by
sys_process_getlwpstatus.c which is always included.
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.5 2020/10/20 20:36:08 christos Exp $
d17 1
a17 1
file	arch/riscv/riscv/fpu.c
@


1.6.2.1
log
@Sync w/ HEAD.
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.7 2020/11/04 06:56:56 skrll Exp $
d17 1
a17 1
file	arch/riscv/riscv/fpu.c			fpe
@


1.5
log
@harmonize process_machdep.c inclusion.
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.4 2019/11/20 19:37:52 pgoyette Exp $
d30 1
a30 1
file	arch/riscv/riscv/process_machdep.c		ptrace | coredump | procfs
@


1.4
log
@Move all non-emulation-specific coredump code into the coredump module,
and remove all #ifdef COREDUMP conditional compilation.  Now, the
coredump module is completely separated from the emulation modules, and
they can all be independently loaded and unloaded.

Welcome to 9.99.18 !
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.3 2019/06/16 07:42:52 maxv Exp $
d30 1
a30 1
file	arch/riscv/riscv/process_machdep.c
@


1.3
log
@Misc changes in RISC-V.
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.2 2019/06/01 12:42:27 maxv Exp $
d24 1
a24 1
file	arch/riscv/riscv/clock_machdep.c	coredump
@


1.2
log
@Misc changes in RISC-V. Start changing the memory layout, too.
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.1 2015/03/28 16:13:56 matt Exp $
a43 1
file	uvm/pmap/pmap_pvt.c
@


1.1
log
@Beginnings of RISCV kernel support.  Note that the pmap support is not yet
committed and probably won't be for awhile.  This is mostly preliminary
waiting for the supervisor specification to come out.  Lots of missing pieces
but it mostly builds.
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.72 2011/08/16 06:58:15 matt Exp $
d44 1
a44 1
file	uvm/pmap/pmap_pv.c
a53 7
# Linux compatibility (COMPAT_LINUX)	XXX Highly experimental
#include "compat/ossaudio/files.ossaudio"
#include "compat/linux/files.linux"
#include "compat/linux/arch/riscv/files.linux_riscv"
#file	arch/riscv/riscv/linux_trap.c		compat_linux
#file	arch/riscv/riscv/linux_syscall.c	compat_linux

@


1.1.22.1
log
@Sync with HEAD
@
text
@d1 1
a1 1
#	$NetBSD: files.riscv,v 1.2 2019/06/01 12:42:27 maxv Exp $
d44 1
a44 1
file	uvm/pmap/pmap_pvt.c
d54 7
@


1.1.22.2
log
@Merge changes from current as of 20200406
@
text
@d1 1
a1 1
#	$NetBSD$
d24 1
a24 1
file	arch/riscv/riscv/clock_machdep.c
@


1.1.22.3
log
@Mostly merge changes from HEAD upto 20200411
@
text
@d44 1
@


1.1.18.1
log
@file files.riscv was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
@
text
@d1 82
@


1.1.18.2
log
@update from HEAD
@
text
@a0 82
#	$NetBSD$
#

maxpartitions	16
maxusers	8 32 64

defflag	opt_ddb.h		DDB_TRACE

#file	arch/riscv/riscv/locore.S
file	arch/riscv/riscv/spl.S

file	arch/riscv/riscv/autoconf.c
file	arch/riscv/riscv/cpu_subr.c
file	arch/riscv/riscv/db_disasm.c		ddb
file	arch/riscv/riscv/db_trace.c		ddb
file	arch/riscv/riscv/fixup.c
file	arch/riscv/riscv/fpu.c
file	arch/riscv/riscv/ipifuncs.c		multiprocessor
file	arch/riscv/riscv/stubs.c
file	arch/riscv/riscv/syscall.c		# syscall handler
file	arch/riscv/riscv/trap.c			# trap handlers

file	arch/riscv/riscv/core_machdep.c		coredump
file	arch/riscv/riscv/clock_machdep.c	coredump
file	arch/riscv/riscv/db_machdep.c		ddb | kgdb
file	arch/riscv/riscv/exec_machdep.c
file	arch/riscv/riscv/kgdb_machdep.c		kgdb
file	arch/riscv/riscv/kobj_machdep.c		modular
file	arch/riscv/riscv/pmap_machdep.c
file	arch/riscv/riscv/process_machdep.c
file	arch/riscv/riscv/procfs_machdep.c	procfs
file	arch/riscv/riscv/riscv_machdep.c
file	arch/riscv/riscv/sig_machdep.c		# signal delivery
file	arch/riscv/riscv/softint_machdep.c
file	arch/riscv/riscv/sys_machdep.c
file	arch/riscv/riscv/vm_machdep.c

file	dev/cons.c
file	dev/md_root.c				memory_disk_hooks

file	kern/subr_disk_mbr.c			disk

file	uvm/pmap/pmap.c
file	uvm/pmap/pmap_pv.c
file	uvm/pmap/pmap_segtab.c
file	uvm/pmap/pmap_tlb.c

# Binary compatibility with 32bit NetBSD (COMPAT_NETBSD32)
file	arch/riscv/riscv/core32_machdep.c	compat_netbsd32 & coredump
file	arch/riscv/riscv/netbsd32_machdep.c	compat_netbsd32
file	arch/riscv/riscv/sig32_machdep.c	compat_netbsd32
include "compat/netbsd32/files.netbsd32"

# Linux compatibility (COMPAT_LINUX)	XXX Highly experimental
#include "compat/ossaudio/files.ossaudio"
#include "compat/linux/files.linux"
#include "compat/linux/arch/riscv/files.linux_riscv"
#file	arch/riscv/riscv/linux_trap.c		compat_linux
#file	arch/riscv/riscv/linux_syscall.c	compat_linux

device	mainbus { [instance=-1] }
attach	mainbus at root
file	arch/riscv/riscv/mainbus.c		mainbus

device	cpu
attach	cpu at mainbus with cpu_mainbus
file	arch/riscv/riscv/cpu_mainbus.c		cpu_mainbus

device	htif { }
attach	htif at mainbus with htif_mainbus
file	arch/riscv/htif/htif.c			htif_mainbus

device	htifcons { } : tty
attach	htifcons at htif with htif_cons
file	arch/riscv/htif/htif_cons.c		htif_cons

device	htifdisk { } : disk
attach	htifdisk at htif with htif_disk
attach	ld at htifdisk with ld_htifdisk
file	arch/riscv/htif/htif_disk.c		htif_disk

include "arch/riscv/conf/majors.riscv"
@


1.1.2.1
log
@file files.riscv was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
@
text
@d1 82
@


1.1.2.2
log
@Sync with HEAD
@
text
@a0 82
#	$NetBSD: files.riscv,v 1.1 2015/03/28 16:13:56 matt Exp $
#

maxpartitions	16
maxusers	8 32 64

defflag	opt_ddb.h		DDB_TRACE

#file	arch/riscv/riscv/locore.S
file	arch/riscv/riscv/spl.S

file	arch/riscv/riscv/autoconf.c
file	arch/riscv/riscv/cpu_subr.c
file	arch/riscv/riscv/db_disasm.c		ddb
file	arch/riscv/riscv/db_trace.c		ddb
file	arch/riscv/riscv/fixup.c
file	arch/riscv/riscv/fpu.c
file	arch/riscv/riscv/ipifuncs.c		multiprocessor
file	arch/riscv/riscv/stubs.c
file	arch/riscv/riscv/syscall.c		# syscall handler
file	arch/riscv/riscv/trap.c			# trap handlers

file	arch/riscv/riscv/core_machdep.c		coredump
file	arch/riscv/riscv/clock_machdep.c	coredump
file	arch/riscv/riscv/db_machdep.c		ddb | kgdb
file	arch/riscv/riscv/exec_machdep.c
file	arch/riscv/riscv/kgdb_machdep.c		kgdb
file	arch/riscv/riscv/kobj_machdep.c		modular
file	arch/riscv/riscv/pmap_machdep.c
file	arch/riscv/riscv/process_machdep.c
file	arch/riscv/riscv/procfs_machdep.c	procfs
file	arch/riscv/riscv/riscv_machdep.c
file	arch/riscv/riscv/sig_machdep.c		# signal delivery
file	arch/riscv/riscv/softint_machdep.c
file	arch/riscv/riscv/sys_machdep.c
file	arch/riscv/riscv/vm_machdep.c

file	dev/cons.c
file	dev/md_root.c				memory_disk_hooks

file	kern/subr_disk_mbr.c			disk

file	uvm/pmap/pmap.c
file	uvm/pmap/pmap_pv.c
file	uvm/pmap/pmap_segtab.c
file	uvm/pmap/pmap_tlb.c

# Binary compatibility with 32bit NetBSD (COMPAT_NETBSD32)
file	arch/riscv/riscv/core32_machdep.c	compat_netbsd32 & coredump
file	arch/riscv/riscv/netbsd32_machdep.c	compat_netbsd32
file	arch/riscv/riscv/sig32_machdep.c	compat_netbsd32
include "compat/netbsd32/files.netbsd32"

# Linux compatibility (COMPAT_LINUX)	XXX Highly experimental
#include "compat/ossaudio/files.ossaudio"
#include "compat/linux/files.linux"
#include "compat/linux/arch/riscv/files.linux_riscv"
#file	arch/riscv/riscv/linux_trap.c		compat_linux
#file	arch/riscv/riscv/linux_syscall.c	compat_linux

device	mainbus { [instance=-1] }
attach	mainbus at root
file	arch/riscv/riscv/mainbus.c		mainbus

device	cpu
attach	cpu at mainbus with cpu_mainbus
file	arch/riscv/riscv/cpu_mainbus.c		cpu_mainbus

device	htif { }
attach	htif at mainbus with htif_mainbus
file	arch/riscv/htif/htif.c			htif_mainbus

device	htifcons { } : tty
attach	htifcons at htif with htif_cons
file	arch/riscv/htif/htif_cons.c		htif_cons

device	htifdisk { } : disk
attach	htifdisk at htif with htif_disk
attach	ld at htifdisk with ld_htifdisk
file	arch/riscv/htif/htif_disk.c		htif_disk

include "arch/riscv/conf/majors.riscv"
@