head 1.15; access; symbols netbsd-11-0-RC4:1.15 netbsd-11-0-RC3:1.15 netbsd-11-0-RC2:1.15 netbsd-11-0-RC1:1.15 perseant-exfatfs-base-20250801:1.15 netbsd-11:1.15.0.126 netbsd-11-base:1.15 netbsd-10-1-RELEASE:1.15 perseant-exfatfs-base-20240630:1.15 perseant-exfatfs:1.15.0.124 perseant-exfatfs-base:1.15 netbsd-8-3-RELEASE:1.15 netbsd-9-4-RELEASE:1.15 netbsd-10-0-RELEASE:1.15 netbsd-10-0-RC6:1.15 netbsd-10-0-RC5:1.15 netbsd-10-0-RC4:1.15 netbsd-10-0-RC3:1.15 netbsd-10-0-RC2:1.15 thorpej-ifq:1.15.0.122 thorpej-ifq-base:1.15 thorpej-altq-separation:1.15.0.120 thorpej-altq-separation-base:1.15 netbsd-10-0-RC1:1.15 netbsd-10:1.15.0.118 netbsd-10-base:1.15 bouyer-sunxi-drm:1.15.0.116 bouyer-sunxi-drm-base:1.15 netbsd-9-3-RELEASE:1.15 thorpej-i2c-spi-conf2:1.15.0.114 thorpej-i2c-spi-conf2-base:1.15 thorpej-futex2:1.15.0.112 thorpej-futex2-base:1.15 thorpej-cfargs2:1.15.0.110 thorpej-cfargs2-base:1.15 cjep_sun2x-base1:1.15 cjep_sun2x:1.15.0.108 cjep_sun2x-base:1.15 cjep_staticlib_x-base1:1.15 netbsd-9-2-RELEASE:1.15 cjep_staticlib_x:1.15.0.106 cjep_staticlib_x-base:1.15 thorpej-i2c-spi-conf:1.15.0.104 thorpej-i2c-spi-conf-base:1.15 thorpej-cfargs:1.15.0.102 thorpej-cfargs-base:1.15 thorpej-futex:1.15.0.100 thorpej-futex-base:1.15 netbsd-9-1-RELEASE:1.15 bouyer-xenpvh-base2:1.15 phil-wifi-20200421:1.15 bouyer-xenpvh-base1:1.15 phil-wifi-20200411:1.15 bouyer-xenpvh:1.15.0.98 bouyer-xenpvh-base:1.15 is-mlppp:1.15.0.96 is-mlppp-base:1.15 phil-wifi-20200406:1.15 netbsd-8-2-RELEASE:1.15 ad-namecache-base3:1.15 netbsd-9-0-RELEASE:1.15 netbsd-9-0-RC2:1.15 ad-namecache-base2:1.15 ad-namecache-base1:1.15 ad-namecache:1.15.0.94 ad-namecache-base:1.15 netbsd-9-0-RC1:1.15 phil-wifi-20191119:1.15 netbsd-9:1.15.0.92 netbsd-9-base:1.15 phil-wifi-20190609:1.15 netbsd-8-1-RELEASE:1.15 netbsd-8-1-RC1:1.15 isaki-audio2:1.15.0.90 isaki-audio2-base:1.15 pgoyette-compat-merge-20190127:1.15 pgoyette-compat-20190127:1.15 pgoyette-compat-20190118:1.15 pgoyette-compat-1226:1.15 pgoyette-compat-1126:1.15 pgoyette-compat-1020:1.15 pgoyette-compat-0930:1.15 pgoyette-compat-0906:1.15 netbsd-7-2-RELEASE:1.15 pgoyette-compat-0728:1.15 netbsd-8-0-RELEASE:1.15 phil-wifi:1.15.0.88 phil-wifi-base:1.15 pgoyette-compat-0625:1.15 netbsd-8-0-RC2:1.15 pgoyette-compat-0521:1.15 pgoyette-compat-0502:1.15 pgoyette-compat-0422:1.15 netbsd-8-0-RC1:1.15 pgoyette-compat-0415:1.15 pgoyette-compat-0407:1.15 pgoyette-compat-0330:1.15 pgoyette-compat-0322:1.15 pgoyette-compat-0315:1.15 netbsd-7-1-2-RELEASE:1.15 pgoyette-compat:1.15.0.86 pgoyette-compat-base:1.15 netbsd-7-1-1-RELEASE:1.15 tls-maxphys-base-20171202:1.15 matt-nb8-mediatek:1.15.0.84 matt-nb8-mediatek-base:1.15 nick-nhusb-base-20170825:1.15 perseant-stdc-iso10646:1.15.0.82 perseant-stdc-iso10646-base:1.15 netbsd-8:1.15.0.80 netbsd-8-base:1.15 prg-localcount2-base3:1.15 prg-localcount2-base2:1.15 prg-localcount2-base1:1.15 prg-localcount2:1.15.0.78 prg-localcount2-base:1.15 pgoyette-localcount-20170426:1.15 bouyer-socketcan-base1:1.15 jdolecek-ncq:1.15.0.76 jdolecek-ncq-base:1.15 pgoyette-localcount-20170320:1.15 netbsd-7-1:1.15.0.74 netbsd-7-1-RELEASE:1.15 netbsd-7-1-RC2:1.15 nick-nhusb-base-20170204:1.15 netbsd-7-nhusb-base-20170116:1.15 bouyer-socketcan:1.15.0.72 bouyer-socketcan-base:1.15 pgoyette-localcount-20170107:1.15 netbsd-7-1-RC1:1.15 nick-nhusb-base-20161204:1.15 pgoyette-localcount-20161104:1.15 netbsd-7-0-2-RELEASE:1.15 nick-nhusb-base-20161004:1.15 localcount-20160914:1.15 netbsd-7-nhusb:1.15.0.70 netbsd-7-nhusb-base:1.15 pgoyette-localcount-20160806:1.15 pgoyette-localcount-20160726:1.15 pgoyette-localcount:1.15.0.68 pgoyette-localcount-base:1.15 nick-nhusb-base-20160907:1.15 nick-nhusb-base-20160529:1.15 netbsd-7-0-1-RELEASE:1.15 nick-nhusb-base-20160422:1.15 nick-nhusb-base-20160319:1.15 nick-nhusb-base-20151226:1.15 netbsd-7-0:1.15.0.66 netbsd-7-0-RELEASE:1.15 nick-nhusb-base-20150921:1.15 netbsd-7-0-RC3:1.15 netbsd-7-0-RC2:1.15 netbsd-7-0-RC1:1.15 nick-nhusb-base-20150606:1.15 nick-nhusb-base-20150406:1.15 nick-nhusb:1.15.0.64 nick-nhusb-base:1.15 netbsd-5-2-3-RELEASE:1.15 netbsd-5-1-5-RELEASE:1.15 netbsd-6-0-6-RELEASE:1.15 netbsd-6-1-5-RELEASE:1.15 netbsd-7:1.15.0.62 netbsd-7-base:1.15 yamt-pagecache-base9:1.15 yamt-pagecache-tag8:1.15 netbsd-6-1-4-RELEASE:1.15 netbsd-6-0-5-RELEASE:1.15 tls-earlyentropy:1.15.0.60 tls-earlyentropy-base:1.15 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.15 riastradh-drm2-base3:1.15 netbsd-6-1-3-RELEASE:1.15 netbsd-6-0-4-RELEASE:1.15 netbsd-5-2-2-RELEASE:1.15 netbsd-5-1-4-RELEASE:1.15 netbsd-6-1-2-RELEASE:1.15 netbsd-6-0-3-RELEASE:1.15 netbsd-5-2-1-RELEASE:1.15 netbsd-5-1-3-RELEASE:1.15 rmind-smpnet-nbase:1.15 netbsd-6-1-1-RELEASE:1.15 riastradh-drm2-base2:1.15 riastradh-drm2-base1:1.15 riastradh-drm2:1.15.0.58 riastradh-drm2-base:1.15 rmind-smpnet:1.15.0.50 rmind-smpnet-base:1.15 netbsd-6-1:1.15.0.56 netbsd-6-0-2-RELEASE:1.15 netbsd-6-1-RELEASE:1.15 khorben-n900:1.15.0.54 netbsd-6-1-RC4:1.15 netbsd-6-1-RC3:1.15 agc-symver:1.15.0.52 agc-symver-base:1.15 netbsd-6-1-RC2:1.15 netbsd-6-1-RC1:1.15 yamt-pagecache-base8:1.15 netbsd-5-2:1.15.0.48 netbsd-6-0-1-RELEASE:1.15 yamt-pagecache-base7:1.15 netbsd-5-2-RELEASE:1.15 netbsd-5-2-RC1:1.15 matt-nb6-plus-nbase:1.15 yamt-pagecache-base6:1.15 netbsd-6-0:1.15.0.46 netbsd-6-0-RELEASE:1.15 netbsd-6-0-RC2:1.15 tls-maxphys:1.15.0.44 tls-maxphys-base:1.15 matt-nb6-plus:1.15.0.42 matt-nb6-plus-base:1.15 netbsd-6-0-RC1:1.15 jmcneill-usbmp-base10:1.15 yamt-pagecache-base5:1.15 jmcneill-usbmp-base9:1.15 yamt-pagecache-base4:1.15 jmcneill-usbmp-base8:1.15 jmcneill-usbmp-base7:1.15 jmcneill-usbmp-base6:1.15 jmcneill-usbmp-base5:1.15 jmcneill-usbmp-base4:1.15 jmcneill-usbmp-base3:1.15 jmcneill-usbmp-pre-base2:1.15 jmcneill-usbmp-base2:1.15 netbsd-6:1.15.0.40 netbsd-6-base:1.15 netbsd-5-1-2-RELEASE:1.15 netbsd-5-1-1-RELEASE:1.15 jmcneill-usbmp:1.15.0.38 jmcneill-usbmp-base:1.15 jmcneill-audiomp3:1.15.0.36 jmcneill-audiomp3-base:1.15 yamt-pagecache-base3:1.15 yamt-pagecache-base2:1.15 yamt-pagecache:1.15.0.34 yamt-pagecache-base:1.15 rmind-uvmplock-nbase:1.15 cherry-xenmp:1.15.0.32 cherry-xenmp-base:1.15 jym-xensuspend-nbase:1.15 uebayasi-xip-base7:1.15 bouyer-quota2-nbase:1.15 bouyer-quota2:1.15.0.30 bouyer-quota2-base:1.15 jruoho-x86intr:1.15.0.28 jruoho-x86intr-base:1.15 matt-mips64-premerge-20101231:1.15 matt-nb5-mips64-premerge-20101231:1.15 matt-nb5-pq3:1.15.0.26 matt-nb5-pq3-base:1.15 netbsd-5-1:1.15.0.24 uebayasi-xip-base6:1.15 uebayasi-xip-base5:1.15 netbsd-5-1-RELEASE:1.15 uebayasi-xip-base4:1.15 uebayasi-xip-base3:1.15 yamt-nfs-mp-base11:1.15 netbsd-5-1-RC4:1.15 matt-nb5-mips64-k15:1.15 uebayasi-xip-base2:1.15 yamt-nfs-mp-base10:1.15 netbsd-5-1-RC3:1.15 netbsd-5-1-RC2:1.15 uebayasi-xip-base1:1.15 netbsd-5-1-RC1:1.15 rmind-uvmplock:1.15.0.22 rmind-uvmplock-base:1.15 yamt-nfs-mp-base9:1.15 uebayasi-xip:1.15.0.20 uebayasi-xip-base:1.15 netbsd-5-0-2-RELEASE:1.15 matt-nb5-mips64-premerge-20091211:1.15 matt-premerge-20091211:1.15 yamt-nfs-mp-base8:1.15 matt-nb5-mips64-u2-k2-k4-k7-k8-k9:1.15 matt-nb4-mips64-k7-u2a-k9b:1.15 matt-nb5-mips64-u1-k1-k5:1.15 yamt-nfs-mp-base7:1.15 matt-nb5-mips64:1.15.0.18 netbsd-5-0-1-RELEASE:1.15 jymxensuspend-base:1.15 yamt-nfs-mp-base6:1.15 yamt-nfs-mp-base5:1.15 yamt-nfs-mp-base4:1.15 yamt-nfs-mp-base3:1.15 nick-hppapmap-base4:1.15 nick-hppapmap-base3:1.15 netbsd-5-0:1.15.0.16 netbsd-5-0-RELEASE:1.15 netbsd-5-0-RC4:1.15 netbsd-5-0-RC3:1.15 nick-hppapmap-base2:1.15 netbsd-5-0-RC2:1.15 jym-xensuspend:1.15.0.14 jym-xensuspend-base:1.15 netbsd-5-0-RC1:1.15 haad-dm-base2:1.15 haad-nbase2:1.15 ad-audiomp2:1.15.0.12 ad-audiomp2-base:1.15 netbsd-5:1.15.0.10 netbsd-5-base:1.15 nick-hppapmap:1.15.0.8 nick-hppapmap-base:1.15 matt-mips64-base2:1.15 haad-dm-base1:1.15 wrstuden-revivesa-base-4:1.15 netbsd-4-0-1-RELEASE:1.14 wrstuden-revivesa-base-3:1.15 wrstuden-revivesa-base-2:1.15 wrstuden-fixsa-newbase:1.14 nick-csl-alignment-base5:1.14 haad-dm:1.15.0.6 haad-dm-base:1.15 wrstuden-revivesa-base-1:1.15 simonb-wapbl-nbase:1.15 yamt-pf42-base4:1.15 simonb-wapbl:1.15.0.4 simonb-wapbl-base:1.15 yamt-pf42-base3:1.15 hpcarm-cleanup-nbase:1.15 yamt-pf42-baseX:1.14 yamt-pf42-base2:1.15 yamt-nfs-mp-base2:1.15 wrstuden-revivesa:1.15.0.2 wrstuden-revivesa-base:1.15 yamt-nfs-mp:1.14.0.72 yamt-nfs-mp-base:1.14 yamt-pf42:1.14.0.70 yamt-pf42-base:1.14 ad-socklock-base1:1.14 yamt-lazymbuf-base15:1.14 yamt-lazymbuf-base14:1.14 keiichi-mipv6-nbase:1.14 mjf-devfs2:1.14.0.68 mjf-devfs2-base:1.15 nick-net80211-sync:1.14.0.66 nick-net80211-sync-base:1.14 keiichi-mipv6:1.14.0.64 keiichi-mipv6-base:1.14 bouyer-xeni386-merge1:1.14 matt-armv6-prevmlocking:1.14 wrstuden-fixsa-base-1:1.14 vmlocking2-base3:1.14 netbsd-4-0:1.14.0.62 netbsd-4-0-RELEASE:1.14 bouyer-xeni386-nbase:1.14 yamt-kmem-base3:1.14 cube-autoconf:1.14.0.60 cube-autoconf-base:1.14 yamt-kmem-base2:1.14 bouyer-xeni386:1.14.0.58 bouyer-xeni386-base:1.14 yamt-kmem:1.14.0.56 yamt-kmem-base:1.14 vmlocking2-base2:1.14 reinoud-bufcleanup-nbase:1.14 vmlocking2:1.14.0.54 vmlocking2-base1:1.14 netbsd-4-0-RC5:1.14 matt-nb4-arm:1.14.0.52 matt-nb4-arm-base:1.14 matt-armv6-nbase:1.14 jmcneill-base:1.14 netbsd-4-0-RC4:1.14 mjf-devfs:1.14.0.50 mjf-devfs-base:1.14 bouyer-xenamd64-base2:1.14 vmlocking-nbase:1.14 yamt-x86pmap-base4:1.14 bouyer-xenamd64:1.14.0.48 bouyer-xenamd64-base:1.14 netbsd-4-0-RC3:1.14 yamt-x86pmap-base3:1.14 yamt-x86pmap-base2:1.14 netbsd-4-0-RC2:1.14 yamt-x86pmap:1.14.0.46 yamt-x86pmap-base:1.14 netbsd-4-0-RC1:1.14 matt-armv6:1.14.0.44 matt-armv6-base:1.14 jmcneill-pm:1.14.0.42 jmcneill-pm-base:1.14 hpcarm-cleanup:1.14.0.40 hpcarm-cleanup-base:1.14 nick-csl-alignment:1.14.0.38 nick-csl-alignment-base:1.14 matt-mips64:1.14.0.36 matt-mips64-base:1.14 netbsd-3-1-1-RELEASE:1.11 netbsd-3-0-3-RELEASE:1.11 yamt-idlelwp-base8:1.14 wrstuden-fixsa:1.14.0.34 wrstuden-fixsa-base:1.14 ppcoea-renovation:1.14.0.32 ppcoea-renovation-base:1.14 thorpej-atomic:1.14.0.30 thorpej-atomic-base:1.14 reinoud-bufcleanup:1.14.0.28 reinoud-bufcleanup-base:1.14 mjf-ufs-trans:1.14.0.26 mjf-ufs-trans-base:1.14 vmlocking:1.14.0.24 vmlocking-base:1.14 ad-audiomp:1.14.0.22 ad-audiomp-base:1.14 yamt-idlelwp:1.14.0.20 post-newlock2-merge:1.14 newlock2-nbase:1.14 yamt-splraiseipl-base5:1.14 yamt-splraiseipl-base4:1.14 yamt-splraiseipl-base3:1.14 abandoned-netbsd-4-base:1.14 abandoned-netbsd-4:1.14.0.12 netbsd-3-1:1.11.0.22 netbsd-3-1-RELEASE:1.11 netbsd-3-0-2-RELEASE:1.11 yamt-splraiseipl-base2:1.14 netbsd-3-1-RC4:1.11 yamt-splraiseipl:1.14.0.16 yamt-splraiseipl-base:1.14 netbsd-3-1-RC3:1.11 yamt-pdpolicy-base9:1.14 newlock2:1.14.0.14 newlock2-base:1.14 yamt-pdpolicy-base8:1.14 netbsd-3-1-RC2:1.11 netbsd-3-1-RC1:1.11 yamt-pdpolicy-base7:1.14 netbsd-4:1.14.0.18 netbsd-4-base:1.14 yamt-pdpolicy-base6:1.14 chap-midi-nbase:1.14 netbsd-3-0-1-RELEASE:1.11 gdamore-uart:1.14.0.10 gdamore-uart-base:1.14 simonb-timcounters-final:1.12.6.1 yamt-pdpolicy-base5:1.14 chap-midi:1.14.0.8 chap-midi-base:1.14 yamt-pdpolicy-base4:1.14 yamt-pdpolicy-base3:1.14 peter-altq-base:1.14 peter-altq:1.14.0.6 yamt-pdpolicy-base2:1.14 elad-kernelauth-base:1.14 elad-kernelauth:1.14.0.4 yamt-pdpolicy:1.14.0.2 yamt-pdpolicy-base:1.14 yamt-uio_vmspace-base5:1.13 simonb-timecounters:1.12.0.6 simonb-timecounters-base:1.14 rpaulo-netinet-merge-pcb:1.12.0.4 rpaulo-netinet-merge-pcb-base:1.14 yamt-uio_vmspace:1.12.0.2 netbsd-3-0:1.11.0.20 netbsd-3-0-RELEASE:1.11 netbsd-3-0-RC6:1.11 yamt-readahead-base3:1.11 netbsd-3-0-RC5:1.11 netbsd-3-0-RC4:1.11 netbsd-3-0-RC3:1.11 yamt-readahead-base2:1.11 netbsd-3-0-RC2:1.11 yamt-readahead-pervnode:1.11 yamt-readahead-perfile:1.11 yamt-readahead:1.11.0.18 yamt-readahead-base:1.11 netbsd-3-0-RC1:1.11 yamt-vop-base3:1.11 netbsd-2-0-3-RELEASE:1.9 netbsd-2-1:1.9.0.22 yamt-vop-base2:1.11 thorpej-vnode-attr:1.11.0.16 thorpej-vnode-attr-base:1.11 netbsd-2-1-RELEASE:1.9 yamt-vop:1.11.0.14 yamt-vop-base:1.11 netbsd-2-1-RC6:1.9 netbsd-2-1-RC5:1.9 netbsd-2-1-RC4:1.9 netbsd-2-1-RC3:1.9 netbsd-2-1-RC2:1.9 netbsd-2-1-RC1:1.9 yamt-lazymbuf:1.11.0.12 yamt-km-base4:1.11 netbsd-2-0-2-RELEASE:1.9 yamt-km-base3:1.11 netbsd-3:1.11.0.10 netbsd-3-base:1.11 yamt-km-base2:1.11 yamt-km:1.11.0.6 yamt-km-base:1.11 kent-audio2:1.11.0.4 kent-audio2-base:1.11 netbsd-2-0-1-RELEASE:1.9 kent-audio1-beforemerge:1.11 netbsd-2:1.9.0.20 netbsd-2-base:1.9 kent-audio1:1.11.0.2 kent-audio1-base:1.11 netbsd-2-0-RELEASE:1.9 netbsd-2-0-RC5:1.9 netbsd-2-0-RC4:1.9 netbsd-2-0-RC3:1.9 netbsd-2-0-RC2:1.9 netbsd-2-0-RC1:1.9 netbsd-2-0:1.9.0.18 netbsd-2-0-base:1.9 netbsd-1-6-PATCH002-RELEASE:1.9 netbsd-1-6-PATCH002:1.9 netbsd-1-6-PATCH002-RC4:1.9 netbsd-1-6-PATCH002-RC3:1.9 netbsd-1-6-PATCH002-RC2:1.9 netbsd-1-6-PATCH002-RC1:1.9 ktrace-lwp:1.9.0.16 ktrace-lwp-base:1.11 netbsd-1-6-PATCH001:1.9 netbsd-1-6-PATCH001-RELEASE:1.9 netbsd-1-6-PATCH001-RC3:1.9 netbsd-1-6-PATCH001-RC2:1.9 netbsd-1-6-PATCH001-RC1:1.9 nathanw_sa_end:1.7.8.2 nathanw_sa_before_merge:1.9 fvdl_fs64_base:1.9 gmcgarry_ctxsw:1.9.0.14 gmcgarry_ctxsw_base:1.9 gmcgarry_ucred:1.9.0.12 gmcgarry_ucred_base:1.9 nathanw_sa_base:1.9 kqueue-aftermerge:1.9 kqueue-beforemerge:1.9 netbsd-1-6-RELEASE:1.9 netbsd-1-6-RC3:1.9 netbsd-1-6-RC2:1.9 netbsd-1-6-RC1:1.9 netbsd-1-6:1.9.0.10 netbsd-1-6-base:1.9 gehenna-devsw:1.9.0.8 gehenna-devsw-base:1.9 eeh-devprop:1.9.0.6 eeh-devprop-base:1.9 newlock:1.9.0.4 newlock-base:1.9 ifpoll-base:1.9 nathanw_sa:1.7.0.8 thorpej-mips-cache:1.7.0.6 thorpej-mips-cache-base:1.7 thorpej-devvp-base3:1.7 thorpej-devvp-base2:1.7 post-chs-ubcperf:1.7 pre-chs-ubcperf:1.7 thorpej-devvp:1.7.0.4 thorpej-devvp-base:1.7 kqueue:1.7.0.2 kqueue-base:1.9 thorpej_scsipi_beforemerge:1.6 thorpej_scsipi_base:1.5 thorpej_scsipi:1.1.0.2 thorpej_scsipi_nbase:1.5; locks; strict; comment @// @; 1.15 date 2008.04.28.20.23.20; author martin; state Exp; branches; next 1.14; 1.14 date 2006.03.05.04.05.39; author uwe; state Exp; branches 1.14.2.1 1.14.68.1 1.14.70.1 1.14.72.1; next 1.13; 1.13 date 2006.02.25.02.28.56; author wiz; state Exp; branches; next 1.12; 1.12 date 2005.12.11.12.17.28; author christos; state Exp; branches 1.12.2.1 1.12.4.1 1.12.6.1; next 1.11; 1.11 date 2004.08.13.15.50.09; author uch; state Exp; branches 1.11.12.1; next 1.10; 1.10 date 2004.08.06.17.21.28; author uch; state Exp; branches; next 1.9; 1.9 date 2002.02.11.17.08.56; author uch; state Exp; branches 1.9.16.1; next 1.8; 1.8 date 2002.02.04.17.38.27; author uch; state Exp; branches; next 1.7; 1.7 date 2001.05.08.18.51.25; author uch; state Exp; branches 1.7.2.1 1.7.8.1; next 1.6; 1.6 date 2001.04.24.19.28.01; author uch; state Exp; branches; next 1.5; 1.5 date 2001.03.25.17.13.17; author uch; state Exp; branches; next 1.4; 1.4 date 2001.03.22.18.27.51; author uch; state Exp; branches; next 1.3; 1.3 date 2001.03.02.18.26.38; author uch; state Exp; branches 1.3.2.1; next 1.2; 1.2 date 2001.02.21.16.01.54; author uch; state Exp; branches; next 1.1; 1.1 date 2001.02.09.18.35.16; author uch; state Exp; branches 1.1.2.1; next ; 1.14.2.1 date 2006.03.05.04.05.39; author uwe; state dead; branches; next 1.14.2.2; 1.14.2.2 date 2006.03.05.04.05.40; author uwe; state Exp; branches; next ; 1.14.68.1 date 2008.06.02.13.22.09; author mjf; state Exp; branches; next ; 1.14.70.1 date 2008.05.18.12.32.02; author yamt; state Exp; branches; next ; 1.14.72.1 date 2008.05.16.02.22.26; author yamt; state Exp; branches; next ; 1.12.2.1 date 2006.03.01.09.27.54; author yamt; state Exp; branches; next ; 1.12.4.1 date 2006.09.09.02.39.38; author rpaulo; state Exp; branches; next ; 1.12.6.1 date 2006.04.22.11.37.28; author simonb; state Exp; branches; next ; 1.11.12.1 date 2006.06.21.14.51.38; author yamt; state Exp; branches; next ; 1.9.16.1 date 2004.08.12.11.41.05; author skrll; state Exp; branches; next 1.9.16.2; 1.9.16.2 date 2004.08.25.06.57.18; author skrll; state Exp; branches; next 1.9.16.3; 1.9.16.3 date 2004.09.18.14.34.46; author skrll; state Exp; branches; next 1.9.16.4; 1.9.16.4 date 2004.09.21.13.15.53; author skrll; state Exp; branches; next 1.9.16.5; 1.9.16.5 date 2005.02.24.08.11.15; author skrll; state Exp; branches; next ; 1.7.2.1 date 2002.02.11.20.08.00; author jdolecek; state Exp; branches; next 1.7.2.2; 1.7.2.2 date 2002.03.16.15.57.52; author jdolecek; state Exp; branches; next ; 1.7.8.1 date 2001.05.08.18.51.25; author nathanw; state dead; branches; next 1.7.8.2; 1.7.8.2 date 2002.02.28.04.09.46; author nathanw; state Exp; branches; next ; 1.3.2.1 date 2001.04.09.01.52.46; author nathanw; state Exp; branches; next 1.3.2.2; 1.3.2.2 date 2001.06.21.19.23.01; author nathanw; state Exp; branches; next ; 1.1.2.1 date 2001.02.09.18.35.16; author bouyer; state dead; branches; next 1.1.2.2; 1.1.2.2 date 2001.02.11.19.10.12; author bouyer; state Exp; branches; next 1.1.2.3; 1.1.2.3 date 2001.03.12.13.28.17; author bouyer; state Exp; branches; next 1.1.2.4; 1.1.2.4 date 2001.03.27.15.30.49; author bouyer; state Exp; branches; next ; desc @@ 1.15 log @Remove clause 3 and 4 from TNF licenses @ text @/* $NetBSD: sh_arch.cpp,v 1.14 2006/03/05 04:05:39 uwe Exp $ */ /*- * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by UCHIYAMA Yasushi. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include SH_BOOT_FUNC_(7707); SH_BOOT_FUNC_(7709); SH_BOOT_FUNC_(7709A); SH_BOOT_FUNC_(7750); static int _cpu_type; int SHArchitecture::cpu_type() { if (_cpu_type == 0) { #if _WIN32_WCE == 101 _cpu_type = 3; #else SYSTEM_INFO si; GetSystemInfo(&si); _cpu_type = si.wProcessorLevel; #endif } return _cpu_type; } BOOL SHArchitecture::init() { if (!_mem->init()) { DPRINTF((TEXT("can't initialize memory manager.\n"))); return FALSE; } // D-RAM information DPRINTF((TEXT("Memory Bank:\n"))); return TRUE; } void SHArchitecture::systemInfo() { // Windows CE common information. super::systemInfo(); // CPU specific. _dev->dump(HPC_MENU._cons_parameter); } BOOL SHArchitecture::setupLoader() { vaddr_t v; if (!_mem->getPage(v , _loader_addr)) { DPRINTF((TEXT("can't get page for 2nd loader.\n"))); return FALSE; } _loader_addr = ptokv(_loader_addr); DPRINTF((TEXT("2nd bootloader address U0: 0x%08x P1: 0x%08x\n"), (unsigned)v,(unsigned)_loader_addr)); memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); return TRUE; } void SHArchitecture::jump(paddr_t info, paddr_t pvec) { kaddr_t sp; vaddr_t v; paddr_t p; // stack for bootloader _mem->getPage(v, p); sp = ptokv(p + _mem->getPageSize() / 2); info = ptokv(info); pvec = ptokv(pvec); DPRINTF((TEXT("boot arg: 0x%08x stack: 0x%08x\nBooting kernel...\n"), info, sp)); // Change to privilege-mode. SetKMode(1); // Cache flush(for 2nd bootloader) // // SH4 uses WinCE CacheSync(). this routine may causes TLB // exception. so calls before suspendIntr(). // cache_flush(); // Disable external interrupt. suspendIntr(); // jump to 2nd loader.(run P1) at this time I still use MMU. __asm( "mov r6, r15\n" "jmp @@r7\n" "nop \n", info, pvec, sp, _loader_addr); // NOTREACHED } // disable external interrupt and save its priority. uint32_t suspendIntr() { uint32_t sr; __asm( "stc sr, r0\n" "mov.l r0, @@r4\n" "or r5, r0\n" "ldc r0, sr\n", &sr, 0x000000f0); return sr & 0x000000f0; } // resume external interrupt priority. void resumeIntr(uint32_t s) { __asm( "stc sr, r0\n" "and r5, r0\n" "or r4, r0\n" "ldc r0, sr\n", s, 0xffffff0f); } @ 1.14 log @s/u_intN_t/uintN_t/ @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.13 2006/02/25 02:28:56 wiz Exp $ */ a17 7 * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the NetBSD * Foundation, Inc. and its contributors. * 4. Neither the name of The NetBSD Foundation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. @ 1.14.2.1 log @file sh_arch.cpp was added on branch yamt-pdpolicy on 2006-03-05 04:05:40 +0000 @ text @d1 172 @ 1.14.2.2 log @s/u_intN_t/uintN_t/ @ text @a0 172 /* $NetBSD: sh_arch.cpp,v 1.14 2006/03/05 04:05:39 uwe Exp $ */ /*- * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by UCHIYAMA Yasushi. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the NetBSD * Foundation, Inc. and its contributors. * 4. Neither the name of The NetBSD Foundation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include SH_BOOT_FUNC_(7707); SH_BOOT_FUNC_(7709); SH_BOOT_FUNC_(7709A); SH_BOOT_FUNC_(7750); static int _cpu_type; int SHArchitecture::cpu_type() { if (_cpu_type == 0) { #if _WIN32_WCE == 101 _cpu_type = 3; #else SYSTEM_INFO si; GetSystemInfo(&si); _cpu_type = si.wProcessorLevel; #endif } return _cpu_type; } BOOL SHArchitecture::init() { if (!_mem->init()) { DPRINTF((TEXT("can't initialize memory manager.\n"))); return FALSE; } // D-RAM information DPRINTF((TEXT("Memory Bank:\n"))); return TRUE; } void SHArchitecture::systemInfo() { // Windows CE common information. super::systemInfo(); // CPU specific. _dev->dump(HPC_MENU._cons_parameter); } BOOL SHArchitecture::setupLoader() { vaddr_t v; if (!_mem->getPage(v , _loader_addr)) { DPRINTF((TEXT("can't get page for 2nd loader.\n"))); return FALSE; } _loader_addr = ptokv(_loader_addr); DPRINTF((TEXT("2nd bootloader address U0: 0x%08x P1: 0x%08x\n"), (unsigned)v,(unsigned)_loader_addr)); memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); return TRUE; } void SHArchitecture::jump(paddr_t info, paddr_t pvec) { kaddr_t sp; vaddr_t v; paddr_t p; // stack for bootloader _mem->getPage(v, p); sp = ptokv(p + _mem->getPageSize() / 2); info = ptokv(info); pvec = ptokv(pvec); DPRINTF((TEXT("boot arg: 0x%08x stack: 0x%08x\nBooting kernel...\n"), info, sp)); // Change to privilege-mode. SetKMode(1); // Cache flush(for 2nd bootloader) // // SH4 uses WinCE CacheSync(). this routine may causes TLB // exception. so calls before suspendIntr(). // cache_flush(); // Disable external interrupt. suspendIntr(); // jump to 2nd loader.(run P1) at this time I still use MMU. __asm( "mov r6, r15\n" "jmp @@r7\n" "nop \n", info, pvec, sp, _loader_addr); // NOTREACHED } // disable external interrupt and save its priority. uint32_t suspendIntr() { uint32_t sr; __asm( "stc sr, r0\n" "mov.l r0, @@r4\n" "or r5, r0\n" "ldc r0, sr\n", &sr, 0x000000f0); return sr & 0x000000f0; } // resume external interrupt priority. void resumeIntr(uint32_t s) { __asm( "stc sr, r0\n" "and r5, r0\n" "or r4, r0\n" "ldc r0, sr\n", s, 0xffffff0f); } @ 1.14.68.1 log @Sync with HEAD. @ text @d1 1 a1 1 /* $NetBSD$ */ d18 7 @ 1.14.70.1 log @sync with head. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.14 2006/03/05 04:05:39 uwe Exp $ */ d18 7 @ 1.14.72.1 log @sync with head. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.14 2006/03/05 04:05:39 uwe Exp $ */ d18 7 @ 1.13 log @Fix some typos. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.12 2005/12/11 12:17:28 christos Exp $ */ d149 1 a149 1 u_int32_t d152 1 a152 1 u_int32_t sr; d164 1 a164 1 resumeIntr(u_int32_t s) @ 1.12 log @merge ktrace-lwp. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.9.16.5 2005/02/24 08:11:15 skrll Exp $ */ d84 1 a84 1 // Windows CE common infomation. @ 1.12.4.1 log @sync with head @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.14 2006/03/05 04:05:39 uwe Exp $ */ d84 1 a84 1 // Windows CE common information. d149 1 a149 1 uint32_t d152 1 a152 1 uint32_t sr; d164 1 a164 1 resumeIntr(uint32_t s) @ 1.12.6.1 log @Sync with head. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.14 2006/03/05 04:05:39 uwe Exp $ */ d84 1 a84 1 // Windows CE common information. d149 1 a149 1 uint32_t d152 1 a152 1 uint32_t sr; d164 1 a164 1 resumeIntr(uint32_t s) @ 1.12.2.1 log @sync with head. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.12 2005/12/11 12:17:28 christos Exp $ */ d84 1 a84 1 // Windows CE common information. @ 1.11 log @add SH7707 @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.10 2004/08/06 17:21:28 uch Exp $ */ @ 1.11.12.1 log @sync with head. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.11 2004/08/13 15:50:09 uch Exp $ */ d84 1 a84 1 // Windows CE common information. d149 1 a149 1 uint32_t d152 1 a152 1 uint32_t sr; d164 1 a164 1 resumeIntr(uint32_t s) @ 1.10 log @make hpcboot.exe compile on VC5 (H/PC Ver.1.01 for MIPS, H/PC Ver.2.00 for SH). @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.9 2002/02/11 17:08:56 uch Exp $ */ d43 1 @ 1.9 log @totaly clean up SH3/SH4 related code @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.8 2002/02/04 17:38:27 uch Exp $ */ d4 1 a4 1 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. d53 3 d59 1 @ 1.9.16.1 log @Sync with HEAD. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.9 2002/02/11 17:08:56 uch Exp $ */ a52 3 #if _WIN32_WCE == 101 _cpu_type = 3; #else a55 1 #endif @ 1.9.16.2 log @Sync with HEAD. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.9.16.1 2004/08/12 11:41:05 skrll Exp $ */ a42 1 SH_BOOT_FUNC_(7707); @ 1.9.16.3 log @Sync with HEAD. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.11 2004/08/13 15:50:09 uch Exp $ */ d4 1 a4 1 * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. @ 1.9.16.4 log @Fix the sync with head I botched. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.9.16.2 2004/08/25 06:57:18 skrll Exp $ */ d4 1 a4 1 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. @ 1.9.16.5 log @Fix merge botches that lost copyright updates. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.9.16.4 2004/09/21 13:15:53 skrll Exp $ */ d4 1 a4 1 * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. @ 1.8 log @SH4 and HD64465(SH4 companion chip) serial console support. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.7 2001/05/08 18:51:25 uch Exp $ */ d42 18 a59 29 #include #include #include "scifreg.h" static void __tmu_channel_info(int, paddr_t, paddr_t, paddr_t); struct SHArchitecture::intr_priority SHArchitecture::ipr_table[] = { { "TMU0", ICU_IPRA_REG16, 12 }, { "TMU1", ICU_IPRA_REG16, 8 }, { "TMU2", ICU_IPRA_REG16, 4 }, { "RTC", ICU_IPRA_REG16, 0 }, { "WDT", ICU_IPRB_REG16, 12 }, { "REF", ICU_IPRB_REG16, 8 }, { "SCI", ICU_IPRB_REG16, 4 }, { "reserve", ICU_IPRB_REG16, 0 }, { "IRQ3", ICU_IPRC_REG16, 12 }, { "IRQ2", ICU_IPRC_REG16, 8 }, { "IRQ1", ICU_IPRC_REG16, 4 }, { "IRQ0", ICU_IPRC_REG16, 0 }, { "PINT0-7", ICU_IPRD_REG16, 12 }, { "PINT8-15", ICU_IPRD_REG16, 8 }, { "IRQ5", ICU_IPRD_REG16, 4 }, { "IRQ4", ICU_IPRD_REG16, 0 }, { "DMAC", ICU_IPRE_REG16, 12 }, { "IrDA", ICU_IPRE_REG16, 8 }, { "SCIF", ICU_IPRE_REG16, 4 }, { "ADC", ICU_IPRE_REG16, 0 }, { 0, 0, 0} /* terminator */ }; d62 1 a62 1 SHArchitecture::init(void) d69 1 a69 1 // set D-RAM information a70 2 _mem->loadBank(DRAM_BANK0_START, DRAM_BANK_SIZE); _mem->loadBank(DRAM_BANK1_START, DRAM_BANK_SIZE); d75 11 d95 3 a97 1 DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"), d118 1 a118 1 _loader_addr = ptokv(_loader_addr); d145 1 a145 1 suspendIntr(void) d152 1 a152 1 "or r5, r0\n" d162 2 a163 1 __asm("stc sr, r0\n" d165 1 a165 1 "or r4, r0\n" a167 692 void SHArchitecture::print_stack_pointer(void) { int sp; __asm("mov.l r15, @@r4", &sp); DPRINTF((TEXT("SP 0x%08x\n"), sp)); } void SHArchitecture::systemInfo() { u_int32_t reg; HpcMenuInterface &menu = HpcMenuInterface::Instance(); Architecture::systemInfo(); // check debug level. if (menu._cons_parameter == 0) return; _kmode = SetKMode(1); // Cache reg = VOLATILE_REF(CCR); DPRINTF((TEXT("Cache "))); if (reg & CCR_CE) DPRINTF((TEXT("Enabled. %s-mode, P0/U0/P3 Write-%s, P1 Write-%s\n"), reg & CCR_RA ? TEXT("RAM") : TEXT("normal"), reg & CCR_WT ? TEXT("Through") : TEXT("Back"), reg & CCR_CB ? TEXT("Back") : TEXT("Through"))); else DPRINTF((TEXT("Disabled.\n"))); // MMU reg = VOLATILE_REF(MMUCR); DPRINTF((TEXT("MMU "))); if (reg & MMUCR_AT) DPRINTF((TEXT("Enabled. %s index-mode, %s virtual storage mode\n"), reg & MMUCR_IX ? TEXT("ASID + VPN") : TEXT("VPN only"), reg & MMUCR_SV ? TEXT("single") : TEXT("multiple"))); else DPRINTF((TEXT("Disabled.\n"))); // Status register reg = 0; __asm("stc sr, r0\n" "mov.l r0, @@r4", ®); DPRINTF((TEXT("SR 0x%08x\n"), reg)); // BSC bsc_dump(); // ICU print_stack_pointer(); icu_dump(); // TMU tmu_dump(); // PFC , I/O port pfc_dump(); // SCIF scif_dump(HPC_PREFERENCE.serial_speed); // HD64461 platid_t platform; platform.dw.dw0 = menu._pref.platid_hi; platform.dw.dw1 = menu._pref.platid_lo; hd64461_dump(platform); SetKMode(_kmode); } void SHArchitecture::icu_dump(void) { DPRINTF((TEXT("<<>>\n"))); print_stack_pointer(); DPRINTF((TEXT("ICR0 0x%08x\n"), reg_read_2(ICU_ICR0_REG16))); DPRINTF((TEXT("ICR1 0x%08x\n"), reg_read_2(ICU_ICR1_REG16))); DPRINTF((TEXT("ICR2 0x%08x\n"), reg_read_2(ICU_ICR2_REG16))); DPRINTF((TEXT("PINTER 0x%08x\n"), reg_read_2(ICU_PINTER_REG16))); DPRINTF((TEXT("IPRA 0x%08x\n"), reg_read_2(ICU_IPRA_REG16))); DPRINTF((TEXT("IPRB 0x%08x\n"), reg_read_2(ICU_IPRB_REG16))); DPRINTF((TEXT("IPRC 0x%08x\n"), reg_read_2(ICU_IPRC_REG16))); DPRINTF((TEXT("IPRD 0x%08x\n"), reg_read_2(ICU_IPRD_REG16))); DPRINTF((TEXT("IPRE 0x%08x\n"), reg_read_2(ICU_IPRE_REG16))); DPRINTF((TEXT("IRR0 0x%08x\n"), reg_read_1(ICU_IRR0_REG8))); DPRINTF((TEXT("IRR1 0x%08x\n"), reg_read_1(ICU_IRR1_REG8))); DPRINTF((TEXT("IRR2 0x%08x\n"), reg_read_1(ICU_IRR2_REG8))); icu_control(); icu_priority(); } void SHArchitecture::icu_priority(void) { struct intr_priority *tab; DPRINTF((TEXT("----interrupt priority----\n"))); for (tab = ipr_table; tab->name; tab++) { DPRINTF((TEXT("%-10S %d\n"), tab->name, (reg_read_2(tab->reg) >> tab->shift) & ICU_IPR_MASK)); } DPRINTF((TEXT("--------------------------\n"))); } void SHArchitecture::icu_control(void) { const char *sense_select[] = { "falling edge", "raising edge", "low level", "reserved", }; u_int16_t r; // PINT0-15 DPRINTF((TEXT("PINT enable(on |) :"))); bitdisp(reg_read_2(ICU_PINTER_REG16)); DPRINTF((TEXT("PINT detect(high |):"))); bitdisp(reg_read_2(ICU_ICR2_REG16)); // NMI r = reg_read_2(ICU_ICR0_REG16); DPRINTF((TEXT("NMI(%S %S-edge),"), r & ICU_ICR0_NMIL ? "High" : "Low", r & ICU_ICR0_NMIE ? "raising" : "falling")); r = reg_read_2(ICU_ICR1_REG16); DPRINTF((TEXT(" %S maskable,"), r & ICU_ICR1_MAI ? "" : "never")); DPRINTF((TEXT(" SR.BL %S\n"), r & ICU_ICR1_BLMSK ? "ignored" : "maskable")); // IRQ0-5 DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"), r & ICU_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]")); if (r & ICU_ICR1_IRQLVL) { DPRINTF((TEXT("IRLS[0:3] %S\n"), r & ICU_ICR1_IRLSEN ? "enabled" : "disabled")); } // sense select for (int i = 5; i >= 0; i--) { DPRINTF((TEXT("IRQ[%d] %S\n"), i, sense_select [ (r >>(i * 2)) & ICU_SENSE_SELECT_MASK])); } } SH_BOOT_FUNC_(7709); SH_BOOT_FUNC_(7709A); SH_BOOT_FUNC_(7750); // // Debug Functions. // void SHArchitecture::bsc_dump() { DPRINTF((TEXT("<<>>\n"))); #define DUMP_BSC_REG(x) \ DPRINTF((TEXT("%-8S"), #x)); \ bitdisp(reg_read_2(SH3_BSC_##x##_REG)) DUMP_BSC_REG(BCR1); DUMP_BSC_REG(BCR2); DUMP_BSC_REG(WCR1); DUMP_BSC_REG(WCR2); DUMP_BSC_REG(MCR); DUMP_BSC_REG(DCR); DUMP_BSC_REG(PCR); DUMP_BSC_REG(RTCSR); DUMP_BSC_REG(RTCNT); DUMP_BSC_REG(RTCOR); DUMP_BSC_REG(RFCR); DUMP_BSC_REG(BCR3); #undef DUMP_BSC_REG } void SHArchitecture::scif_dump(int bps) { u_int16_t r16; #ifdef SH4 u_int16_t r8; #else u_int8_t r8; #endif int n; DPRINTF((TEXT("<<>>\n"))); /* mode */ r8 = SHREG_SCSMR2; n = 1 <<((r8 & SCSMR2_CKS) << 1); DPRINTF((TEXT("mode: %dbit %S-parity %d stop bit clock PCLOCK/%d\n"), r8 & SCSMR2_CHR ? 7 : 8, r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", r8 & SCSMR2_STOP ? 2 : 1, n)); /* bit rate */ r8 = SHREG_SCBRR2; DPRINTF((TEXT("SCBRR=%d(%dbps) estimated PCLOCK %dHz\n"), r8, bps, 32 * bps *(r8 + 1) * n)); /* control */ #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSCR2_##m, #m) DPRINTF((TEXT("SCSCR2: "))); r8 = SHREG_SCSCR2; DBG_BIT_PRINT(r8, TIE); DBG_BIT_PRINT(r8, RIE); DBG_BIT_PRINT(r8, TE); DBG_BIT_PRINT(r8, RE); DPRINTF((TEXT("CKE=%d\n"), r8 & SCSCR2_CKE)); #undef DBG_BIT_PRINT /* status */ #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSSR2_##m, #m) r16 = SHREG_SCSSR2; DPRINTF((TEXT("SCSSR2: "))); DBG_BIT_PRINT(r16, ER); DBG_BIT_PRINT(r16, TEND); DBG_BIT_PRINT(r16, TDFE); DBG_BIT_PRINT(r16, BRK); DBG_BIT_PRINT(r16, FER); DBG_BIT_PRINT(r16, PER); DBG_BIT_PRINT(r16, RDF); DBG_BIT_PRINT(r16, DR); #undef DBG_BIT_PRINT /* FIFO control */ #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCFCR2_##m, #m) r8 = SHREG_SCFCR2; DPRINTF((TEXT("SCFCR2: "))); DBG_BIT_PRINT(r8, RTRG1); DBG_BIT_PRINT(r8, RTRG0); DBG_BIT_PRINT(r8, TTRG1); DBG_BIT_PRINT(r8, TTRG0); DBG_BIT_PRINT(r8, MCE); DBG_BIT_PRINT(r8, TFRST); DBG_BIT_PRINT(r8, RFRST); DBG_BIT_PRINT(r8, LOOP); DPRINTF((TEXT("\n"))); #undef DBG_BIT_PRINT } void SHArchitecture::pfc_dump() { DPRINTF((TEXT("<<>>\n"))); DPRINTF((TEXT("[control]\n"))); #define DUMP_PFC_REG(x) \ DPRINTF((TEXT("P%SCR :"), #x)); \ bitdisp(reg_read_2(SH3_P##x##CR_REG16)) DUMP_PFC_REG(A); DUMP_PFC_REG(B); DUMP_PFC_REG(C); DUMP_PFC_REG(D); DUMP_PFC_REG(E); DUMP_PFC_REG(F); DUMP_PFC_REG(G); DUMP_PFC_REG(H); DUMP_PFC_REG(J); DUMP_PFC_REG(K); DUMP_PFC_REG(L); #undef DUMP_PFC_REG DPRINTF((TEXT("SCPCR :"))); bitdisp(reg_read_2(SH3_SCPCR_REG16)); DPRINTF((TEXT("\n[data]\n"))); #define DUMP_IOPORT_REG(x) \ DPRINTF((TEXT("P%SDR :"), #x)); \ bitdisp(reg_read_1(SH3_P##x##DR_REG8)) DUMP_IOPORT_REG(A); DUMP_IOPORT_REG(B); DUMP_IOPORT_REG(C); DUMP_IOPORT_REG(D); DUMP_IOPORT_REG(E); DUMP_IOPORT_REG(F); DUMP_IOPORT_REG(G); DUMP_IOPORT_REG(H); DUMP_IOPORT_REG(J); DUMP_IOPORT_REG(K); DUMP_IOPORT_REG(L); #undef DUMP_IOPORT_REG DPRINTF((TEXT("SCPDR :"))); bitdisp(reg_read_1(SH3_SCPDR_REG8)); } void SHArchitecture::tmu_dump() { u_int8_t r8; DPRINTF((TEXT("<<>>\n"))); /* Common */ /* TOCR timer output control register */ r8 = reg_read_1(SH3_TOCR_REG8); DPRINTF((TEXT("TCLK = %S\n"), r8 & TOCR_TCOE ? "RTC output" : "input")); /* TSTR */ r8 = reg_read_1(SH3_TSTR_REG8); DPRINTF((TEXT("Timer start(#0:2) [%c][%c][%c]\n"), r8 & TSTR_STR0 ? 'x' : '_', r8 & TSTR_STR1 ? 'x' : '_', r8 & TSTR_STR2 ? 'x' : '_')); #define CHANNEL_DUMP(a, x) \ tmu_channel_dump(x, SH##a##_TCOR##x##_REG, \ SH##a##_TCNT##x##_REG, \ SH##a##_TCR##x##_REG16) CHANNEL_DUMP(3, 0); CHANNEL_DUMP(3, 1); CHANNEL_DUMP(3, 2); #undef CHANNEL_DUMP DPRINTF((TEXT("\n"))); } void SHArchitecture::tmu_channel_dump(int unit, paddr_t tcor, paddr_t tcnt, paddr_t tcr) { u_int32_t r32; u_int16_t r16; DPRINTF((TEXT("TMU#%d:"), unit)); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, TCR_##m, #m) /* TCR*/ r16 = reg_read_2(tcr); DBG_BIT_PRINT(r16, UNF); DBG_BIT_PRINT(r16, UNIE); DBG_BIT_PRINT(r16, CKEG1); DBG_BIT_PRINT(r16, CKEG0); DBG_BIT_PRINT(r16, TPSC2); DBG_BIT_PRINT(r16, TPSC1); DBG_BIT_PRINT(r16, TPSC0); /* channel 2 has input capture. */ if (unit == 2) { DBG_BIT_PRINT(r16, ICPF); DBG_BIT_PRINT(r16, ICPE1); DBG_BIT_PRINT(r16, ICPE0); } #undef DBG_BIT_PRINT /* TCNT0 timer counter */ r32 = reg_read_4(tcnt); DPRINTF((TEXT("\ncnt=0x%08x"), r32)); /* TCOR0 timer constant register */ r32 = reg_read_4(tcor); DPRINTF((TEXT(" constant=0x%04x"), r32)); if (unit == 2) DPRINTF((TEXT(" input capture=0x%08x\n"), SH3_TCPR2_REG)); else DPRINTF((TEXT("\n"))); } void SHArchitecture::hd64461_dump(platid_t &platform) { u_int16_t r16; u_int8_t r8; #define MATCH(p) \ platid_match(&platform, &platid_mask_MACH_##p) DPRINTF((TEXT("<<>>\n"))); if (!MATCH(HP_LX) && !MATCH(HP_JORNADA_6XX) && !MATCH(HITACHI_PERSONA_HPW230JC)) { DPRINTF((TEXT("don't exist."))); return; } #if 0 DPRINTF((TEXT("frame buffer test start\n"))); u_int8_t *fb = reinterpret_cast(HD64461_FBBASE); for (int i = 0; i < 320 * 240 * 2 / 8; i++) *fb++ = 0xff; DPRINTF((TEXT("frame buffer test end\n"))); #endif // System DPRINTF((TEXT("STBCR (System Control Register)\n"))); r16 = reg_read_2(HD64461_SYSSTBCR_REG16); bitdisp(r16); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m) DBG_BIT_PRINT(r16, CKIO_STBY); DBG_BIT_PRINT(r16, SAFECKE_IST); DBG_BIT_PRINT(r16, SLCKE_IST); DBG_BIT_PRINT(r16, SAFECKE_OST); DBG_BIT_PRINT(r16, SLCKE_OST); DBG_BIT_PRINT(r16, SMIAST); DBG_BIT_PRINT(r16, SLCDST); DBG_BIT_PRINT(r16, SPC0ST); DBG_BIT_PRINT(r16, SPC1ST); DBG_BIT_PRINT(r16, SAFEST); DBG_BIT_PRINT(r16, STM0ST); DBG_BIT_PRINT(r16, STM1ST); DBG_BIT_PRINT(r16, SIRST); DBG_BIT_PRINT(r16, SURTSD); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("SYSCR (System Configuration Register)\n"))); r16 = reg_read_2(HD64461_SYSSYSCR_REG16); bitdisp(r16); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m) DBG_BIT_PRINT(r16, SCPU_BUS_IGAT); DBG_BIT_PRINT(r16, SPTA_IR); DBG_BIT_PRINT(r16, SPTA_TM); DBG_BIT_PRINT(r16, SPTB_UR); DBG_BIT_PRINT(r16, WAIT_CTL_SEL); DBG_BIT_PRINT(r16, SMODE1); DBG_BIT_PRINT(r16, SMODE0); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n"))); r16 = reg_read_2(HD64461_SYSSCPUCR_REG16); bitdisp(r16); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m) DBG_BIT_PRINT(r16, SPDSTOF); DBG_BIT_PRINT(r16, SPDSTIG); DBG_BIT_PRINT(r16, SPCSTOF); DBG_BIT_PRINT(r16, SPCSTIG); DBG_BIT_PRINT(r16, SPBSTOF); DBG_BIT_PRINT(r16, SPBSTIG); DBG_BIT_PRINT(r16, SPASTOF); DBG_BIT_PRINT(r16, SPASTIG); DBG_BIT_PRINT(r16, SLCDSTIG); DBG_BIT_PRINT(r16, SCPU_CS56_EP); DBG_BIT_PRINT(r16, SCPU_CMD_EP); DBG_BIT_PRINT(r16, SCPU_ADDR_EP); DBG_BIT_PRINT(r16, SCPDPU); DBG_BIT_PRINT(r16, SCPU_A2319_EP); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("\n"))); // INTC DPRINTF((TEXT("NIRR (Interrupt Request Register)\n"))); r16 = reg_read_2(HD64461_INTCNIRR_REG16); bitdisp(r16); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIRR_##m, #m) DBG_BIT_PRINT(r16, PCC0R); DBG_BIT_PRINT(r16, PCC1R); DBG_BIT_PRINT(r16, AFER); DBG_BIT_PRINT(r16, GPIOR); DBG_BIT_PRINT(r16, TMU0R); DBG_BIT_PRINT(r16, TMU1R); DBG_BIT_PRINT(r16, IRDAR); DBG_BIT_PRINT(r16, UARTR); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n"))); r16 = reg_read_2(HD64461_INTCNIMR_REG16); bitdisp(r16); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIMR_##m, #m) DBG_BIT_PRINT(r16, PCC0M); DBG_BIT_PRINT(r16, PCC1M); DBG_BIT_PRINT(r16, AFEM); DBG_BIT_PRINT(r16, GPIOM); DBG_BIT_PRINT(r16, TMU0M); DBG_BIT_PRINT(r16, TMU1M); DBG_BIT_PRINT(r16, IRDAM); DBG_BIT_PRINT(r16, UARTM); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("\n"))); // PCMCIA // PCC0 DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n"))); DPRINTF((TEXT("PCC0 Interface Status Register\n"))); r8 = reg_read_1(HD64461_PCC0ISR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) DBG_BIT_PRINT(r8, P0READY); DBG_BIT_PRINT(r8, P0MWP); DBG_BIT_PRINT(r8, P0VS2); DBG_BIT_PRINT(r8, P0VS1); DBG_BIT_PRINT(r8, P0CD2); DBG_BIT_PRINT(r8, P0CD1); DBG_BIT_PRINT(r8, P0BVD2); DBG_BIT_PRINT(r8, P0BVD1); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC0 General Control Register\n"))); r8 = reg_read_1(HD64461_PCC0GCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) DBG_BIT_PRINT(r8, P0DRVE); DBG_BIT_PRINT(r8, P0PCCR); DBG_BIT_PRINT(r8, P0PCCT); DBG_BIT_PRINT(r8, P0VCC0); DBG_BIT_PRINT(r8, P0MMOD); DBG_BIT_PRINT(r8, P0PA25); DBG_BIT_PRINT(r8, P0PA24); DBG_BIT_PRINT(r8, P0REG); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC0 Card Status Change Register\n"))); r8 = reg_read_1(HD64461_PCC0CSCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) DBG_BIT_PRINT(r8, P0SCDI); DBG_BIT_PRINT(r8, P0IREQ); DBG_BIT_PRINT(r8, P0SC); DBG_BIT_PRINT(r8, P0CDC); DBG_BIT_PRINT(r8, P0RC); DBG_BIT_PRINT(r8, P0BW); DBG_BIT_PRINT(r8, P0BD); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n"))); r8 = reg_read_1(HD64461_PCC0CSCIER_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) DBG_BIT_PRINT(r8, P0CRE); DBG_BIT_PRINT(r8, P0SCE); DBG_BIT_PRINT(r8, P0CDE); DBG_BIT_PRINT(r8, P0RE); DBG_BIT_PRINT(r8, P0BWE); DBG_BIT_PRINT(r8, P0BDE); #undef DBG_BIT_PRINT DPRINTF((TEXT("\ninterrupt type: "))); switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { case HD64461_PCC0CSCIER_P0IREQE_NONE: DPRINTF((TEXT("none\n"))); break; case HD64461_PCC0CSCIER_P0IREQE_LEVEL: DPRINTF((TEXT("level\n"))); break; case HD64461_PCC0CSCIER_P0IREQE_FEDGE: DPRINTF((TEXT("falling edge\n"))); break; case HD64461_PCC0CSCIER_P0IREQE_REDGE: DPRINTF((TEXT("rising edge\n"))); break; } DPRINTF((TEXT("PCC0 Software Control Register\n"))); r8 = reg_read_1(HD64461_PCC0SCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) DBG_BIT_PRINT(r8, P0VCC1); DBG_BIT_PRINT(r8, P0SWP); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); // PCC1 DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n"))); DPRINTF((TEXT("PCC1 Interface Status Register\n"))); r8 = reg_read_1(HD64461_PCC1ISR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) DBG_BIT_PRINT(r8, P1READY); DBG_BIT_PRINT(r8, P1MWP); DBG_BIT_PRINT(r8, P1VS2); DBG_BIT_PRINT(r8, P1VS1); DBG_BIT_PRINT(r8, P1CD2); DBG_BIT_PRINT(r8, P1CD1); DBG_BIT_PRINT(r8, P1BVD2); DBG_BIT_PRINT(r8, P1BVD1); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC1 General Contorol Register\n"))); r8 = reg_read_1(HD64461_PCC1GCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) DBG_BIT_PRINT(r8, P1DRVE); DBG_BIT_PRINT(r8, P1PCCR); DBG_BIT_PRINT(r8, P1VCC0); DBG_BIT_PRINT(r8, P1MMOD); DBG_BIT_PRINT(r8, P1PA25); DBG_BIT_PRINT(r8, P1PA24); DBG_BIT_PRINT(r8, P1REG); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC1 Card Status Change Register\n"))); r8 = reg_read_1(HD64461_PCC1CSCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) DBG_BIT_PRINT(r8, P1SCDI); DBG_BIT_PRINT(r8, P1CDC); DBG_BIT_PRINT(r8, P1RC); DBG_BIT_PRINT(r8, P1BW); DBG_BIT_PRINT(r8, P1BD); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n"))); r8 = reg_read_1(HD64461_PCC1CSCIER_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) DBG_BIT_PRINT(r8, P1CRE); DBG_BIT_PRINT(r8, P1CDE); DBG_BIT_PRINT(r8, P1RE); DBG_BIT_PRINT(r8, P1BWE); DBG_BIT_PRINT(r8, P1BDE); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC1 Software Control Register\n"))); r8 = reg_read_1(HD64461_PCC1SCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) DBG_BIT_PRINT(r8, P1VCC1); DBG_BIT_PRINT(r8, P1SWP); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); // General Control DPRINTF((TEXT("[General Control]\n"))); DPRINTF((TEXT("PCC0 Output pins Control Register\n"))); r8 = reg_read_1(HD64461_PCCP0OCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) DBG_BIT_PRINT(r8, P0DEPLUP); DBG_BIT_PRINT(r8, P0AEPLUP); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC1 Output pins Control Register\n"))); r8 = reg_read_1(HD64461_PCCP1OCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) DBG_BIT_PRINT(r8, P1RST8MA); DBG_BIT_PRINT(r8, P1RST4MA); DBG_BIT_PRINT(r8, P1RAS8MA); DBG_BIT_PRINT(r8, P1RAS4MA); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PC Card General Control Register\n"))); r8 = reg_read_1(HD64461_PCCPGCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) DBG_BIT_PRINT(r8, PSSDIR); DBG_BIT_PRINT(r8, PSSRDWR); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); // GPIO #define GPIO_DUMP_REG8(x) \ bitdisp(reg_read_1(HD64461_GPA##x##R_REG16)); \ bitdisp(reg_read_1(HD64461_GPB##x##R_REG16)); \ bitdisp(reg_read_1(HD64461_GPC##x##R_REG16)); \ bitdisp(reg_read_1(HD64461_GPD##x##R_REG16)) #define GPIO_DUMP_REG16(x) \ bitdisp(reg_read_2(HD64461_GPA##x##R_REG16)); \ bitdisp(reg_read_2(HD64461_GPB##x##R_REG16)); \ bitdisp(reg_read_2(HD64461_GPC##x##R_REG16)); \ bitdisp(reg_read_2(HD64461_GPD##x##R_REG16)) DPRINTF((TEXT("GPIO Port Control Register\n"))); GPIO_DUMP_REG16(C); DPRINTF((TEXT("GPIO Port Data Register\n"))); GPIO_DUMP_REG8(D); DPRINTF((TEXT("GPIO Port Interrupt Control Register\n"))); GPIO_DUMP_REG8(IC); DPRINTF((TEXT("GPIO Port Interrupt Status Register\n"))); GPIO_DUMP_REG8(IS); } #ifdef SH7709TEST u_int32_t sh7707_fb_dma_addr; u_int16_t val; int s; s = suspendIntr(); VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR0; val = VOLATILE_REF16(SH7707_LCDDMR_REG16); sh7707_fb_dma_addr = val; VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR1; val = VOLATILE_REF16(SH7707_LCDDMR_REG16); sh7707_fb_dma_addr |= (val << 16); resumeIntr(s); DPRINTF((TEXT("SH7707 frame buffer dma address: 0x%08x\n"), sh7707_fb_dma_addr)); #endif @ 1.7 log @KNF. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.6 2001/04/24 19:28:01 uch Exp $ */ d4 1 a4 1 * Copyright (c) 2001 The NetBSD Foundation, Inc. d39 1 d43 1 d75 1 d81 1 a100 1 DPRINTF((TEXT("2nd bootloader copy done.\n"))); d119 1 a119 1 DPRINTF((TEXT("BootArgs 0x%08x Stack 0x%08x\nBooting kernel...\n"), d125 7 a134 3 // Cache flush(for 2nd bootloader) cache_flush(); d136 2 a137 1 __asm("mov r6, r15\n" d139 1 a139 1 "nop\n", info, pvec, sp, _loader_addr); d148 3 a150 1 __asm("stc sr, r0\n" d161 1 d172 1 d247 1 d271 1 d322 1 d330 1 d354 3 d358 1 d367 1 a367 1 r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", @ 1.7.8.1 log @file sh_arch.cpp was added on branch nathanw_sa on 2002-02-28 04:09:46 +0000 @ text @d1 838 @ 1.7.8.2 log @Catch up to -current. @ text @a0 167 /* $NetBSD: sh_arch.cpp,v 1.7.8.1 2002/02/28 04:09:46 nathanw Exp $ */ /*- * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by UCHIYAMA Yasushi. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the NetBSD * Foundation, Inc. and its contributors. * 4. Neither the name of The NetBSD Foundation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include SH_BOOT_FUNC_(7709); SH_BOOT_FUNC_(7709A); SH_BOOT_FUNC_(7750); static int _cpu_type; int SHArchitecture::cpu_type() { if (_cpu_type == 0) { SYSTEM_INFO si; GetSystemInfo(&si); _cpu_type = si.wProcessorLevel; } return _cpu_type; } BOOL SHArchitecture::init() { if (!_mem->init()) { DPRINTF((TEXT("can't initialize memory manager.\n"))); return FALSE; } // D-RAM information DPRINTF((TEXT("Memory Bank:\n"))); return TRUE; } void SHArchitecture::systemInfo() { // Windows CE common infomation. super::systemInfo(); // CPU specific. _dev->dump(HPC_MENU._cons_parameter); } BOOL SHArchitecture::setupLoader() { vaddr_t v; if (!_mem->getPage(v , _loader_addr)) { DPRINTF((TEXT("can't get page for 2nd loader.\n"))); return FALSE; } _loader_addr = ptokv(_loader_addr); DPRINTF((TEXT("2nd bootloader address U0: 0x%08x P1: 0x%08x\n"), (unsigned)v,(unsigned)_loader_addr)); memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); return TRUE; } void SHArchitecture::jump(paddr_t info, paddr_t pvec) { kaddr_t sp; vaddr_t v; paddr_t p; // stack for bootloader _mem->getPage(v, p); sp = ptokv(p + _mem->getPageSize() / 2); info = ptokv(info); pvec = ptokv(pvec); DPRINTF((TEXT("boot arg: 0x%08x stack: 0x%08x\nBooting kernel...\n"), info, sp)); // Change to privilege-mode. SetKMode(1); // Cache flush(for 2nd bootloader) // // SH4 uses WinCE CacheSync(). this routine may causes TLB // exception. so calls before suspendIntr(). // cache_flush(); // Disable external interrupt. suspendIntr(); // jump to 2nd loader.(run P1) at this time I still use MMU. __asm( "mov r6, r15\n" "jmp @@r7\n" "nop \n", info, pvec, sp, _loader_addr); // NOTREACHED } // disable external interrupt and save its priority. u_int32_t suspendIntr() { u_int32_t sr; __asm( "stc sr, r0\n" "mov.l r0, @@r4\n" "or r5, r0\n" "ldc r0, sr\n", &sr, 0x000000f0); return sr & 0x000000f0; } // resume external interrupt priority. void resumeIntr(u_int32_t s) { __asm( "stc sr, r0\n" "and r5, r0\n" "or r4, r0\n" "ldc r0, sr\n", s, 0xffffff0f); } @ 1.7.2.1 log @Sync w/ -current. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.7 2001/05/08 18:51:25 uch Exp $ */ d4 1 a4 1 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. a38 1 #include a41 1 #include a72 1 a77 1 DPRINTF((TEXT("Memory Bank:\n"))); d97 1 d116 1 a116 1 DPRINTF((TEXT("boot arg: 0x%08x stack: 0x%08x\nBooting kernel...\n"), d122 3 a125 4 // // SH4 uses WinCE CacheSync(). this routine may causes TLB // exception. so calls before suspendIntr(). // a127 3 // Disable external interrupt. suspendIntr(); d129 1 a129 2 __asm( "mov r6, r15\n" d131 1 a131 1 "nop \n", info, pvec, sp, _loader_addr); d140 1 a140 3 __asm( "stc sr, r0\n" a150 1 a160 1 a234 1 a257 1 a307 1 SH_BOOT_FUNC_(7750); a314 1 a337 3 #ifdef SH4 u_int16_t r8; #else a338 1 #endif d347 1 a347 1 r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", @ 1.7.2.2 log @Catch up with -current. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.7.2.1 2002/02/11 20:08:00 jdolecek Exp $ */ d42 29 a70 18 SH_BOOT_FUNC_(7709); SH_BOOT_FUNC_(7709A); SH_BOOT_FUNC_(7750); static int _cpu_type; int SHArchitecture::cpu_type() { if (_cpu_type == 0) { SYSTEM_INFO si; GetSystemInfo(&si); _cpu_type = si.wProcessorLevel; } return _cpu_type; } d73 1 a73 1 SHArchitecture::init() d80 1 a80 1 // D-RAM information d82 2 a87 11 void SHArchitecture::systemInfo() { // Windows CE common infomation. super::systemInfo(); // CPU specific. _dev->dump(HPC_MENU._cons_parameter); } d97 1 a97 3 _loader_addr = ptokv(_loader_addr); DPRINTF((TEXT("2nd bootloader address U0: 0x%08x P1: 0x%08x\n"), d118 1 a118 1 d145 1 a145 1 suspendIntr() d152 1 a152 1 "or r5, r0\n" d162 1 a162 2 __asm( "stc sr, r0\n" d164 1 a164 1 "or r4, r0\n" d167 692 @ 1.6 log @code clean up. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.5 2001/03/25 17:13:17 uch Exp $ */ d94 1 a94 1 (unsigned)v,(unsigned)_loader_addr)); d117 1 a117 1 info, sp)); d130 2 a131 2 "jmp @@r7\n" "nop\n", info, pvec, sp, _loader_addr); d141 3 a143 3 "mov.l r0, @@r4\n" "or r5, r0\n" "ldc r0, sr\n", &sr, 0x000000f0); d152 3 a154 3 "and r5, r0\n" "or r4, r0\n" "ldc r0, sr\n", s, 0xffffff0f); d184 3 a186 3 reg & CCR_RA ? TEXT("RAM") : TEXT("normal"), reg & CCR_WT ? TEXT("Through") : TEXT("Back"), reg & CCR_CB ? TEXT("Back") : TEXT("Through"))); d195 3 a197 3 reg & MMUCR_IX ? TEXT("ASID + VPN") : TEXT("VPN only"), reg & MMUCR_SV ? TEXT("single") : TEXT("multiple"))); d204 1 a204 1 "mov.l r0, @@r4", ®); d261 1 a261 1 (reg_read_2(tab->reg) >> tab->shift) & ICU_IPR_MASK)); d285 2 a286 2 r & ICU_ICR0_NMIL ? "High" : "Low", r & ICU_ICR0_NMIE ? "raising" : "falling")); d290 1 a290 1 r & ICU_ICR1_BLMSK ? "ignored" : "maskable")); d293 1 a293 1 r & ICU_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]")); d296 1 a296 1 r & ICU_ICR1_IRLSEN ? "enabled" : "disabled")); d301 2 a302 2 sense_select [ (r >>(i * 2)) & ICU_SENSE_SELECT_MASK])); d346 4 a349 4 r8 & SCSMR2_CHR ? 7 : 8, r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", r8 & SCSMR2_STOP ? 2 : 1, n)); d353 1 a353 1 32 * bps *(r8 + 1) * n)); d448 1 a448 1 r8 & TOCR_TCOE ? "RTC output" : "input")); d452 3 a454 3 r8 & TSTR_STR0 ? 'x' : '_', r8 & TSTR_STR1 ? 'x' : '_', r8 & TSTR_STR2 ? 'x' : '_')); d469 1 a469 1 paddr_t tcr) d823 3 a825 3 u_int32_t sh7707_fb_dma_addr; u_int16_t val; int s; d827 8 a834 8 s = suspendIntr(); VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR0; val = VOLATILE_REF16(SH7707_LCDDMR_REG16); sh7707_fb_dma_addr = val; VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR1; val = VOLATILE_REF16(SH7707_LCDDMR_REG16); sh7707_fb_dma_addr |= (val << 16); resumeIntr(s); d836 2 a837 2 DPRINTF((TEXT("SH7707 frame buffer dma address: 0x%08x\n"), sh7707_fb_dma_addr)); @ 1.5 log @selectable serial console speed. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.4 2001/03/22 18:27:51 uch Exp $ */ d221 1 a221 1 scif_dump(menu._pref.serial_speed); @ 1.4 log @add HD64461 UART serial console. add SH3 SCI console method add SH3 TMU register dump use generic serial console when companion chip is unknown. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.3 2001/03/02 18:26:38 uch Exp $ */ d221 1 a221 1 scif_dump(19200); @ 1.3 log @rewind progress bar when boot button is pushed. (SH3) if check box on console window is checked, dump system register. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.2 2001/02/21 16:01:54 uch Exp $ */ d44 2 d214 3 d436 67 @ 1.3.2.1 log @Catch up with -current. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.5 2001/03/25 17:13:17 uch Exp $ */ a43 2 static void __tmu_channel_info(int, paddr_t, paddr_t, paddr_t); a211 3 // TMU tmu_dump(); d216 1 a216 1 scif_dump(menu._pref.serial_speed); a430 67 } void SHArchitecture::tmu_dump() { u_int8_t r8; DPRINTF((TEXT("<<>>\n"))); /* Common */ /* TOCR timer output control register */ r8 = reg_read_1(SH3_TOCR_REG8); DPRINTF((TEXT("TCLK = %S\n"), r8 & TOCR_TCOE ? "RTC output" : "input")); /* TSTR */ r8 = reg_read_1(SH3_TSTR_REG8); DPRINTF((TEXT("Timer start(#0:2) [%c][%c][%c]\n"), r8 & TSTR_STR0 ? 'x' : '_', r8 & TSTR_STR1 ? 'x' : '_', r8 & TSTR_STR2 ? 'x' : '_')); #define CHANNEL_DUMP(a, x) \ tmu_channel_dump(x, SH##a##_TCOR##x##_REG, \ SH##a##_TCNT##x##_REG, \ SH##a##_TCR##x##_REG16) CHANNEL_DUMP(3, 0); CHANNEL_DUMP(3, 1); CHANNEL_DUMP(3, 2); #undef CHANNEL_DUMP DPRINTF((TEXT("\n"))); } void SHArchitecture::tmu_channel_dump(int unit, paddr_t tcor, paddr_t tcnt, paddr_t tcr) { u_int32_t r32; u_int16_t r16; DPRINTF((TEXT("TMU#%d:"), unit)); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, TCR_##m, #m) /* TCR*/ r16 = reg_read_2(tcr); DBG_BIT_PRINT(r16, UNF); DBG_BIT_PRINT(r16, UNIE); DBG_BIT_PRINT(r16, CKEG1); DBG_BIT_PRINT(r16, CKEG0); DBG_BIT_PRINT(r16, TPSC2); DBG_BIT_PRINT(r16, TPSC1); DBG_BIT_PRINT(r16, TPSC0); /* channel 2 has input capture. */ if (unit == 2) { DBG_BIT_PRINT(r16, ICPF); DBG_BIT_PRINT(r16, ICPE1); DBG_BIT_PRINT(r16, ICPE0); } #undef DBG_BIT_PRINT /* TCNT0 timer counter */ r32 = reg_read_4(tcnt); DPRINTF((TEXT("\ncnt=0x%08x"), r32)); /* TCOR0 timer constant register */ r32 = reg_read_4(tcor); DPRINTF((TEXT(" constant=0x%04x"), r32)); if (unit == 2) DPRINTF((TEXT(" input capture=0x%08x\n"), SH3_TCPR2_REG)); else DPRINTF((TEXT("\n"))); @ 1.3.2.2 log @Catch up to -current. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.3.2.1 2001/04/09 01:52:46 nathanw Exp $ */ d94 1 a94 1 (unsigned)v,(unsigned)_loader_addr)); d117 1 a117 1 info, sp)); d130 2 a131 2 "jmp @@r7\n" "nop\n", info, pvec, sp, _loader_addr); d141 3 a143 3 "mov.l r0, @@r4\n" "or r5, r0\n" "ldc r0, sr\n", &sr, 0x000000f0); d152 3 a154 3 "and r5, r0\n" "or r4, r0\n" "ldc r0, sr\n", s, 0xffffff0f); d184 3 a186 3 reg & CCR_RA ? TEXT("RAM") : TEXT("normal"), reg & CCR_WT ? TEXT("Through") : TEXT("Back"), reg & CCR_CB ? TEXT("Back") : TEXT("Through"))); d195 3 a197 3 reg & MMUCR_IX ? TEXT("ASID + VPN") : TEXT("VPN only"), reg & MMUCR_SV ? TEXT("single") : TEXT("multiple"))); d204 1 a204 1 "mov.l r0, @@r4", ®); d221 1 a221 1 scif_dump(HPC_PREFERENCE.serial_speed); d261 1 a261 1 (reg_read_2(tab->reg) >> tab->shift) & ICU_IPR_MASK)); d285 2 a286 2 r & ICU_ICR0_NMIL ? "High" : "Low", r & ICU_ICR0_NMIE ? "raising" : "falling")); d290 1 a290 1 r & ICU_ICR1_BLMSK ? "ignored" : "maskable")); d293 1 a293 1 r & ICU_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]")); d296 1 a296 1 r & ICU_ICR1_IRLSEN ? "enabled" : "disabled")); d301 2 a302 2 sense_select [ (r >>(i * 2)) & ICU_SENSE_SELECT_MASK])); d346 4 a349 4 r8 & SCSMR2_CHR ? 7 : 8, r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", r8 & SCSMR2_STOP ? 2 : 1, n)); d353 1 a353 1 32 * bps *(r8 + 1) * n)); d448 1 a448 1 r8 & TOCR_TCOE ? "RTC output" : "input")); d452 3 a454 3 r8 & TSTR_STR0 ? 'x' : '_', r8 & TSTR_STR1 ? 'x' : '_', r8 & TSTR_STR2 ? 'x' : '_')); d469 1 a469 1 paddr_t tcr) d823 3 a825 3 u_int32_t sh7707_fb_dma_addr; u_int16_t val; int s; d827 8 a834 8 s = suspendIntr(); VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR0; val = VOLATILE_REF16(SH7707_LCDDMR_REG16); sh7707_fb_dma_addr = val; VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR1; val = VOLATILE_REF16(SH7707_LCDDMR_REG16); sh7707_fb_dma_addr |= (val << 16); resumeIntr(s); d836 2 a837 2 DPRINTF((TEXT("SH7707 frame buffer dma address: 0x%08x\n"), sh7707_fb_dma_addr)); @ 1.2 log @more diagnostic message. (SH3) add framebuffer information (ARM) fix boot parameter bug. (-b=sd0) @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.1 2001/02/09 18:35:16 uch Exp $ */ d167 1 d171 4 a219 1 HpcMenuInterface &menu = HpcMenuInterface::Instance(); @ 1.1 log @bootloader for SH3, SA-1100, TX39, VR41 based Windows CE(2.00 or later) @ text @d1 1 a1 1 /* $NetBSD$ */ d39 1 d41 1 d200 3 a202 3 // SCIF scif_dump(19200); d207 12 a218 3 #if 0 // Frame Buffer (this test is destructive.) hd64461_framebuffer_test(); #endif d226 1 d229 12 a240 12 DPRINTF((TEXT("ICR0 0x%08x\n"), reg_read16(ICU_ICR0_REG16))); DPRINTF((TEXT("ICR1 0x%08x\n"), reg_read16(ICU_ICR1_REG16))); DPRINTF((TEXT("ICR2 0x%08x\n"), reg_read16(ICU_ICR2_REG16))); DPRINTF((TEXT("PINTER 0x%08x\n"), reg_read16(ICU_PINTER_REG16))); DPRINTF((TEXT("IPRA 0x%08x\n"), reg_read16(ICU_IPRA_REG16))); DPRINTF((TEXT("IPRB 0x%08x\n"), reg_read16(ICU_IPRB_REG16))); DPRINTF((TEXT("IPRC 0x%08x\n"), reg_read16(ICU_IPRC_REG16))); DPRINTF((TEXT("IPRD 0x%08x\n"), reg_read16(ICU_IPRD_REG16))); DPRINTF((TEXT("IPRE 0x%08x\n"), reg_read16(ICU_IPRE_REG16))); DPRINTF((TEXT("IRR0 0x%08x\n"), reg_read8(ICU_IRR0_REG8))); DPRINTF((TEXT("IRR1 0x%08x\n"), reg_read8(ICU_IRR1_REG8))); DPRINTF((TEXT("IRR2 0x%08x\n"), reg_read8(ICU_IRR2_REG8))); d252 1 a252 1 (reg_read16(tab->reg) >> tab->shift) & ICU_IPR_MASK)); d267 1 d270 1 a270 1 bitdisp(reg_read16(ICU_PINTER_REG16)); d272 1 a272 1 bitdisp(reg_read16(ICU_ICR2_REG16)); d274 1 a274 1 r = reg_read16(ICU_ICR0_REG16); d278 1 a278 1 r = reg_read16(ICU_ICR1_REG16); d283 2 a284 3 DPRINTF((TEXT("IRQ[3:0] : %S source\n"), r & ICU_ICR1_IRQLVL ? "IRL 15level" : "dependent IRQ[0:3](IRL disabled)")); d304 22 d332 1 d388 1 a388 1 SHArchitecture::hd64461_framebuffer_test() d390 57 d448 299 a746 1 #if SH7709TEST a761 5 #else u_int8_t *fb = reinterpret_cast(HD64461_FB_ADDR); for (int i = 0; i < 480 * 240 * 2 / 8; i++) *fb++ = 0xff; a762 2 DPRINTF((TEXT("frame buffer test end\n"))); } @ 1.1.2.1 log @file sh_arch.cpp was added on branch thorpej_scsipi on 2001-02-11 19:10:12 +0000 @ text @d1 379 @ 1.1.2.2 log @Sync with HEAD. @ text @a0 379 /* $NetBSD: sh_arch.cpp,v 1.1.2.1 2001/02/11 19:10:12 bouyer Exp $ */ /*- * Copyright (c) 2001 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by UCHIYAMA Yasushi. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the NetBSD * Foundation, Inc. and its contributors. * 4. Neither the name of The NetBSD Foundation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include "scifreg.h" struct SHArchitecture::intr_priority SHArchitecture::ipr_table[] = { { "TMU0", ICU_IPRA_REG16, 12 }, { "TMU1", ICU_IPRA_REG16, 8 }, { "TMU2", ICU_IPRA_REG16, 4 }, { "RTC", ICU_IPRA_REG16, 0 }, { "WDT", ICU_IPRB_REG16, 12 }, { "REF", ICU_IPRB_REG16, 8 }, { "SCI", ICU_IPRB_REG16, 4 }, { "reserve", ICU_IPRB_REG16, 0 }, { "IRQ3", ICU_IPRC_REG16, 12 }, { "IRQ2", ICU_IPRC_REG16, 8 }, { "IRQ1", ICU_IPRC_REG16, 4 }, { "IRQ0", ICU_IPRC_REG16, 0 }, { "PINT0-7", ICU_IPRD_REG16, 12 }, { "PINT8-15", ICU_IPRD_REG16, 8 }, { "IRQ5", ICU_IPRD_REG16, 4 }, { "IRQ4", ICU_IPRD_REG16, 0 }, { "DMAC", ICU_IPRE_REG16, 12 }, { "IrDA", ICU_IPRE_REG16, 8 }, { "SCIF", ICU_IPRE_REG16, 4 }, { "ADC", ICU_IPRE_REG16, 0 }, { 0, 0, 0} /* terminator */ }; BOOL SHArchitecture::init(void) { if (!_mem->init()) { DPRINTF((TEXT("can't initialize memory manager.\n"))); return FALSE; } // set D-RAM information _mem->loadBank(DRAM_BANK0_START, DRAM_BANK_SIZE); _mem->loadBank(DRAM_BANK1_START, DRAM_BANK_SIZE); return TRUE; } BOOL SHArchitecture::setupLoader() { vaddr_t v; if (!_mem->getPage(v , _loader_addr)) { DPRINTF((TEXT("can't get page for 2nd loader.\n"))); return FALSE; } DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"), (unsigned)v,(unsigned)_loader_addr)); memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); DPRINTF((TEXT("2nd bootloader copy done.\n"))); return TRUE; } void SHArchitecture::jump(paddr_t info, paddr_t pvec) { kaddr_t sp; vaddr_t v; paddr_t p; // stack for bootloader _mem->getPage(v, p); sp = ptokv(p + _mem->getPageSize() / 2); info = ptokv(info); pvec = ptokv(pvec); _loader_addr = ptokv(_loader_addr); DPRINTF((TEXT("BootArgs 0x%08x Stack 0x%08x\nBooting kernel...\n"), info, sp)); // Change to privilege-mode. SetKMode(1); // Disable external interrupt. suspendIntr(); // Cache flush(for 2nd bootloader) cache_flush(); // jump to 2nd loader.(run P1) at this time I still use MMU. __asm("mov r6, r15\n" "jmp @@r7\n" "nop\n", info, pvec, sp, _loader_addr); // NOTREACHED } // disable external interrupt and save its priority. u_int32_t suspendIntr(void) { u_int32_t sr; __asm("stc sr, r0\n" "mov.l r0, @@r4\n" "or r5, r0\n" "ldc r0, sr\n", &sr, 0x000000f0); return sr & 0x000000f0; } // resume external interrupt priority. void resumeIntr(u_int32_t s) { __asm("stc sr, r0\n" "and r5, r0\n" "or r4, r0\n" "ldc r0, sr\n", s, 0xffffff0f); } void SHArchitecture::print_stack_pointer(void) { int sp; __asm("mov.l r15, @@r4", &sp); DPRINTF((TEXT("SP 0x%08x\n"), sp)); } void SHArchitecture::systemInfo() { u_int32_t reg; Architecture::systemInfo(); _kmode = SetKMode(1); // Cache reg = VOLATILE_REF(CCR); DPRINTF((TEXT("Cache "))); if (reg & CCR_CE) DPRINTF((TEXT("Enabled. %s-mode, P0/U0/P3 Write-%s, P1 Write-%s\n"), reg & CCR_RA ? TEXT("RAM") : TEXT("normal"), reg & CCR_WT ? TEXT("Through") : TEXT("Back"), reg & CCR_CB ? TEXT("Back") : TEXT("Through"))); else DPRINTF((TEXT("Disabled.\n"))); // MMU reg = VOLATILE_REF(MMUCR); DPRINTF((TEXT("MMU "))); if (reg & MMUCR_AT) DPRINTF((TEXT("Enabled. %s index-mode, %s virtual storage mode\n"), reg & MMUCR_IX ? TEXT("ASID + VPN") : TEXT("VPN only"), reg & MMUCR_SV ? TEXT("single") : TEXT("multiple"))); else DPRINTF((TEXT("Disabled.\n"))); // Status register reg = 0; __asm("stc sr, r0\n" "mov.l r0, @@r4", ®); DPRINTF((TEXT("SR 0x%08x\n"), reg)); // SCIF scif_dump(19200); // ICU print_stack_pointer(); icu_dump(); #if 0 // Frame Buffer (this test is destructive.) hd64461_framebuffer_test(); #endif SetKMode(_kmode); } void SHArchitecture::icu_dump(void) { print_stack_pointer(); DPRINTF((TEXT("ICR0 0x%08x\n"), reg_read16(ICU_ICR0_REG16))); DPRINTF((TEXT("ICR1 0x%08x\n"), reg_read16(ICU_ICR1_REG16))); DPRINTF((TEXT("ICR2 0x%08x\n"), reg_read16(ICU_ICR2_REG16))); DPRINTF((TEXT("PINTER 0x%08x\n"), reg_read16(ICU_PINTER_REG16))); DPRINTF((TEXT("IPRA 0x%08x\n"), reg_read16(ICU_IPRA_REG16))); DPRINTF((TEXT("IPRB 0x%08x\n"), reg_read16(ICU_IPRB_REG16))); DPRINTF((TEXT("IPRC 0x%08x\n"), reg_read16(ICU_IPRC_REG16))); DPRINTF((TEXT("IPRD 0x%08x\n"), reg_read16(ICU_IPRD_REG16))); DPRINTF((TEXT("IPRE 0x%08x\n"), reg_read16(ICU_IPRE_REG16))); DPRINTF((TEXT("IRR0 0x%08x\n"), reg_read8(ICU_IRR0_REG8))); DPRINTF((TEXT("IRR1 0x%08x\n"), reg_read8(ICU_IRR1_REG8))); DPRINTF((TEXT("IRR2 0x%08x\n"), reg_read8(ICU_IRR2_REG8))); icu_control(); icu_priority(); } void SHArchitecture::icu_priority(void) { struct intr_priority *tab; DPRINTF((TEXT("----interrupt priority----\n"))); for (tab = ipr_table; tab->name; tab++) { DPRINTF((TEXT("%-10S %d\n"), tab->name, (reg_read16(tab->reg) >> tab->shift) & ICU_IPR_MASK)); } DPRINTF((TEXT("--------------------------\n"))); } void SHArchitecture::icu_control(void) { const char *sense_select[] = { "falling edge", "raising edge", "low level", "reserved", }; u_int16_t r; // PINT0-15 DPRINTF((TEXT("PINT enable(on |) :"))); bitdisp(reg_read16(ICU_PINTER_REG16)); DPRINTF((TEXT("PINT detect(high |):"))); bitdisp(reg_read16(ICU_ICR2_REG16)); // NMI r = reg_read16(ICU_ICR0_REG16); DPRINTF((TEXT("NMI(%S %S-edge),"), r & ICU_ICR0_NMIL ? "High" : "Low", r & ICU_ICR0_NMIE ? "raising" : "falling")); r = reg_read16(ICU_ICR1_REG16); DPRINTF((TEXT(" %S maskable,"), r & ICU_ICR1_MAI ? "" : "never")); DPRINTF((TEXT(" SR.BL %S\n"), r & ICU_ICR1_BLMSK ? "ignored" : "maskable")); // IRQ0-5 DPRINTF((TEXT("IRQ[3:0] : %S source\n"), r & ICU_ICR1_IRQLVL ? "IRL 15level" : "dependent IRQ[0:3](IRL disabled)")); if (r & ICU_ICR1_IRQLVL) { DPRINTF((TEXT("IRLS[0:3] %S\n"), r & ICU_ICR1_IRLSEN ? "enabled" : "disabled")); } // sense select for (int i = 5; i >= 0; i--) { DPRINTF((TEXT("IRQ[%d] %S\n"), i, sense_select [ (r >>(i * 2)) & ICU_SENSE_SELECT_MASK])); } } SH_BOOT_FUNC_(7709); SH_BOOT_FUNC_(7709A); // // Debug Functions. // void SHArchitecture::scif_dump(int bps) { u_int16_t r16; u_int8_t r8; int n; /* mode */ r8 = SHREG_SCSMR2; n = 1 <<((r8 & SCSMR2_CKS) << 1); DPRINTF((TEXT("mode: %dbit %S-parity %d stop bit clock PCLOCK/%d\n"), r8 & SCSMR2_CHR ? 7 : 8, r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", r8 & SCSMR2_STOP ? 2 : 1, n)); /* bit rate */ r8 = SHREG_SCBRR2; DPRINTF((TEXT("SCBRR=%d(%dbps) estimated PCLOCK %dHz\n"), r8, bps, 32 * bps *(r8 + 1) * n)); /* control */ #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSCR2_##m, #m) DPRINTF((TEXT("SCSCR2: "))); r8 = SHREG_SCSCR2; DBG_BIT_PRINT(r8, TIE); DBG_BIT_PRINT(r8, RIE); DBG_BIT_PRINT(r8, TE); DBG_BIT_PRINT(r8, RE); DPRINTF((TEXT("CKE=%d\n"), r8 & SCSCR2_CKE)); #undef DBG_BIT_PRINT /* status */ #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSSR2_##m, #m) r16 = SHREG_SCSSR2; DPRINTF((TEXT("SCSSR2: "))); DBG_BIT_PRINT(r16, ER); DBG_BIT_PRINT(r16, TEND); DBG_BIT_PRINT(r16, TDFE); DBG_BIT_PRINT(r16, BRK); DBG_BIT_PRINT(r16, FER); DBG_BIT_PRINT(r16, PER); DBG_BIT_PRINT(r16, RDF); DBG_BIT_PRINT(r16, DR); #undef DBG_BIT_PRINT /* FIFO control */ #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCFCR2_##m, #m) r8 = SHREG_SCFCR2; DPRINTF((TEXT("SCFCR2: "))); DBG_BIT_PRINT(r8, RTRG1); DBG_BIT_PRINT(r8, RTRG0); DBG_BIT_PRINT(r8, TTRG1); DBG_BIT_PRINT(r8, TTRG0); DBG_BIT_PRINT(r8, MCE); DBG_BIT_PRINT(r8, TFRST); DBG_BIT_PRINT(r8, RFRST); DBG_BIT_PRINT(r8, LOOP); DPRINTF((TEXT("\n"))); #undef DBG_BIT_PRINT } void SHArchitecture::hd64461_framebuffer_test() { DPRINTF((TEXT("frame buffer test start\n"))); #if SH7709TEST u_int32_t sh7707_fb_dma_addr; u_int16_t val; int s; s = suspendIntr(); VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR0; val = VOLATILE_REF16(SH7707_LCDDMR_REG16); sh7707_fb_dma_addr = val; VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR1; val = VOLATILE_REF16(SH7707_LCDDMR_REG16); sh7707_fb_dma_addr |= (val << 16); resumeIntr(s); DPRINTF((TEXT("SH7707 frame buffer dma address: 0x%08x\n"), sh7707_fb_dma_addr)); #else u_int8_t *fb = reinterpret_cast(HD64461_FB_ADDR); for (int i = 0; i < 480 * 240 * 2 / 8; i++) *fb++ = 0xff; #endif DPRINTF((TEXT("frame buffer test end\n"))); } @ 1.1.2.3 log @Sync with HEAD. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.1.2.2 2001/03/12 13:28:17 bouyer Exp $ */ a38 1 #include a39 1 #include a164 1 HpcMenuInterface &menu = HpcMenuInterface::Instance(); a167 4 // check debug level. if (menu._cons_parameter == 0) return; d198 3 a200 3 // BSC bsc_dump(); d205 3 a207 11 // PFC , I/O port pfc_dump(); // SCIF scif_dump(19200); // HD64461 platid_t platform; platform.dw.dw0 = menu._pref.platid_hi; platform.dw.dw1 = menu._pref.platid_lo; hd64461_dump(platform); a214 1 DPRINTF((TEXT("<<>>\n"))); d217 12 a228 12 DPRINTF((TEXT("ICR0 0x%08x\n"), reg_read_2(ICU_ICR0_REG16))); DPRINTF((TEXT("ICR1 0x%08x\n"), reg_read_2(ICU_ICR1_REG16))); DPRINTF((TEXT("ICR2 0x%08x\n"), reg_read_2(ICU_ICR2_REG16))); DPRINTF((TEXT("PINTER 0x%08x\n"), reg_read_2(ICU_PINTER_REG16))); DPRINTF((TEXT("IPRA 0x%08x\n"), reg_read_2(ICU_IPRA_REG16))); DPRINTF((TEXT("IPRB 0x%08x\n"), reg_read_2(ICU_IPRB_REG16))); DPRINTF((TEXT("IPRC 0x%08x\n"), reg_read_2(ICU_IPRC_REG16))); DPRINTF((TEXT("IPRD 0x%08x\n"), reg_read_2(ICU_IPRD_REG16))); DPRINTF((TEXT("IPRE 0x%08x\n"), reg_read_2(ICU_IPRE_REG16))); DPRINTF((TEXT("IRR0 0x%08x\n"), reg_read_1(ICU_IRR0_REG8))); DPRINTF((TEXT("IRR1 0x%08x\n"), reg_read_1(ICU_IRR1_REG8))); DPRINTF((TEXT("IRR2 0x%08x\n"), reg_read_1(ICU_IRR2_REG8))); d240 1 a240 1 (reg_read_2(tab->reg) >> tab->shift) & ICU_IPR_MASK)); a254 1 d257 1 a257 1 bitdisp(reg_read_2(ICU_PINTER_REG16)); d259 1 a259 1 bitdisp(reg_read_2(ICU_ICR2_REG16)); d261 1 a261 1 r = reg_read_2(ICU_ICR0_REG16); d265 1 a265 1 r = reg_read_2(ICU_ICR1_REG16); d270 3 a272 2 DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"), r & ICU_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]")); a291 22 SHArchitecture::bsc_dump() { DPRINTF((TEXT("<<>>\n"))); #define DUMP_BSC_REG(x) \ DPRINTF((TEXT("%-8S"), #x)); \ bitdisp(reg_read_2(SH3_BSC_##x##_REG)) DUMP_BSC_REG(BCR1); DUMP_BSC_REG(BCR2); DUMP_BSC_REG(WCR1); DUMP_BSC_REG(WCR2); DUMP_BSC_REG(MCR); DUMP_BSC_REG(DCR); DUMP_BSC_REG(PCR); DUMP_BSC_REG(RTCSR); DUMP_BSC_REG(RTCNT); DUMP_BSC_REG(RTCOR); DUMP_BSC_REG(RFCR); DUMP_BSC_REG(BCR3); #undef DUMP_BSC_REG } void a297 1 DPRINTF((TEXT("<<>>\n"))); d353 1 a353 43 SHArchitecture::pfc_dump() { DPRINTF((TEXT("<<>>\n"))); DPRINTF((TEXT("[control]\n"))); #define DUMP_PFC_REG(x) \ DPRINTF((TEXT("P%SCR :"), #x)); \ bitdisp(reg_read_2(SH3_P##x##CR_REG16)) DUMP_PFC_REG(A); DUMP_PFC_REG(B); DUMP_PFC_REG(C); DUMP_PFC_REG(D); DUMP_PFC_REG(E); DUMP_PFC_REG(F); DUMP_PFC_REG(G); DUMP_PFC_REG(H); DUMP_PFC_REG(J); DUMP_PFC_REG(K); DUMP_PFC_REG(L); #undef DUMP_PFC_REG DPRINTF((TEXT("SCPCR :"))); bitdisp(reg_read_2(SH3_SCPCR_REG16)); DPRINTF((TEXT("\n[data]\n"))); #define DUMP_IOPORT_REG(x) \ DPRINTF((TEXT("P%SDR :"), #x)); \ bitdisp(reg_read_1(SH3_P##x##DR_REG8)) DUMP_IOPORT_REG(A); DUMP_IOPORT_REG(B); DUMP_IOPORT_REG(C); DUMP_IOPORT_REG(D); DUMP_IOPORT_REG(E); DUMP_IOPORT_REG(F); DUMP_IOPORT_REG(G); DUMP_IOPORT_REG(H); DUMP_IOPORT_REG(J); DUMP_IOPORT_REG(K); DUMP_IOPORT_REG(L); #undef DUMP_IOPORT_REG DPRINTF((TEXT("SCPDR :"))); bitdisp(reg_read_1(SH3_SCPDR_REG8)); } void SHArchitecture::hd64461_dump(platid_t &platform) a354 15 u_int16_t r16; u_int8_t r8; #define MATCH(p) \ platid_match(&platform, &platid_mask_MACH_##p) DPRINTF((TEXT("<<>>\n"))); if (!MATCH(HP_LX) && !MATCH(HP_JORNADA_6XX) && !MATCH(HITACHI_PERSONA_HPW230JC)) { DPRINTF((TEXT("don't exist."))); return; } #if 0 d356 1 a356 299 u_int8_t *fb = reinterpret_cast(HD64461_FBBASE); for (int i = 0; i < 320 * 240 * 2 / 8; i++) *fb++ = 0xff; DPRINTF((TEXT("frame buffer test end\n"))); #endif // System DPRINTF((TEXT("STBCR (System Control Register)\n"))); r16 = reg_read_2(HD64461_SYSSTBCR_REG16); bitdisp(r16); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m) DBG_BIT_PRINT(r16, CKIO_STBY); DBG_BIT_PRINT(r16, SAFECKE_IST); DBG_BIT_PRINT(r16, SLCKE_IST); DBG_BIT_PRINT(r16, SAFECKE_OST); DBG_BIT_PRINT(r16, SLCKE_OST); DBG_BIT_PRINT(r16, SMIAST); DBG_BIT_PRINT(r16, SLCDST); DBG_BIT_PRINT(r16, SPC0ST); DBG_BIT_PRINT(r16, SPC1ST); DBG_BIT_PRINT(r16, SAFEST); DBG_BIT_PRINT(r16, STM0ST); DBG_BIT_PRINT(r16, STM1ST); DBG_BIT_PRINT(r16, SIRST); DBG_BIT_PRINT(r16, SURTSD); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("SYSCR (System Configuration Register)\n"))); r16 = reg_read_2(HD64461_SYSSYSCR_REG16); bitdisp(r16); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m) DBG_BIT_PRINT(r16, SCPU_BUS_IGAT); DBG_BIT_PRINT(r16, SPTA_IR); DBG_BIT_PRINT(r16, SPTA_TM); DBG_BIT_PRINT(r16, SPTB_UR); DBG_BIT_PRINT(r16, WAIT_CTL_SEL); DBG_BIT_PRINT(r16, SMODE1); DBG_BIT_PRINT(r16, SMODE0); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n"))); r16 = reg_read_2(HD64461_SYSSCPUCR_REG16); bitdisp(r16); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m) DBG_BIT_PRINT(r16, SPDSTOF); DBG_BIT_PRINT(r16, SPDSTIG); DBG_BIT_PRINT(r16, SPCSTOF); DBG_BIT_PRINT(r16, SPCSTIG); DBG_BIT_PRINT(r16, SPBSTOF); DBG_BIT_PRINT(r16, SPBSTIG); DBG_BIT_PRINT(r16, SPASTOF); DBG_BIT_PRINT(r16, SPASTIG); DBG_BIT_PRINT(r16, SLCDSTIG); DBG_BIT_PRINT(r16, SCPU_CS56_EP); DBG_BIT_PRINT(r16, SCPU_CMD_EP); DBG_BIT_PRINT(r16, SCPU_ADDR_EP); DBG_BIT_PRINT(r16, SCPDPU); DBG_BIT_PRINT(r16, SCPU_A2319_EP); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("\n"))); // INTC DPRINTF((TEXT("NIRR (Interrupt Request Register)\n"))); r16 = reg_read_2(HD64461_INTCNIRR_REG16); bitdisp(r16); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIRR_##m, #m) DBG_BIT_PRINT(r16, PCC0R); DBG_BIT_PRINT(r16, PCC1R); DBG_BIT_PRINT(r16, AFER); DBG_BIT_PRINT(r16, GPIOR); DBG_BIT_PRINT(r16, TMU0R); DBG_BIT_PRINT(r16, TMU1R); DBG_BIT_PRINT(r16, IRDAR); DBG_BIT_PRINT(r16, UARTR); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n"))); r16 = reg_read_2(HD64461_INTCNIMR_REG16); bitdisp(r16); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIMR_##m, #m) DBG_BIT_PRINT(r16, PCC0M); DBG_BIT_PRINT(r16, PCC1M); DBG_BIT_PRINT(r16, AFEM); DBG_BIT_PRINT(r16, GPIOM); DBG_BIT_PRINT(r16, TMU0M); DBG_BIT_PRINT(r16, TMU1M); DBG_BIT_PRINT(r16, IRDAM); DBG_BIT_PRINT(r16, UARTM); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("\n"))); // PCMCIA // PCC0 DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n"))); DPRINTF((TEXT("PCC0 Interface Status Register\n"))); r8 = reg_read_1(HD64461_PCC0ISR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) DBG_BIT_PRINT(r8, P0READY); DBG_BIT_PRINT(r8, P0MWP); DBG_BIT_PRINT(r8, P0VS2); DBG_BIT_PRINT(r8, P0VS1); DBG_BIT_PRINT(r8, P0CD2); DBG_BIT_PRINT(r8, P0CD1); DBG_BIT_PRINT(r8, P0BVD2); DBG_BIT_PRINT(r8, P0BVD1); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC0 General Control Register\n"))); r8 = reg_read_1(HD64461_PCC0GCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) DBG_BIT_PRINT(r8, P0DRVE); DBG_BIT_PRINT(r8, P0PCCR); DBG_BIT_PRINT(r8, P0PCCT); DBG_BIT_PRINT(r8, P0VCC0); DBG_BIT_PRINT(r8, P0MMOD); DBG_BIT_PRINT(r8, P0PA25); DBG_BIT_PRINT(r8, P0PA24); DBG_BIT_PRINT(r8, P0REG); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC0 Card Status Change Register\n"))); r8 = reg_read_1(HD64461_PCC0CSCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) DBG_BIT_PRINT(r8, P0SCDI); DBG_BIT_PRINT(r8, P0IREQ); DBG_BIT_PRINT(r8, P0SC); DBG_BIT_PRINT(r8, P0CDC); DBG_BIT_PRINT(r8, P0RC); DBG_BIT_PRINT(r8, P0BW); DBG_BIT_PRINT(r8, P0BD); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n"))); r8 = reg_read_1(HD64461_PCC0CSCIER_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) DBG_BIT_PRINT(r8, P0CRE); DBG_BIT_PRINT(r8, P0SCE); DBG_BIT_PRINT(r8, P0CDE); DBG_BIT_PRINT(r8, P0RE); DBG_BIT_PRINT(r8, P0BWE); DBG_BIT_PRINT(r8, P0BDE); #undef DBG_BIT_PRINT DPRINTF((TEXT("\ninterrupt type: "))); switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { case HD64461_PCC0CSCIER_P0IREQE_NONE: DPRINTF((TEXT("none\n"))); break; case HD64461_PCC0CSCIER_P0IREQE_LEVEL: DPRINTF((TEXT("level\n"))); break; case HD64461_PCC0CSCIER_P0IREQE_FEDGE: DPRINTF((TEXT("falling edge\n"))); break; case HD64461_PCC0CSCIER_P0IREQE_REDGE: DPRINTF((TEXT("rising edge\n"))); break; } DPRINTF((TEXT("PCC0 Software Control Register\n"))); r8 = reg_read_1(HD64461_PCC0SCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) DBG_BIT_PRINT(r8, P0VCC1); DBG_BIT_PRINT(r8, P0SWP); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); // PCC1 DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n"))); DPRINTF((TEXT("PCC1 Interface Status Register\n"))); r8 = reg_read_1(HD64461_PCC1ISR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) DBG_BIT_PRINT(r8, P1READY); DBG_BIT_PRINT(r8, P1MWP); DBG_BIT_PRINT(r8, P1VS2); DBG_BIT_PRINT(r8, P1VS1); DBG_BIT_PRINT(r8, P1CD2); DBG_BIT_PRINT(r8, P1CD1); DBG_BIT_PRINT(r8, P1BVD2); DBG_BIT_PRINT(r8, P1BVD1); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC1 General Contorol Register\n"))); r8 = reg_read_1(HD64461_PCC1GCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) DBG_BIT_PRINT(r8, P1DRVE); DBG_BIT_PRINT(r8, P1PCCR); DBG_BIT_PRINT(r8, P1VCC0); DBG_BIT_PRINT(r8, P1MMOD); DBG_BIT_PRINT(r8, P1PA25); DBG_BIT_PRINT(r8, P1PA24); DBG_BIT_PRINT(r8, P1REG); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC1 Card Status Change Register\n"))); r8 = reg_read_1(HD64461_PCC1CSCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) DBG_BIT_PRINT(r8, P1SCDI); DBG_BIT_PRINT(r8, P1CDC); DBG_BIT_PRINT(r8, P1RC); DBG_BIT_PRINT(r8, P1BW); DBG_BIT_PRINT(r8, P1BD); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n"))); r8 = reg_read_1(HD64461_PCC1CSCIER_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) DBG_BIT_PRINT(r8, P1CRE); DBG_BIT_PRINT(r8, P1CDE); DBG_BIT_PRINT(r8, P1RE); DBG_BIT_PRINT(r8, P1BWE); DBG_BIT_PRINT(r8, P1BDE); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC1 Software Control Register\n"))); r8 = reg_read_1(HD64461_PCC1SCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) DBG_BIT_PRINT(r8, P1VCC1); DBG_BIT_PRINT(r8, P1SWP); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); // General Control DPRINTF((TEXT("[General Control]\n"))); DPRINTF((TEXT("PCC0 Output pins Control Register\n"))); r8 = reg_read_1(HD64461_PCCP0OCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) DBG_BIT_PRINT(r8, P0DEPLUP); DBG_BIT_PRINT(r8, P0AEPLUP); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PCC1 Output pins Control Register\n"))); r8 = reg_read_1(HD64461_PCCP1OCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) DBG_BIT_PRINT(r8, P1RST8MA); DBG_BIT_PRINT(r8, P1RST4MA); DBG_BIT_PRINT(r8, P1RAS8MA); DBG_BIT_PRINT(r8, P1RAS4MA); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); DPRINTF((TEXT("PC Card General Control Register\n"))); r8 = reg_read_1(HD64461_PCCPGCR_REG8); bitdisp(r8); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) DBG_BIT_PRINT(r8, PSSDIR); DBG_BIT_PRINT(r8, PSSRDWR); #undef DBG_BIT_PRINT DPRINTF((TEXT("\n"))); // GPIO #define GPIO_DUMP_REG8(x) \ bitdisp(reg_read_1(HD64461_GPA##x##R_REG16)); \ bitdisp(reg_read_1(HD64461_GPB##x##R_REG16)); \ bitdisp(reg_read_1(HD64461_GPC##x##R_REG16)); \ bitdisp(reg_read_1(HD64461_GPD##x##R_REG16)) #define GPIO_DUMP_REG16(x) \ bitdisp(reg_read_2(HD64461_GPA##x##R_REG16)); \ bitdisp(reg_read_2(HD64461_GPB##x##R_REG16)); \ bitdisp(reg_read_2(HD64461_GPC##x##R_REG16)); \ bitdisp(reg_read_2(HD64461_GPD##x##R_REG16)) DPRINTF((TEXT("GPIO Port Control Register\n"))); GPIO_DUMP_REG16(C); DPRINTF((TEXT("GPIO Port Data Register\n"))); GPIO_DUMP_REG8(D); DPRINTF((TEXT("GPIO Port Interrupt Control Register\n"))); GPIO_DUMP_REG8(IC); DPRINTF((TEXT("GPIO Port Interrupt Status Register\n"))); GPIO_DUMP_REG8(IS); } #ifdef SH7709TEST d372 5 d378 2 @ 1.1.2.4 log @Sync with HEAD. @ text @d1 1 a1 1 /* $NetBSD: sh_arch.cpp,v 1.1.2.3 2001/03/27 15:30:49 bouyer Exp $ */ a43 2 static void __tmu_channel_info(int, paddr_t, paddr_t, paddr_t); a211 3 // TMU tmu_dump(); d216 1 a216 1 scif_dump(menu._pref.serial_speed); a433 67 SHArchitecture::tmu_dump() { u_int8_t r8; DPRINTF((TEXT("<<>>\n"))); /* Common */ /* TOCR timer output control register */ r8 = reg_read_1(SH3_TOCR_REG8); DPRINTF((TEXT("TCLK = %S\n"), r8 & TOCR_TCOE ? "RTC output" : "input")); /* TSTR */ r8 = reg_read_1(SH3_TSTR_REG8); DPRINTF((TEXT("Timer start(#0:2) [%c][%c][%c]\n"), r8 & TSTR_STR0 ? 'x' : '_', r8 & TSTR_STR1 ? 'x' : '_', r8 & TSTR_STR2 ? 'x' : '_')); #define CHANNEL_DUMP(a, x) \ tmu_channel_dump(x, SH##a##_TCOR##x##_REG, \ SH##a##_TCNT##x##_REG, \ SH##a##_TCR##x##_REG16) CHANNEL_DUMP(3, 0); CHANNEL_DUMP(3, 1); CHANNEL_DUMP(3, 2); #undef CHANNEL_DUMP DPRINTF((TEXT("\n"))); } void SHArchitecture::tmu_channel_dump(int unit, paddr_t tcor, paddr_t tcnt, paddr_t tcr) { u_int32_t r32; u_int16_t r16; DPRINTF((TEXT("TMU#%d:"), unit)); #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, TCR_##m, #m) /* TCR*/ r16 = reg_read_2(tcr); DBG_BIT_PRINT(r16, UNF); DBG_BIT_PRINT(r16, UNIE); DBG_BIT_PRINT(r16, CKEG1); DBG_BIT_PRINT(r16, CKEG0); DBG_BIT_PRINT(r16, TPSC2); DBG_BIT_PRINT(r16, TPSC1); DBG_BIT_PRINT(r16, TPSC0); /* channel 2 has input capture. */ if (unit == 2) { DBG_BIT_PRINT(r16, ICPF); DBG_BIT_PRINT(r16, ICPE1); DBG_BIT_PRINT(r16, ICPE0); } #undef DBG_BIT_PRINT /* TCNT0 timer counter */ r32 = reg_read_4(tcnt); DPRINTF((TEXT("\ncnt=0x%08x"), r32)); /* TCOR0 timer constant register */ r32 = reg_read_4(tcor); DPRINTF((TEXT(" constant=0x%04x"), r32)); if (unit == 2) DPRINTF((TEXT(" input capture=0x%08x\n"), SH3_TCPR2_REG)); else DPRINTF((TEXT("\n"))); } void @