head 1.9; access; symbols netbsd-11-0-RC4:1.9 netbsd-11-0-RC3:1.9 netbsd-11-0-RC2:1.9 netbsd-11-0-RC1:1.9 perseant-exfatfs-base-20250801:1.9 netbsd-11:1.9.0.98 netbsd-11-base:1.9 netbsd-10-1-RELEASE:1.9 perseant-exfatfs-base-20240630:1.9 perseant-exfatfs:1.9.0.96 perseant-exfatfs-base:1.9 netbsd-8-3-RELEASE:1.9 netbsd-9-4-RELEASE:1.9 netbsd-10-0-RELEASE:1.9 netbsd-10-0-RC6:1.9 netbsd-10-0-RC5:1.9 netbsd-10-0-RC4:1.9 netbsd-10-0-RC3:1.9 netbsd-10-0-RC2:1.9 thorpej-ifq:1.9.0.94 thorpej-ifq-base:1.9 thorpej-altq-separation:1.9.0.92 thorpej-altq-separation-base:1.9 netbsd-10-0-RC1:1.9 netbsd-10:1.9.0.90 netbsd-10-base:1.9 bouyer-sunxi-drm:1.9.0.88 bouyer-sunxi-drm-base:1.9 netbsd-9-3-RELEASE:1.9 thorpej-i2c-spi-conf2:1.9.0.86 thorpej-i2c-spi-conf2-base:1.9 thorpej-futex2:1.9.0.84 thorpej-futex2-base:1.9 thorpej-cfargs2:1.9.0.82 thorpej-cfargs2-base:1.9 cjep_sun2x-base1:1.9 cjep_sun2x:1.9.0.80 cjep_sun2x-base:1.9 cjep_staticlib_x-base1:1.9 netbsd-9-2-RELEASE:1.9 cjep_staticlib_x:1.9.0.78 cjep_staticlib_x-base:1.9 thorpej-i2c-spi-conf:1.9.0.76 thorpej-i2c-spi-conf-base:1.9 thorpej-cfargs:1.9.0.74 thorpej-cfargs-base:1.9 thorpej-futex:1.9.0.72 thorpej-futex-base:1.9 netbsd-9-1-RELEASE:1.9 bouyer-xenpvh-base2:1.9 phil-wifi-20200421:1.9 bouyer-xenpvh-base1:1.9 phil-wifi-20200411:1.9 bouyer-xenpvh:1.9.0.70 bouyer-xenpvh-base:1.9 is-mlppp:1.9.0.68 is-mlppp-base:1.9 phil-wifi-20200406:1.9 netbsd-8-2-RELEASE:1.9 ad-namecache-base3:1.9 netbsd-9-0-RELEASE:1.9 netbsd-9-0-RC2:1.9 ad-namecache-base2:1.9 ad-namecache-base1:1.9 ad-namecache:1.9.0.66 ad-namecache-base:1.9 netbsd-9-0-RC1:1.9 phil-wifi-20191119:1.9 netbsd-9:1.9.0.64 netbsd-9-base:1.9 phil-wifi-20190609:1.9 netbsd-8-1-RELEASE:1.9 netbsd-8-1-RC1:1.9 isaki-audio2:1.9.0.62 isaki-audio2-base:1.9 pgoyette-compat-merge-20190127:1.9 pgoyette-compat-20190127:1.9 pgoyette-compat-20190118:1.9 pgoyette-compat-1226:1.9 pgoyette-compat-1126:1.9 pgoyette-compat-1020:1.9 pgoyette-compat-0930:1.9 pgoyette-compat-0906:1.9 netbsd-7-2-RELEASE:1.9 pgoyette-compat-0728:1.9 netbsd-8-0-RELEASE:1.9 phil-wifi:1.9.0.60 phil-wifi-base:1.9 pgoyette-compat-0625:1.9 netbsd-8-0-RC2:1.9 pgoyette-compat-0521:1.9 pgoyette-compat-0502:1.9 pgoyette-compat-0422:1.9 netbsd-8-0-RC1:1.9 pgoyette-compat-0415:1.9 pgoyette-compat-0407:1.9 pgoyette-compat-0330:1.9 pgoyette-compat-0322:1.9 pgoyette-compat-0315:1.9 netbsd-7-1-2-RELEASE:1.9 pgoyette-compat:1.9.0.58 pgoyette-compat-base:1.9 netbsd-7-1-1-RELEASE:1.9 tls-maxphys-base-20171202:1.9 matt-nb8-mediatek:1.9.0.56 matt-nb8-mediatek-base:1.9 nick-nhusb-base-20170825:1.9 perseant-stdc-iso10646:1.9.0.54 perseant-stdc-iso10646-base:1.9 netbsd-8:1.9.0.52 netbsd-8-base:1.9 prg-localcount2-base3:1.9 prg-localcount2-base2:1.9 prg-localcount2-base1:1.9 prg-localcount2:1.9.0.50 prg-localcount2-base:1.9 pgoyette-localcount-20170426:1.9 bouyer-socketcan-base1:1.9 jdolecek-ncq:1.9.0.48 jdolecek-ncq-base:1.9 pgoyette-localcount-20170320:1.9 netbsd-7-1:1.9.0.46 netbsd-7-1-RELEASE:1.9 netbsd-7-1-RC2:1.9 nick-nhusb-base-20170204:1.9 netbsd-7-nhusb-base-20170116:1.9 bouyer-socketcan:1.9.0.44 bouyer-socketcan-base:1.9 pgoyette-localcount-20170107:1.9 netbsd-7-1-RC1:1.9 nick-nhusb-base-20161204:1.9 pgoyette-localcount-20161104:1.9 netbsd-7-0-2-RELEASE:1.9 nick-nhusb-base-20161004:1.9 localcount-20160914:1.9 netbsd-7-nhusb:1.9.0.42 netbsd-7-nhusb-base:1.9 pgoyette-localcount-20160806:1.9 pgoyette-localcount-20160726:1.9 pgoyette-localcount:1.9.0.40 pgoyette-localcount-base:1.9 nick-nhusb-base-20160907:1.9 nick-nhusb-base-20160529:1.9 netbsd-7-0-1-RELEASE:1.9 nick-nhusb-base-20160422:1.9 nick-nhusb-base-20160319:1.9 nick-nhusb-base-20151226:1.9 netbsd-7-0:1.9.0.38 netbsd-7-0-RELEASE:1.9 nick-nhusb-base-20150921:1.9 netbsd-7-0-RC3:1.9 netbsd-7-0-RC2:1.9 netbsd-7-0-RC1:1.9 nick-nhusb-base-20150606:1.9 nick-nhusb-base-20150406:1.9 nick-nhusb:1.9.0.36 nick-nhusb-base:1.9 netbsd-5-2-3-RELEASE:1.8 netbsd-5-1-5-RELEASE:1.8 netbsd-6-0-6-RELEASE:1.9 netbsd-6-1-5-RELEASE:1.9 netbsd-7:1.9.0.34 netbsd-7-base:1.9 yamt-pagecache-base9:1.9 yamt-pagecache-tag8:1.9 netbsd-6-1-4-RELEASE:1.9 netbsd-6-0-5-RELEASE:1.9 tls-earlyentropy:1.9.0.32 tls-earlyentropy-base:1.9 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.9 riastradh-drm2-base3:1.9 netbsd-6-1-3-RELEASE:1.9 netbsd-6-0-4-RELEASE:1.9 netbsd-5-2-2-RELEASE:1.8 netbsd-5-1-4-RELEASE:1.8 netbsd-6-1-2-RELEASE:1.9 netbsd-6-0-3-RELEASE:1.9 netbsd-5-2-1-RELEASE:1.8 netbsd-5-1-3-RELEASE:1.8 rmind-smpnet-nbase:1.9 netbsd-6-1-1-RELEASE:1.9 riastradh-drm2-base2:1.9 riastradh-drm2-base1:1.9 riastradh-drm2:1.9.0.30 riastradh-drm2-base:1.9 rmind-smpnet:1.9.0.22 rmind-smpnet-base:1.9 netbsd-6-1:1.9.0.28 netbsd-6-0-2-RELEASE:1.9 netbsd-6-1-RELEASE:1.9 khorben-n900:1.9.0.26 netbsd-6-1-RC4:1.9 netbsd-6-1-RC3:1.9 agc-symver:1.9.0.24 agc-symver-base:1.9 netbsd-6-1-RC2:1.9 netbsd-6-1-RC1:1.9 yamt-pagecache-base8:1.9 netbsd-5-2:1.8.0.28 netbsd-6-0-1-RELEASE:1.9 yamt-pagecache-base7:1.9 netbsd-5-2-RELEASE:1.8 netbsd-5-2-RC1:1.8 matt-nb6-plus-nbase:1.9 yamt-pagecache-base6:1.9 netbsd-6-0:1.9.0.20 netbsd-6-0-RELEASE:1.9 netbsd-6-0-RC2:1.9 tls-maxphys:1.9.0.18 tls-maxphys-base:1.9 matt-nb6-plus:1.9.0.16 matt-nb6-plus-base:1.9 netbsd-6-0-RC1:1.9 jmcneill-usbmp-base10:1.9 yamt-pagecache-base5:1.9 jmcneill-usbmp-base9:1.9 yamt-pagecache-base4:1.9 jmcneill-usbmp-base8:1.9 jmcneill-usbmp-base7:1.9 jmcneill-usbmp-base6:1.9 jmcneill-usbmp-base5:1.9 jmcneill-usbmp-base4:1.9 jmcneill-usbmp-base3:1.9 jmcneill-usbmp-pre-base2:1.9 jmcneill-usbmp-base2:1.9 netbsd-6:1.9.0.14 netbsd-6-base:1.9 netbsd-5-1-2-RELEASE:1.8 netbsd-5-1-1-RELEASE:1.8 jmcneill-usbmp:1.9.0.12 jmcneill-usbmp-base:1.9 jmcneill-audiomp3:1.9.0.10 jmcneill-audiomp3-base:1.9 yamt-pagecache-base3:1.9 yamt-pagecache-base2:1.9 yamt-pagecache:1.9.0.8 yamt-pagecache-base:1.9 rmind-uvmplock-nbase:1.9 cherry-xenmp:1.9.0.6 cherry-xenmp-base:1.9 jym-xensuspend-nbase:1.9 uebayasi-xip-base7:1.9 bouyer-quota2-nbase:1.9 bouyer-quota2:1.9.0.4 bouyer-quota2-base:1.9 jruoho-x86intr:1.9.0.2 jruoho-x86intr-base:1.9 matt-mips64-premerge-20101231:1.9 matt-nb5-mips64-premerge-20101231:1.8 matt-nb5-pq3:1.8.0.26 matt-nb5-pq3-base:1.8 netbsd-5-1:1.8.0.24 uebayasi-xip-base6:1.9 uebayasi-xip-base5:1.9 netbsd-5-1-RELEASE:1.8 uebayasi-xip-base4:1.9 uebayasi-xip-base3:1.9 yamt-nfs-mp-base11:1.9 netbsd-5-1-RC4:1.8 matt-nb5-mips64-k15:1.8 uebayasi-xip-base2:1.9 yamt-nfs-mp-base10:1.9 netbsd-5-1-RC3:1.8 netbsd-5-1-RC2:1.8 uebayasi-xip-base1:1.9 netbsd-5-1-RC1:1.8 rmind-uvmplock:1.8.0.22 rmind-uvmplock-base:1.9 yamt-nfs-mp-base9:1.8 uebayasi-xip:1.8.0.20 uebayasi-xip-base:1.8 netbsd-5-0-2-RELEASE:1.8 matt-nb5-mips64-premerge-20091211:1.8 matt-premerge-20091211:1.8 yamt-nfs-mp-base8:1.8 matt-nb5-mips64-u2-k2-k4-k7-k8-k9:1.8 matt-nb4-mips64-k7-u2a-k9b:1.8 matt-nb5-mips64-u1-k1-k5:1.8 yamt-nfs-mp-base7:1.8 matt-nb5-mips64:1.8.0.18 netbsd-5-0-1-RELEASE:1.8 jymxensuspend-base:1.8 yamt-nfs-mp-base6:1.8 yamt-nfs-mp-base5:1.8 yamt-nfs-mp-base4:1.8 yamt-nfs-mp-base3:1.8 nick-hppapmap-base4:1.8 nick-hppapmap-base3:1.8 netbsd-5-0:1.8.0.16 netbsd-5-0-RELEASE:1.8 netbsd-5-0-RC4:1.8 netbsd-5-0-RC3:1.8 nick-hppapmap-base2:1.8 netbsd-5-0-RC2:1.8 jym-xensuspend:1.8.0.14 jym-xensuspend-base:1.9 netbsd-5-0-RC1:1.8 haad-dm-base2:1.8 haad-nbase2:1.8 ad-audiomp2:1.8.0.12 ad-audiomp2-base:1.8 netbsd-5:1.8.0.10 netbsd-5-base:1.8 nick-hppapmap:1.8.0.8 nick-hppapmap-base:1.8 matt-mips64-base2:1.8 haad-dm-base1:1.8 wrstuden-revivesa-base-4:1.8 netbsd-4-0-1-RELEASE:1.6 wrstuden-revivesa-base-3:1.8 wrstuden-revivesa-base-2:1.8 wrstuden-fixsa-newbase:1.6 nick-csl-alignment-base5:1.6 haad-dm:1.8.0.6 haad-dm-base:1.8 wrstuden-revivesa-base-1:1.8 simonb-wapbl-nbase:1.8 yamt-pf42-base4:1.8 simonb-wapbl:1.8.0.4 simonb-wapbl-base:1.8 yamt-pf42-base3:1.8 hpcarm-cleanup-nbase:1.8 yamt-pf42-baseX:1.7 yamt-pf42-base2:1.8 yamt-nfs-mp-base2:1.8 wrstuden-revivesa:1.8.0.2 wrstuden-revivesa-base:1.8 yamt-nfs-mp:1.7.0.4 yamt-nfs-mp-base:1.7 yamt-pf42:1.7.0.2 yamt-pf42-base:1.7 ad-socklock-base1:1.7 yamt-lazymbuf-base15:1.7 yamt-lazymbuf-base14:1.7 keiichi-mipv6-nbase:1.7 mjf-devfs2:1.6.0.68 mjf-devfs2-base:1.8 nick-net80211-sync:1.6.0.66 nick-net80211-sync-base:1.6 keiichi-mipv6:1.6.0.64 keiichi-mipv6-base:1.7 bouyer-xeni386-merge1:1.6 matt-armv6-prevmlocking:1.6 wrstuden-fixsa-base-1:1.6 vmlocking2-base3:1.6 netbsd-4-0:1.6.0.62 netbsd-4-0-RELEASE:1.6 bouyer-xeni386-nbase:1.6 yamt-kmem-base3:1.6 cube-autoconf:1.6.0.60 cube-autoconf-base:1.6 yamt-kmem-base2:1.6 bouyer-xeni386:1.6.0.58 bouyer-xeni386-base:1.6 yamt-kmem:1.6.0.56 yamt-kmem-base:1.6 vmlocking2-base2:1.6 reinoud-bufcleanup-nbase:1.6 vmlocking2:1.6.0.54 vmlocking2-base1:1.6 netbsd-4-0-RC5:1.6 matt-nb4-arm:1.6.0.52 matt-nb4-arm-base:1.6 matt-armv6-nbase:1.7 jmcneill-base:1.6 netbsd-4-0-RC4:1.6 mjf-devfs:1.6.0.50 mjf-devfs-base:1.6 bouyer-xenamd64-base2:1.6 vmlocking-nbase:1.6 yamt-x86pmap-base4:1.6 bouyer-xenamd64:1.6.0.48 bouyer-xenamd64-base:1.6 netbsd-4-0-RC3:1.6 yamt-x86pmap-base3:1.6 yamt-x86pmap-base2:1.6 netbsd-4-0-RC2:1.6 yamt-x86pmap:1.6.0.46 yamt-x86pmap-base:1.6 netbsd-4-0-RC1:1.6 matt-armv6:1.6.0.44 matt-armv6-base:1.6 jmcneill-pm:1.6.0.42 jmcneill-pm-base:1.6 hpcarm-cleanup:1.6.0.40 hpcarm-cleanup-base:1.6 nick-csl-alignment:1.6.0.38 nick-csl-alignment-base:1.6 matt-mips64:1.6.0.36 matt-mips64-base:1.6 netbsd-3-1-1-RELEASE:1.4 netbsd-3-0-3-RELEASE:1.4 yamt-idlelwp-base8:1.6 wrstuden-fixsa:1.6.0.34 wrstuden-fixsa-base:1.6 ppcoea-renovation:1.6.0.32 ppcoea-renovation-base:1.6 thorpej-atomic:1.6.0.30 thorpej-atomic-base:1.6 reinoud-bufcleanup:1.6.0.28 reinoud-bufcleanup-base:1.6 mjf-ufs-trans:1.6.0.26 mjf-ufs-trans-base:1.6 vmlocking:1.6.0.24 vmlocking-base:1.6 ad-audiomp:1.6.0.22 ad-audiomp-base:1.6 yamt-idlelwp:1.6.0.20 post-newlock2-merge:1.6 newlock2-nbase:1.6 yamt-splraiseipl-base5:1.6 yamt-splraiseipl-base4:1.6 yamt-splraiseipl-base3:1.6 abandoned-netbsd-4-base:1.6 abandoned-netbsd-4:1.6.0.12 netbsd-3-1:1.4.0.22 netbsd-3-1-RELEASE:1.4 netbsd-3-0-2-RELEASE:1.4 yamt-splraiseipl-base2:1.6 netbsd-3-1-RC4:1.4 yamt-splraiseipl:1.6.0.16 yamt-splraiseipl-base:1.6 netbsd-3-1-RC3:1.4 yamt-pdpolicy-base9:1.6 newlock2:1.6.0.14 newlock2-base:1.6 yamt-pdpolicy-base8:1.6 netbsd-3-1-RC2:1.4 netbsd-3-1-RC1:1.4 yamt-pdpolicy-base7:1.6 netbsd-4:1.6.0.18 netbsd-4-base:1.6 yamt-pdpolicy-base6:1.6 chap-midi-nbase:1.6 netbsd-3-0-1-RELEASE:1.4 gdamore-uart:1.6.0.10 gdamore-uart-base:1.6 simonb-timcounters-final:1.5.6.1 yamt-pdpolicy-base5:1.6 chap-midi:1.6.0.8 chap-midi-base:1.6 yamt-pdpolicy-base4:1.6 yamt-pdpolicy-base3:1.6 peter-altq-base:1.6 peter-altq:1.6.0.6 yamt-pdpolicy-base2:1.6 elad-kernelauth-base:1.6 elad-kernelauth:1.6.0.4 yamt-pdpolicy:1.6.0.2 yamt-pdpolicy-base:1.6 yamt-uio_vmspace-base5:1.5 simonb-timecounters:1.5.0.6 simonb-timecounters-base:1.6 rpaulo-netinet-merge-pcb:1.5.0.4 rpaulo-netinet-merge-pcb-base:1.6 yamt-uio_vmspace:1.5.0.2 netbsd-3-0:1.4.0.20 netbsd-3-0-RELEASE:1.4 netbsd-3-0-RC6:1.4 yamt-readahead-base3:1.4 netbsd-3-0-RC5:1.4 netbsd-3-0-RC4:1.4 netbsd-3-0-RC3:1.4 yamt-readahead-base2:1.4 netbsd-3-0-RC2:1.4 yamt-readahead-pervnode:1.4 yamt-readahead-perfile:1.4 yamt-readahead:1.4.0.18 yamt-readahead-base:1.4 netbsd-3-0-RC1:1.4 yamt-vop-base3:1.4 netbsd-2-0-3-RELEASE:1.3 netbsd-2-1:1.3.0.28 yamt-vop-base2:1.4 thorpej-vnode-attr:1.4.0.16 thorpej-vnode-attr-base:1.4 netbsd-2-1-RELEASE:1.3 yamt-vop:1.4.0.14 yamt-vop-base:1.4 netbsd-2-1-RC6:1.3 netbsd-2-1-RC5:1.3 netbsd-2-1-RC4:1.3 netbsd-2-1-RC3:1.3 netbsd-2-1-RC2:1.3 netbsd-2-1-RC1:1.3 yamt-lazymbuf:1.4.0.12 yamt-km-base4:1.4 netbsd-2-0-2-RELEASE:1.3 yamt-km-base3:1.4 netbsd-3:1.4.0.10 netbsd-3-base:1.4 yamt-km-base2:1.4 yamt-km:1.4.0.6 yamt-km-base:1.4 kent-audio2:1.4.0.4 kent-audio2-base:1.4 netbsd-2-0-1-RELEASE:1.3 kent-audio1-beforemerge:1.4 netbsd-2:1.3.0.26 netbsd-2-base:1.3 kent-audio1:1.4.0.2 kent-audio1-base:1.4 netbsd-2-0-RELEASE:1.3 netbsd-2-0-RC5:1.3 netbsd-2-0-RC4:1.3 netbsd-2-0-RC3:1.3 netbsd-2-0-RC2:1.3 netbsd-2-0-RC1:1.3 netbsd-2-0:1.3.0.24 netbsd-2-0-base:1.3 netbsd-1-6-PATCH002-RELEASE:1.3 netbsd-1-6-PATCH002:1.3 netbsd-1-6-PATCH002-RC4:1.3 netbsd-1-6-PATCH002-RC3:1.3 netbsd-1-6-PATCH002-RC2:1.3 netbsd-1-6-PATCH002-RC1:1.3 ktrace-lwp:1.3.0.22 ktrace-lwp-base:1.4 netbsd-1-6-PATCH001:1.3 netbsd-1-6-PATCH001-RELEASE:1.3 netbsd-1-6-PATCH001-RC3:1.3 netbsd-1-6-PATCH001-RC2:1.3 netbsd-1-6-PATCH001-RC1:1.3 nathanw_sa_end:1.3 nathanw_sa_before_merge:1.3 fvdl_fs64_base:1.3 gmcgarry_ctxsw:1.3.0.20 gmcgarry_ctxsw_base:1.3 gmcgarry_ucred:1.3.0.18 gmcgarry_ucred_base:1.3 nathanw_sa_base:1.3 kqueue-aftermerge:1.3 kqueue-beforemerge:1.3 netbsd-1-6-RELEASE:1.3 netbsd-1-6-RC3:1.3 netbsd-1-6-RC2:1.3 netbsd-1-6-RC1:1.3 netbsd-1-6:1.3.0.16 netbsd-1-6-base:1.3 gehenna-devsw:1.3.0.14 gehenna-devsw-base:1.3 eeh-devprop:1.3.0.12 eeh-devprop-base:1.3 newlock:1.3.0.10 newlock-base:1.3 ifpoll-base:1.3 nathanw_sa:1.3.0.6 thorpej-mips-cache:1.3.0.4 thorpej-mips-cache-base:1.3 thorpej-devvp-base3:1.3 thorpej-devvp-base2:1.3 post-chs-ubcperf:1.3 pre-chs-ubcperf:1.3 thorpej-devvp:1.3.0.2 thorpej-devvp-base:1.3 kqueue:1.2.0.2 kqueue-base:1.3 thorpej_scsipi_beforemerge:1.2 thorpej_scsipi_base:1.2 thorpej_scsipi:1.1.0.2 thorpej_scsipi_nbase:1.2; locks; strict; comment @;; @; 1.9 date 2010.04.06.16.20.28; author nonaka; state Exp; branches; next 1.8; 1.8 date 2008.05.03.23.49.14; author martin; state Exp; branches 1.8.20.1 1.8.22.1; next 1.7; 1.7 date 2008.03.08.01.50.06; author rafal; state Exp; branches 1.7.2.1 1.7.4.1; next 1.6; 1.6 date 2006.03.05.04.05.39; author uwe; state Exp; branches 1.6.2.1 1.6.44.1 1.6.64.1 1.6.68.1; next 1.5; 1.5 date 2005.12.11.12.17.28; author christos; state Exp; branches 1.5.4.1 1.5.6.1; next 1.4; 1.4 date 2004.08.06.18.33.09; author uch; state Exp; branches 1.4.12.1; next 1.3; 1.3 date 2001.07.17.01.43.42; author toshii; state Exp; branches 1.3.6.1 1.3.22.1; next 1.2; 1.2 date 2001.03.23.08.48.12; author toshii; state Exp; branches 1.2.2.1; next 1.1; 1.1 date 2001.02.09.18.34.49; author uch; state Exp; branches 1.1.2.1 1.1.4.1; next ; 1.8.20.1 date 2010.04.30.14.39.24; author uebayasi; state Exp; branches; next ; 1.8.22.1 date 2010.05.30.05.16.50; author rmind; state Exp; branches; next ; 1.7.2.1 date 2008.05.18.12.32.01; author yamt; state Exp; branches; next ; 1.7.4.1 date 2008.05.16.02.22.24; author yamt; state Exp; branches; next 1.7.4.2; 1.7.4.2 date 2010.08.11.22.52.03; author yamt; state Exp; branches; next ; 1.6.2.1 date 2006.03.05.04.05.39; author uwe; state dead; branches; next 1.6.2.2; 1.6.2.2 date 2006.03.05.04.05.40; author uwe; state Exp; branches; next ; 1.6.44.1 date 2008.03.23.02.04.03; author matt; state Exp; branches; next ; 1.6.64.1 date 2008.03.24.07.14.57; author keiichi; state Exp; branches; next ; 1.6.68.1 date 2008.04.03.12.42.16; author mjf; state Exp; branches; next 1.6.68.2; 1.6.68.2 date 2008.06.02.13.22.08; author mjf; state Exp; branches; next ; 1.5.4.1 date 2006.09.09.02.39.37; author rpaulo; state Exp; branches; next ; 1.5.6.1 date 2006.04.22.11.37.28; author simonb; state Exp; branches; next ; 1.4.12.1 date 2006.06.21.14.51.38; author yamt; state Exp; branches; next 1.4.12.2; 1.4.12.2 date 2008.03.17.09.14.17; author yamt; state Exp; branches; next ; 1.3.6.1 date 2001.07.17.01.43.42; author toshii; state dead; branches; next 1.3.6.2; 1.3.6.2 date 2001.07.17.01.43.43; author toshii; state Exp; branches; next ; 1.3.22.1 date 2004.08.12.11.41.05; author skrll; state Exp; branches; next 1.3.22.2; 1.3.22.2 date 2004.09.18.14.34.39; author skrll; state Exp; branches; next 1.3.22.3; 1.3.22.3 date 2004.09.21.13.15.53; author skrll; state Exp; branches; next ; 1.2.2.1 date 2001.08.03.04.11.31; author lukem; state Exp; branches; next ; 1.1.2.1 date 2001.02.09.18.34.49; author bouyer; state dead; branches; next 1.1.2.2; 1.1.2.2 date 2001.02.11.19.09.57; author bouyer; state Exp; branches; next 1.1.2.3; 1.1.2.3 date 2001.03.27.15.30.49; author bouyer; state Exp; branches; next ; 1.1.4.1 date 2001.04.09.01.52.41; author nathanw; state Exp; branches; next ; desc @@ 1.9 log @Added support PXA270. @ text @; $NetBSD: arm.asm,v 1.8 2008/05/03 23:49:14 martin Exp $ ; ; Copyright (c) 2001 The NetBSD Foundation, Inc. ; All rights reserved. ; ; This code is derived from software contributed to The NetBSD Foundation ; by UCHIYAMA Yasushi. ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions ; are met: ; 1. Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; ; THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS ; ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS ; BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ; ;armasm.exe $(InputPath) ;arm.obj ; ; dummy buffer for WritebackDCache EXPORT |dcachesize| [DATA] EXPORT |dcachebuf| [DATA] AREA |.data|, DATA |dcachesize| DCD 8192 ; for SA1100 |dcachebuf| % 65536 ; max D-cache size AREA |.text|, CODE, PIC ; ; Operation mode ops. ; EXPORT |SetSVCMode| |SetSVCMode| PROC mrs r0, cpsr bic r0, r0, #0x1f orr r0, r0, #0x13 msr cpsr, r0 mov pc, lr ENDP ; |SetSVCMode| EXPORT |SetSystemMode| |SetSystemMode| PROC mrs r0, cpsr orr r0, r0, #0x1f msr cpsr, r0 mov pc, lr ENDP ; |SetSystemMode| ; ; Interrupt ops. ; EXPORT |DI| |DI| PROC mrs r0, cpsr orr r0, r0, #0xc0 msr cpsr, r0 mov pc, lr ENDP ; |DI| EXPORT |EI| |EI| PROC mrs r0, cpsr bic r0, r0, #0xc0 msr cpsr, r0 mov pc, lr ENDP ; |EI| ; ; Cache ops. ; EXPORT |InvalidateICache| |InvalidateICache| PROC ; c7 (CRn) Cache Control Register ; c5, 0 (CRm, opcode_2) Flush I ; r0 (Rd) ignored mcr p15, 0, r0, c7, c5, 0 mov pc, lr ENDP ; |InvalidateICache| EXPORT |WritebackDCache| |WritebackDCache| PROC ldr r0, [pc, #24] ; dcachebuf ldr r1, [pc, #24] ldr r1, [r1] ; dcache-size add r1, r1, r0 |wbdc1| ldr r2, [r0], #32 ; line-size is 32byte. teq r1, r0 bne |wbdc1| mov pc, lr DCD |dcachebuf| DCD |dcachesize| ENDP ; |WritebackDCache| EXPORT |InvalidateDCache| |InvalidateDCache| PROC ; c7 (CRn) Cache Control Register ; c6, 0 (CRm, opcode_2) Flush D ; r0 (Rd) ignored mcr p15, 0, r0, c7, c6, 0 mov pc, lr ENDP ; |InvalidateDCache| EXPORT |WritebackInvalidateDCache| |WritebackInvalidateDCache| PROC ldr r0, [pc, #28] ; dcachebuf ldr r1, [pc, #28] ldr r1, [r1] ; dcache-size add r1, r1, r0 |wbidc1| ldr r2, [r0], #32 teq r1, r0 bne |wbidc1| mcr p15, 0, r0, c7, c6, 0 mov pc, lr DCD |dcachebuf| DCD |dcachesize| ENDP ; |WritebackInvalidateDCache| ; ; WriteBuffer ops ; EXPORT |WritebufferFlush| |WritebufferFlush| PROC ; c7 (CRn) Cache Control Register ; c10, 4(CRm, opcode_2) Flush D ; r0 (Rd) ignored mcr p15, 0, r0, c7, c10, 4 mov pc, lr ENDP ; |WritebufferFlush| ; ; TLB ops. ; EXPORT |FlushIDTLB| |FlushIDTLB| PROC mcr p15, 0, r0, c8, c7, 0 mov pc, lr ENDP ; |FlushIDTLB| EXPORT |FlushITLB| |FlushITLB| PROC mcr p15, 0, r0, c8, c5, 0 mov pc, lr ENDP ; |FlushITLB| EXPORT |FlushDTLB| |FlushDTLB| PROC mcr p15, 0, r0, c8, c6, 0 mov pc, lr ENDP ; |FlushITLB| EXPORT |FlushDTLBS| |FlushDTLBS| PROC mcr p15, 0, r0, c8, c6, 1 mov pc, lr ENDP ; |FlushITLBS| ; ; CurrentProgramStatusRegister access. ; EXPORT |GetCPSR| |GetCPSR| PROC mrs r0, cpsr mov pc, lr ENDP ; |GetCPSR| EXPORT |SetCPSR| |SetCPSR| PROC msr cpsr, r0 mov pc, lr ENDP ; |SetCPSR| ; ; SA-1100 Coprocessor15 access. ; ; Reg0 ID (R) EXPORT |GetCop15Reg0| |GetCop15Reg0| PROC mrc p15, 0, r0, c0, c0, 0 ; 0x4401a119 (44|01 = version 4|A11 = SA1100|9 = E stepping) mov pc, lr ENDP ; |GetCop15Reg0| ; Reg1 Control (R/W) EXPORT |GetCop15Reg1| |GetCop15Reg1| PROC mrc p15, 0, r0, c1, c0, 0 ; 0xc007327f (||...........|||..||..|..|||||||) ; 0 (1)MMU enabled ; 1 (1)Address fault enabled ; 2 (1)D-cache enabled ; 3 (1)Write-buffer enabled ; 7 (0)little-endian ; 8 (0)MMU protection (System) ; 9 (1)MMU protection (ROM) ; 12 (1)I-cache enabled ; 13 (1)Base address of interrupt vector is 0xffff0000 mov pc, lr ENDP ; |GetCop15Reg1| EXPORT |SetCop15Reg1| |SetCop15Reg1| PROC mcr p15, 0, r0, c1, c0, 0 nop nop nop mov pc, lr ENDP ; |SetCop15Reg1| ; Reg2 Translation table base (R/W) EXPORT |GetCop15Reg2| |GetCop15Reg2| PROC mrc p15, 0, r0, c2, c0, 0 mov pc, lr ENDP ; |GetCop15Reg2| EXPORT |SetCop15Reg2| |SetCop15Reg2| PROC mcr p15, 0, r0, c2, c0, 0 mov pc, lr ENDP ; |SetCop15Reg2| ; Reg3 Domain access control (R/W) EXPORT |GetCop15Reg3| |GetCop15Reg3| PROC mrc p15, 0, r0, c3, c0, 0 mov pc, lr ENDP ; |GetCop15Reg3| EXPORT |SetCop15Reg3| |SetCop15Reg3| PROC mcr p15, 0, r0, c3, c0, 0 mov pc, lr ENDP ; |SetCop15Reg3| ; Reg5 Fault status (R/W) EXPORT |GetCop15Reg5| |GetCop15Reg5| PROC mrc p15, 0, r0, c5, c0, 0 mov pc, lr ENDP ; |GetCop15Reg5| ; Reg6 Fault address (R/W) EXPORT |GetCop15Reg6| |GetCop15Reg6| PROC mrc p15, 0, r0, c6, c0, 0 mov pc, lr ENDP ; |GetCop15Reg6| ; Reg7 Cache operations (W) ; -> Cache ops ; Reg8 TLB operations (Flush) (W) ; -> TLB ops ; Reg9 Read buffer operations (W) ; Reg13 Process ID (R/W) EXPORT |GetCop15Reg13| |GetCop15Reg13| PROC mrc p15, 0, r0, c13, c0, 0 mov pc, lr ENDP ; |GetCop15Reg13| EXPORT |SetCop15Reg13| |SetCop15Reg13| PROC mcr p15, 0, r0, c13, c0, 0 mov pc, lr ENDP ; |SetCop15Reg13| ; Reg14 Breakpoint (R/W) EXPORT |GetCop15Reg14| |GetCop15Reg14| PROC mrc p15, 0, r0, c14, c0, 0 mov pc, lr ENDP ; |GetCop15Reg14| ; Reg15 Test, clock, and idle (W) END @ 1.8 log @Move to 2 clause TNF license @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.7 2008/03/08 01:50:06 rafal Exp $ d36 1 d39 2 d42 1 a42 1 % 8192 ; D-cache size d97 4 a100 2 ldr r0, [pc, #16] ; dcachebuf add r1, r0, #8192 ; cache-size is 8Kbyte. d107 1 d121 4 a124 2 ldr r0, [pc, #20] ; dcachebuf add r1, r0, #8192 d132 1 a287 225 ; FlatJump (kaddr_t bootinfo, kaddr_t pvec, kaddr_t stack ; kaddr_t jump) ; bootinfo boot information block address. ; pvec page vector of kernel. ; stack physical address of stack ; jump physical address of boot function ; *** MMU and pipeline behavier are SA-1100 specific. *** EXPORT |FlatJump| |FlatJump| PROC ; disable interrupt mrs r4, cpsr orr r4, r4, #0xc0 msr cpsr, r4 ; disable MMU, I/D-Cache, Writebuffer. ; interrupt vector address is 0xffff0000 ; 32bit exception handler/address range. ldr r4, [pc, #24] ; Disable WB/Cache/MMU mcr p15, 0, r4, c1, c0, 0 ; Invalidate I/D-cache. mcr p15, 0, r4, c7, c7, 0 ; Fetch translated fetch ; Invalidate TLB entries. mcr p15, 0, r4, c8, c7, 0 ; Fetch translated decode ; jump to kernel entry physical address. mov pc, r3 ; Fetch translated execute ; NOTREACHED nop ; Fetch nontranslated cache access nop ; Fetch nontranslated writeback mov pc, lr ; Fetch nontranslated DCD 0x00002030 ENDP ; |FlatJump| ; ; UART test ; ; boot_func (uint32_t mapaddr, uint32_t bootinfo, uint32_t flags) ; EXPORT |boot_func| |boot_func| PROC nop ; Cop15 hazard nop ; Cop15 hazard nop ; Cop15 hazard mov sp, r2 ; set bootloader stack ; mov r4, r0 ; mov r5, r1 ; bl colorbar ; mov r0, r4 ; mov r1, r5 bl boot nop ; NOTREACHED nop ENDP ; |boot_func| EXPORT |colorbar| |colorbar| PROC stmfd sp!, {r4-r7, lr} adr r4, |$FBADDR| ldr r4, [r4] mov r7, #8 add r0, r0, r7 |color_loop| mov r6, r0 and r6, r6, #7 orr r6, r6, r6, LSL #8 orr r6, r6, r6, LSL #16 add r5, r4, #0x9600 |fb_loop| str r6, [r4], #4 cmp r4, r5 blt |fb_loop| subs r7, r7, #1 bne |color_loop| ldmfd sp!, {r4-r7, pc} |$FBADDR| DCD 0xc0003000 ; use WindowsCE default. ENDP ; |colorbar| EXPORT |boot| |boot| PROC ; ; UART test code ; ; ; print boot_info address (r0) and page_vector start address (r1). ; mov r4, r0 ; mov r5, r1 ; mov r0, #'I' ; bl btputc ; mov r0, r4 ; bl hexdump ; mov r0, #'P' ; bl btputc ; mov r0, r5 ; bl hexdump ; mov r7, r4 ; mov r2, r5 ; start mov r7, r0 ; if enabled above debug print, remove this. mov r2, r1 ; if enabled above debug print, remove this. |page_loop| mvn r0, #0 ; ~0 cmp r2, r0 beq |page_end| ; if (next == ~0) goto page_end mov r1, r2 ; p = next ldr r2, [r1] ; next ldr r3, [r1, #4] ; src ldr r4, [r1, #8] ; dst ldr r5, [r1, #12] ; sz cmp r3, r0 add r6, r4, r5 ; end address bne |page_memcpy4| ; if (src != ~0) goto page_memcpy4 mov r0, #0 |page_memset| ; memset (dst, 0, sz) uncached. str r0, [r4], #4 cmp r4, r6 blt |page_memset| b |page_loop| |page_memcpy4| ; memcpy (dst, src, sz) uncached. ldr r0, [r3], #4 ldr r5, [r3], #4 str r0, [r4], #4 cmp r4, r6 strlt r5, [r4], #4 cmplt r4, r6 blt |page_memcpy4| b |page_loop| |page_end| ; ; jump to kernel ; ; mov r0, #'E' ; bl btputc ; ldr r0, [r7] ; bl hexdump ; ldr r0, [r7] ; ldr r0, [r0] ; bl hexdump ; set stack pointer mov r5, #4096 add r6, r6, #8192 sub r5, r5, #1 bic sp, r6, r5 ; set bootargs ldr r4, [r7] ldr r0, [r7, #4] ldr r1, [r7, #8] ldr r2, [r7, #12] mov pc, r4 ; NOTREACHED |infinite_loop| nop nop nop nop nop b |infinite_loop| ENDP ; |boot| |btputc| PROC adr r1, |$UARTTXBSY| ldr r1, [r1] |btputc_busy| ldr r2, [r1] and r2, r2, #1 cmp r2, #1 beq |btputc_busy| adr r1, |$UARTTXADR| ldr r1, [r1] str r0, [r1] mov pc, lr ENDP ;|btputc| |hexdump| PROC stmfd sp!, {r4-r5, lr} mov r4, r0 mov r0, #0x30 bl btputc mov r0, #0x78 bl btputc mov r0, r4 ; Transmit register address adr r1, |$UARTTXADR| ldr r1, [r1] ; Transmit busy register address adr r2, |$UARTTXBSY| ldr r2, [r2] mov r5, #8 |hex_loop| mov r3, r0, LSR #28 cmp r3, #9 addgt r3, r3, #0x41 - 10 addle r3, r3, #0x30 |hex_busyloop| ldr r4, [r2] and r4, r4, #1 cmp r4, #1 beq |hex_busyloop| str r3, [r1] mov r0, r0, LSL #4 subs r5, r5, #1 bne |hex_loop| mov r0, #0x0d bl btputc mov r0, #0x0a bl btputc ldmfd sp!, {r4-r5, pc} ENDP ;|hexdump| |$UARTTXADR| DCD 0x80050014 |$UARTTXBSY| DCD 0x80050020 EXPORT |boot_func_end| [ DATA ] |boot_func_end| DCD 0x0 @ 1.8.22.1 log @sync with head @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.8 2008/05/03 23:49:14 martin Exp $ a35 1 EXPORT |dcachesize| [DATA] a37 2 |dcachesize| DCD 8192 ; for SA1100 d39 1 a39 1 % 65536 ; max D-cache size d94 2 a95 4 ldr r0, [pc, #24] ; dcachebuf ldr r1, [pc, #24] ldr r1, [r1] ; dcache-size add r1, r1, r0 a101 1 DCD |dcachesize| d115 2 a116 4 ldr r0, [pc, #28] ; dcachebuf ldr r1, [pc, #28] ldr r1, [r1] ; dcache-size add r1, r1, r0 a123 1 DCD |dcachesize| d279 225 @ 1.8.20.1 log @Sync with HEAD. @ text @d1 1 a1 1 ; $NetBSD$ a35 1 EXPORT |dcachesize| [DATA] a37 2 |dcachesize| DCD 8192 ; for SA1100 d39 1 a39 1 % 65536 ; max D-cache size d94 2 a95 4 ldr r0, [pc, #24] ; dcachebuf ldr r1, [pc, #24] ldr r1, [r1] ; dcache-size add r1, r1, r0 a101 1 DCD |dcachesize| d115 2 a116 4 ldr r0, [pc, #28] ; dcachebuf ldr r1, [pc, #28] ldr r1, [r1] ; dcache-size add r1, r1, r0 a123 1 DCD |dcachesize| d279 225 @ 1.7 log @Grrr, don't grow the stack *up*, grown it *down* as everything else expects. Fixes a frequent memory stomp of the bootinfo page (the kernel entry address, no less) that occurrs when you turn the serial-debug code in the ARM 2nd- stage bootloader. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.6 2006/03/05 04:05:39 uwe Exp $ a16 7 ; 3. All advertising materials mentioning features or use of this software ; must display the following acknowledgement: ; This product includes software developed by the NetBSD ; Foundation, Inc. and its contributors. ; 4. Neither the name of The NetBSD Foundation nor the names of its ; contributors may be used to endorse or promote products derived ; from this software without specific prior written permission. @ 1.7.2.1 log @sync with head. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.7 2008/03/08 01:50:06 rafal Exp $ d17 7 @ 1.7.4.1 log @sync with head. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.7 2008/03/08 01:50:06 rafal Exp $ d17 7 @ 1.7.4.2 log @sync with head. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.7.4.1 2008/05/16 02:22:24 yamt Exp $ a35 1 EXPORT |dcachesize| [DATA] a37 2 |dcachesize| DCD 8192 ; for SA1100 d39 1 a39 1 % 65536 ; max D-cache size d94 2 a95 4 ldr r0, [pc, #24] ; dcachebuf ldr r1, [pc, #24] ldr r1, [r1] ; dcache-size add r1, r1, r0 a101 1 DCD |dcachesize| d115 2 a116 4 ldr r0, [pc, #28] ; dcachebuf ldr r1, [pc, #28] ldr r1, [r1] ; dcache-size add r1, r1, r0 a123 1 DCD |dcachesize| d279 225 @ 1.6 log @s/u_intN_t/uintN_t/ @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.5 2005/12/11 12:17:28 christos Exp $ d340 1 a340 1 stmea sp!, {r4-r7, lr} d360 1 a360 1 ldmea sp!, {r4-r7, pc} d468 1 a468 1 stmea sp!, {r4-r5, lr} d500 1 a500 1 ldmea sp!, {r4-r5, pc} @ 1.6.2.1 log @file arm.asm was added on branch yamt-pdpolicy on 2006-03-05 04:05:40 +0000 @ text @d1 511 @ 1.6.2.2 log @s/u_intN_t/uintN_t/ @ text @a0 511 ; $NetBSD: arm.asm,v 1.6 2006/03/05 04:05:39 uwe Exp $ ; ; Copyright (c) 2001 The NetBSD Foundation, Inc. ; All rights reserved. ; ; This code is derived from software contributed to The NetBSD Foundation ; by UCHIYAMA Yasushi. ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions ; are met: ; 1. Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; 3. All advertising materials mentioning features or use of this software ; must display the following acknowledgement: ; This product includes software developed by the NetBSD ; Foundation, Inc. and its contributors. ; 4. Neither the name of The NetBSD Foundation nor the names of its ; contributors may be used to endorse or promote products derived ; from this software without specific prior written permission. ; ; THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS ; ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS ; BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ; ;armasm.exe $(InputPath) ;arm.obj ; ; dummy buffer for WritebackDCache EXPORT |dcachebuf| [DATA] AREA |.data|, DATA |dcachebuf| % 8192 ; D-cache size AREA |.text|, CODE, PIC ; ; Operation mode ops. ; EXPORT |SetSVCMode| |SetSVCMode| PROC mrs r0, cpsr bic r0, r0, #0x1f orr r0, r0, #0x13 msr cpsr, r0 mov pc, lr ENDP ; |SetSVCMode| EXPORT |SetSystemMode| |SetSystemMode| PROC mrs r0, cpsr orr r0, r0, #0x1f msr cpsr, r0 mov pc, lr ENDP ; |SetSystemMode| ; ; Interrupt ops. ; EXPORT |DI| |DI| PROC mrs r0, cpsr orr r0, r0, #0xc0 msr cpsr, r0 mov pc, lr ENDP ; |DI| EXPORT |EI| |EI| PROC mrs r0, cpsr bic r0, r0, #0xc0 msr cpsr, r0 mov pc, lr ENDP ; |EI| ; ; Cache ops. ; EXPORT |InvalidateICache| |InvalidateICache| PROC ; c7 (CRn) Cache Control Register ; c5, 0 (CRm, opcode_2) Flush I ; r0 (Rd) ignored mcr p15, 0, r0, c7, c5, 0 mov pc, lr ENDP ; |InvalidateICache| EXPORT |WritebackDCache| |WritebackDCache| PROC ldr r0, [pc, #16] ; dcachebuf add r1, r0, #8192 ; cache-size is 8Kbyte. |wbdc1| ldr r2, [r0], #32 ; line-size is 32byte. teq r1, r0 bne |wbdc1| mov pc, lr DCD |dcachebuf| ENDP ; |WritebackDCache| EXPORT |InvalidateDCache| |InvalidateDCache| PROC ; c7 (CRn) Cache Control Register ; c6, 0 (CRm, opcode_2) Flush D ; r0 (Rd) ignored mcr p15, 0, r0, c7, c6, 0 mov pc, lr ENDP ; |InvalidateDCache| EXPORT |WritebackInvalidateDCache| |WritebackInvalidateDCache| PROC ldr r0, [pc, #20] ; dcachebuf add r1, r0, #8192 |wbidc1| ldr r2, [r0], #32 teq r1, r0 bne |wbidc1| mcr p15, 0, r0, c7, c6, 0 mov pc, lr DCD |dcachebuf| ENDP ; |WritebackInvalidateDCache| ; ; WriteBuffer ops ; EXPORT |WritebufferFlush| |WritebufferFlush| PROC ; c7 (CRn) Cache Control Register ; c10, 4(CRm, opcode_2) Flush D ; r0 (Rd) ignored mcr p15, 0, r0, c7, c10, 4 mov pc, lr ENDP ; |WritebufferFlush| ; ; TLB ops. ; EXPORT |FlushIDTLB| |FlushIDTLB| PROC mcr p15, 0, r0, c8, c7, 0 mov pc, lr ENDP ; |FlushIDTLB| EXPORT |FlushITLB| |FlushITLB| PROC mcr p15, 0, r0, c8, c5, 0 mov pc, lr ENDP ; |FlushITLB| EXPORT |FlushDTLB| |FlushDTLB| PROC mcr p15, 0, r0, c8, c6, 0 mov pc, lr ENDP ; |FlushITLB| EXPORT |FlushDTLBS| |FlushDTLBS| PROC mcr p15, 0, r0, c8, c6, 1 mov pc, lr ENDP ; |FlushITLBS| ; ; CurrentProgramStatusRegister access. ; EXPORT |GetCPSR| |GetCPSR| PROC mrs r0, cpsr mov pc, lr ENDP ; |GetCPSR| EXPORT |SetCPSR| |SetCPSR| PROC msr cpsr, r0 mov pc, lr ENDP ; |SetCPSR| ; ; SA-1100 Coprocessor15 access. ; ; Reg0 ID (R) EXPORT |GetCop15Reg0| |GetCop15Reg0| PROC mrc p15, 0, r0, c0, c0, 0 ; 0x4401a119 (44|01 = version 4|A11 = SA1100|9 = E stepping) mov pc, lr ENDP ; |GetCop15Reg0| ; Reg1 Control (R/W) EXPORT |GetCop15Reg1| |GetCop15Reg1| PROC mrc p15, 0, r0, c1, c0, 0 ; 0xc007327f (||...........|||..||..|..|||||||) ; 0 (1)MMU enabled ; 1 (1)Address fault enabled ; 2 (1)D-cache enabled ; 3 (1)Write-buffer enabled ; 7 (0)little-endian ; 8 (0)MMU protection (System) ; 9 (1)MMU protection (ROM) ; 12 (1)I-cache enabled ; 13 (1)Base address of interrupt vector is 0xffff0000 mov pc, lr ENDP ; |GetCop15Reg1| EXPORT |SetCop15Reg1| |SetCop15Reg1| PROC mcr p15, 0, r0, c1, c0, 0 nop nop nop mov pc, lr ENDP ; |SetCop15Reg1| ; Reg2 Translation table base (R/W) EXPORT |GetCop15Reg2| |GetCop15Reg2| PROC mrc p15, 0, r0, c2, c0, 0 mov pc, lr ENDP ; |GetCop15Reg2| EXPORT |SetCop15Reg2| |SetCop15Reg2| PROC mcr p15, 0, r0, c2, c0, 0 mov pc, lr ENDP ; |SetCop15Reg2| ; Reg3 Domain access control (R/W) EXPORT |GetCop15Reg3| |GetCop15Reg3| PROC mrc p15, 0, r0, c3, c0, 0 mov pc, lr ENDP ; |GetCop15Reg3| EXPORT |SetCop15Reg3| |SetCop15Reg3| PROC mcr p15, 0, r0, c3, c0, 0 mov pc, lr ENDP ; |SetCop15Reg3| ; Reg5 Fault status (R/W) EXPORT |GetCop15Reg5| |GetCop15Reg5| PROC mrc p15, 0, r0, c5, c0, 0 mov pc, lr ENDP ; |GetCop15Reg5| ; Reg6 Fault address (R/W) EXPORT |GetCop15Reg6| |GetCop15Reg6| PROC mrc p15, 0, r0, c6, c0, 0 mov pc, lr ENDP ; |GetCop15Reg6| ; Reg7 Cache operations (W) ; -> Cache ops ; Reg8 TLB operations (Flush) (W) ; -> TLB ops ; Reg9 Read buffer operations (W) ; Reg13 Process ID (R/W) EXPORT |GetCop15Reg13| |GetCop15Reg13| PROC mrc p15, 0, r0, c13, c0, 0 mov pc, lr ENDP ; |GetCop15Reg13| EXPORT |SetCop15Reg13| |SetCop15Reg13| PROC mcr p15, 0, r0, c13, c0, 0 mov pc, lr ENDP ; |SetCop15Reg13| ; Reg14 Breakpoint (R/W) EXPORT |GetCop15Reg14| |GetCop15Reg14| PROC mrc p15, 0, r0, c14, c0, 0 mov pc, lr ENDP ; |GetCop15Reg14| ; Reg15 Test, clock, and idle (W) ; FlatJump (kaddr_t bootinfo, kaddr_t pvec, kaddr_t stack ; kaddr_t jump) ; bootinfo boot information block address. ; pvec page vector of kernel. ; stack physical address of stack ; jump physical address of boot function ; *** MMU and pipeline behavier are SA-1100 specific. *** EXPORT |FlatJump| |FlatJump| PROC ; disable interrupt mrs r4, cpsr orr r4, r4, #0xc0 msr cpsr, r4 ; disable MMU, I/D-Cache, Writebuffer. ; interrupt vector address is 0xffff0000 ; 32bit exception handler/address range. ldr r4, [pc, #24] ; Disable WB/Cache/MMU mcr p15, 0, r4, c1, c0, 0 ; Invalidate I/D-cache. mcr p15, 0, r4, c7, c7, 0 ; Fetch translated fetch ; Invalidate TLB entries. mcr p15, 0, r4, c8, c7, 0 ; Fetch translated decode ; jump to kernel entry physical address. mov pc, r3 ; Fetch translated execute ; NOTREACHED nop ; Fetch nontranslated cache access nop ; Fetch nontranslated writeback mov pc, lr ; Fetch nontranslated DCD 0x00002030 ENDP ; |FlatJump| ; ; UART test ; ; boot_func (uint32_t mapaddr, uint32_t bootinfo, uint32_t flags) ; EXPORT |boot_func| |boot_func| PROC nop ; Cop15 hazard nop ; Cop15 hazard nop ; Cop15 hazard mov sp, r2 ; set bootloader stack ; mov r4, r0 ; mov r5, r1 ; bl colorbar ; mov r0, r4 ; mov r1, r5 bl boot nop ; NOTREACHED nop ENDP ; |boot_func| EXPORT |colorbar| |colorbar| PROC stmea sp!, {r4-r7, lr} adr r4, |$FBADDR| ldr r4, [r4] mov r7, #8 add r0, r0, r7 |color_loop| mov r6, r0 and r6, r6, #7 orr r6, r6, r6, LSL #8 orr r6, r6, r6, LSL #16 add r5, r4, #0x9600 |fb_loop| str r6, [r4], #4 cmp r4, r5 blt |fb_loop| subs r7, r7, #1 bne |color_loop| ldmea sp!, {r4-r7, pc} |$FBADDR| DCD 0xc0003000 ; use WindowsCE default. ENDP ; |colorbar| EXPORT |boot| |boot| PROC ; ; UART test code ; ; ; print boot_info address (r0) and page_vector start address (r1). ; mov r4, r0 ; mov r5, r1 ; mov r0, #'I' ; bl btputc ; mov r0, r4 ; bl hexdump ; mov r0, #'P' ; bl btputc ; mov r0, r5 ; bl hexdump ; mov r7, r4 ; mov r2, r5 ; start mov r7, r0 ; if enabled above debug print, remove this. mov r2, r1 ; if enabled above debug print, remove this. |page_loop| mvn r0, #0 ; ~0 cmp r2, r0 beq |page_end| ; if (next == ~0) goto page_end mov r1, r2 ; p = next ldr r2, [r1] ; next ldr r3, [r1, #4] ; src ldr r4, [r1, #8] ; dst ldr r5, [r1, #12] ; sz cmp r3, r0 add r6, r4, r5 ; end address bne |page_memcpy4| ; if (src != ~0) goto page_memcpy4 mov r0, #0 |page_memset| ; memset (dst, 0, sz) uncached. str r0, [r4], #4 cmp r4, r6 blt |page_memset| b |page_loop| |page_memcpy4| ; memcpy (dst, src, sz) uncached. ldr r0, [r3], #4 ldr r5, [r3], #4 str r0, [r4], #4 cmp r4, r6 strlt r5, [r4], #4 cmplt r4, r6 blt |page_memcpy4| b |page_loop| |page_end| ; ; jump to kernel ; ; mov r0, #'E' ; bl btputc ; ldr r0, [r7] ; bl hexdump ; ldr r0, [r7] ; ldr r0, [r0] ; bl hexdump ; set stack pointer mov r5, #4096 add r6, r6, #8192 sub r5, r5, #1 bic sp, r6, r5 ; set bootargs ldr r4, [r7] ldr r0, [r7, #4] ldr r1, [r7, #8] ldr r2, [r7, #12] mov pc, r4 ; NOTREACHED |infinite_loop| nop nop nop nop nop b |infinite_loop| ENDP ; |boot| |btputc| PROC adr r1, |$UARTTXBSY| ldr r1, [r1] |btputc_busy| ldr r2, [r1] and r2, r2, #1 cmp r2, #1 beq |btputc_busy| adr r1, |$UARTTXADR| ldr r1, [r1] str r0, [r1] mov pc, lr ENDP ;|btputc| |hexdump| PROC stmea sp!, {r4-r5, lr} mov r4, r0 mov r0, #0x30 bl btputc mov r0, #0x78 bl btputc mov r0, r4 ; Transmit register address adr r1, |$UARTTXADR| ldr r1, [r1] ; Transmit busy register address adr r2, |$UARTTXBSY| ldr r2, [r2] mov r5, #8 |hex_loop| mov r3, r0, LSR #28 cmp r3, #9 addgt r3, r3, #0x41 - 10 addle r3, r3, #0x30 |hex_busyloop| ldr r4, [r2] and r4, r4, #1 cmp r4, #1 beq |hex_busyloop| str r3, [r1] mov r0, r0, LSL #4 subs r5, r5, #1 bne |hex_loop| mov r0, #0x0d bl btputc mov r0, #0x0a bl btputc ldmea sp!, {r4-r5, pc} ENDP ;|hexdump| |$UARTTXADR| DCD 0x80050014 |$UARTTXBSY| DCD 0x80050020 EXPORT |boot_func_end| [ DATA ] |boot_func_end| DCD 0x0 END @ 1.6.68.1 log @Sync with HEAD. @ text @d1 1 a1 1 ; $NetBSD$ d340 1 a340 1 stmfd sp!, {r4-r7, lr} d360 1 a360 1 ldmfd sp!, {r4-r7, pc} d468 1 a468 1 stmfd sp!, {r4-r5, lr} d500 1 a500 1 ldmfd sp!, {r4-r5, pc} @ 1.6.68.2 log @Sync with HEAD. @ text @d17 7 @ 1.6.64.1 log @sync with head. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.7 2008/03/08 01:50:06 rafal Exp $ d340 1 a340 1 stmfd sp!, {r4-r7, lr} d360 1 a360 1 ldmfd sp!, {r4-r7, pc} d468 1 a468 1 stmfd sp!, {r4-r5, lr} d500 1 a500 1 ldmfd sp!, {r4-r5, pc} @ 1.6.44.1 log @sync with HEAD @ text @d1 1 a1 1 ; arm.asm,v 1.6 2006/03/05 04:05:39 uwe Exp d340 1 a340 1 stmfd sp!, {r4-r7, lr} d360 1 a360 1 ldmfd sp!, {r4-r7, pc} d468 1 a468 1 stmfd sp!, {r4-r5, lr} d500 1 a500 1 ldmfd sp!, {r4-r5, pc} @ 1.5 log @merge ktrace-lwp. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.3.22.3 2004/09/21 13:15:53 skrll Exp $ d320 1 a320 1 ; boot_func (u_int32_t mapaddr, u_int32_t bootinfo, u_int32_t flags) @ 1.5.4.1 log @sync with head @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.6 2006/03/05 04:05:39 uwe Exp $ d320 1 a320 1 ; boot_func (uint32_t mapaddr, uint32_t bootinfo, uint32_t flags) @ 1.5.6.1 log @Sync with head. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.6 2006/03/05 04:05:39 uwe Exp $ d320 1 a320 1 ; boot_func (uint32_t mapaddr, uint32_t bootinfo, uint32_t flags) @ 1.4 log @clean up whitespace. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.3 2001/07/17 01:43:42 toshii Exp $ @ 1.4.12.1 log @sync with head. @ text @d1 1 a1 1 ; $NetBSD$ d320 1 a320 1 ; boot_func (uint32_t mapaddr, uint32_t bootinfo, uint32_t flags) @ 1.4.12.2 log @sync with head. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.4.12.1 2006/06/21 14:51:38 yamt Exp $ d340 1 a340 1 stmfd sp!, {r4-r7, lr} d360 1 a360 1 ldmfd sp!, {r4-r7, pc} d468 1 a468 1 stmfd sp!, {r4-r5, lr} d500 1 a500 1 ldmfd sp!, {r4-r5, pc} @ 1.3 log @"infomation" -> "information" @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.2 2001/03/23 08:48:12 toshii Exp $ d37 1 a37 1 d45 1 a45 1 |dcachebuf| d49 1 a49 1 d86 1 a86 1 d98 1 a98 1 d110 1 a110 1 d116 1 a116 1 mcr p15, 0, r0, c7, c6, 0 d159 1 a159 1 d181 1 a181 1 EXPORT |SetCPSR| d214 1 a214 1 EXPORT |SetCop15Reg1| d222 3 a224 3 ; Reg2 Translation table base (R/W) EXPORT |GetCop15Reg2| d229 1 a229 1 EXPORT |SetCop15Reg2| d241 1 a241 1 EXPORT |SetCop15Reg3| d246 1 a246 1 d248 1 a248 1 EXPORT |GetCop15Reg5| d253 3 a255 3 ; Reg6 Fault address (R/W) EXPORT |GetCop15Reg6| d265 3 a267 3 ; Reg9 Read buffer operations (W) ; Reg13 Process ID (R/W) EXPORT |GetCop15Reg13| d272 1 a272 1 EXPORT |SetCop15Reg13| d277 1 a277 1 d279 1 a279 1 EXPORT |GetCop15Reg14| d285 1 a285 1 d291 1 a291 1 ; jump physical address of boot function d319 1 a319 1 ; d336 2 a337 2 ENDP ; |boot_func| d339 3 a341 3 |colorbar| PROC stmea sp!, {r4-r7, lr} adr r4, |$FBADDR| d343 1 a343 1 d349 1 a349 1 orr r6, r6, r6, LSL #8 d356 1 a356 1 d358 2 a359 2 bne |color_loop| d363 2 a364 2 ENDP ; |colorbar| d369 1 a369 1 ; d382 2 a383 2 ; mov r2, r5 ; start d386 1 a386 1 |page_loop| d390 1 a390 1 d396 1 a396 1 d401 1 a401 1 mov r0, #0 d407 1 a407 1 d421 1 a421 1 ; d443 1 a443 1 d452 1 a452 1 d482 1 a482 1 |hex_loop| d502 1 a502 1 d505 3 a507 3 |$UARTTXBSY| DCD 0x80050020 d509 1 a509 1 |boot_func_end| DCD 0x0 @ 1.3.6.1 log @file arm.asm was added on branch nathanw_sa on 2001-07-17 01:43:43 +0000 @ text @d1 511 @ 1.3.6.2 log @"infomation" -> "information" @ text @a0 511 ; $NetBSD: arm.asm,v 1.3 2001/07/17 01:43:42 toshii Exp $ ; ; Copyright (c) 2001 The NetBSD Foundation, Inc. ; All rights reserved. ; ; This code is derived from software contributed to The NetBSD Foundation ; by UCHIYAMA Yasushi. ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions ; are met: ; 1. Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; 3. All advertising materials mentioning features or use of this software ; must display the following acknowledgement: ; This product includes software developed by the NetBSD ; Foundation, Inc. and its contributors. ; 4. Neither the name of The NetBSD Foundation nor the names of its ; contributors may be used to endorse or promote products derived ; from this software without specific prior written permission. ; ; THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS ; ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS ; BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ; ;armasm.exe $(InputPath) ;arm.obj ; ; dummy buffer for WritebackDCache EXPORT |dcachebuf| [DATA] AREA |.data|, DATA |dcachebuf| % 8192 ; D-cache size AREA |.text|, CODE, PIC ; ; Operation mode ops. ; EXPORT |SetSVCMode| |SetSVCMode| PROC mrs r0, cpsr bic r0, r0, #0x1f orr r0, r0, #0x13 msr cpsr, r0 mov pc, lr ENDP ; |SetSVCMode| EXPORT |SetSystemMode| |SetSystemMode| PROC mrs r0, cpsr orr r0, r0, #0x1f msr cpsr, r0 mov pc, lr ENDP ; |SetSystemMode| ; ; Interrupt ops. ; EXPORT |DI| |DI| PROC mrs r0, cpsr orr r0, r0, #0xc0 msr cpsr, r0 mov pc, lr ENDP ; |DI| EXPORT |EI| |EI| PROC mrs r0, cpsr bic r0, r0, #0xc0 msr cpsr, r0 mov pc, lr ENDP ; |EI| ; ; Cache ops. ; EXPORT |InvalidateICache| |InvalidateICache| PROC ; c7 (CRn) Cache Control Register ; c5, 0 (CRm, opcode_2) Flush I ; r0 (Rd) ignored mcr p15, 0, r0, c7, c5, 0 mov pc, lr ENDP ; |InvalidateICache| EXPORT |WritebackDCache| |WritebackDCache| PROC ldr r0, [pc, #16] ; dcachebuf add r1, r0, #8192 ; cache-size is 8Kbyte. |wbdc1| ldr r2, [r0], #32 ; line-size is 32byte. teq r1, r0 bne |wbdc1| mov pc, lr DCD |dcachebuf| ENDP ; |WritebackDCache| EXPORT |InvalidateDCache| |InvalidateDCache| PROC ; c7 (CRn) Cache Control Register ; c6, 0 (CRm, opcode_2) Flush D ; r0 (Rd) ignored mcr p15, 0, r0, c7, c6, 0 mov pc, lr ENDP ; |InvalidateDCache| EXPORT |WritebackInvalidateDCache| |WritebackInvalidateDCache| PROC ldr r0, [pc, #20] ; dcachebuf add r1, r0, #8192 |wbidc1| ldr r2, [r0], #32 teq r1, r0 bne |wbidc1| mcr p15, 0, r0, c7, c6, 0 mov pc, lr DCD |dcachebuf| ENDP ; |WritebackInvalidateDCache| ; ; WriteBuffer ops ; EXPORT |WritebufferFlush| |WritebufferFlush| PROC ; c7 (CRn) Cache Control Register ; c10, 4(CRm, opcode_2) Flush D ; r0 (Rd) ignored mcr p15, 0, r0, c7, c10, 4 mov pc, lr ENDP ; |WritebufferFlush| ; ; TLB ops. ; EXPORT |FlushIDTLB| |FlushIDTLB| PROC mcr p15, 0, r0, c8, c7, 0 mov pc, lr ENDP ; |FlushIDTLB| EXPORT |FlushITLB| |FlushITLB| PROC mcr p15, 0, r0, c8, c5, 0 mov pc, lr ENDP ; |FlushITLB| EXPORT |FlushDTLB| |FlushDTLB| PROC mcr p15, 0, r0, c8, c6, 0 mov pc, lr ENDP ; |FlushITLB| EXPORT |FlushDTLBS| |FlushDTLBS| PROC mcr p15, 0, r0, c8, c6, 1 mov pc, lr ENDP ; |FlushITLBS| ; ; CurrentProgramStatusRegister access. ; EXPORT |GetCPSR| |GetCPSR| PROC mrs r0, cpsr mov pc, lr ENDP ; |GetCPSR| EXPORT |SetCPSR| |SetCPSR| PROC msr cpsr, r0 mov pc, lr ENDP ; |SetCPSR| ; ; SA-1100 Coprocessor15 access. ; ; Reg0 ID (R) EXPORT |GetCop15Reg0| |GetCop15Reg0| PROC mrc p15, 0, r0, c0, c0, 0 ; 0x4401a119 (44|01 = version 4|A11 = SA1100|9 = E stepping) mov pc, lr ENDP ; |GetCop15Reg0| ; Reg1 Control (R/W) EXPORT |GetCop15Reg1| |GetCop15Reg1| PROC mrc p15, 0, r0, c1, c0, 0 ; 0xc007327f (||...........|||..||..|..|||||||) ; 0 (1)MMU enabled ; 1 (1)Address fault enabled ; 2 (1)D-cache enabled ; 3 (1)Write-buffer enabled ; 7 (0)little-endian ; 8 (0)MMU protection (System) ; 9 (1)MMU protection (ROM) ; 12 (1)I-cache enabled ; 13 (1)Base address of interrupt vector is 0xffff0000 mov pc, lr ENDP ; |GetCop15Reg1| EXPORT |SetCop15Reg1| |SetCop15Reg1| PROC mcr p15, 0, r0, c1, c0, 0 nop nop nop mov pc, lr ENDP ; |SetCop15Reg1| ; Reg2 Translation table base (R/W) EXPORT |GetCop15Reg2| |GetCop15Reg2| PROC mrc p15, 0, r0, c2, c0, 0 mov pc, lr ENDP ; |GetCop15Reg2| EXPORT |SetCop15Reg2| |SetCop15Reg2| PROC mcr p15, 0, r0, c2, c0, 0 mov pc, lr ENDP ; |SetCop15Reg2| ; Reg3 Domain access control (R/W) EXPORT |GetCop15Reg3| |GetCop15Reg3| PROC mrc p15, 0, r0, c3, c0, 0 mov pc, lr ENDP ; |GetCop15Reg3| EXPORT |SetCop15Reg3| |SetCop15Reg3| PROC mcr p15, 0, r0, c3, c0, 0 mov pc, lr ENDP ; |SetCop15Reg3| ; Reg5 Fault status (R/W) EXPORT |GetCop15Reg5| |GetCop15Reg5| PROC mrc p15, 0, r0, c5, c0, 0 mov pc, lr ENDP ; |GetCop15Reg5| ; Reg6 Fault address (R/W) EXPORT |GetCop15Reg6| |GetCop15Reg6| PROC mrc p15, 0, r0, c6, c0, 0 mov pc, lr ENDP ; |GetCop15Reg6| ; Reg7 Cache operations (W) ; -> Cache ops ; Reg8 TLB operations (Flush) (W) ; -> TLB ops ; Reg9 Read buffer operations (W) ; Reg13 Process ID (R/W) EXPORT |GetCop15Reg13| |GetCop15Reg13| PROC mrc p15, 0, r0, c13, c0, 0 mov pc, lr ENDP ; |GetCop15Reg13| EXPORT |SetCop15Reg13| |SetCop15Reg13| PROC mcr p15, 0, r0, c13, c0, 0 mov pc, lr ENDP ; |SetCop15Reg13| ; Reg14 Breakpoint (R/W) EXPORT |GetCop15Reg14| |GetCop15Reg14| PROC mrc p15, 0, r0, c14, c0, 0 mov pc, lr ENDP ; |GetCop15Reg14| ; Reg15 Test, clock, and idle (W) ; FlatJump (kaddr_t bootinfo, kaddr_t pvec, kaddr_t stack ; kaddr_t jump) ; bootinfo boot information block address. ; pvec page vector of kernel. ; stack physical address of stack ; jump physical address of boot function ; *** MMU and pipeline behavier are SA-1100 specific. *** EXPORT |FlatJump| |FlatJump| PROC ; disable interrupt mrs r4, cpsr orr r4, r4, #0xc0 msr cpsr, r4 ; disable MMU, I/D-Cache, Writebuffer. ; interrupt vector address is 0xffff0000 ; 32bit exception handler/address range. ldr r4, [pc, #24] ; Disable WB/Cache/MMU mcr p15, 0, r4, c1, c0, 0 ; Invalidate I/D-cache. mcr p15, 0, r4, c7, c7, 0 ; Fetch translated fetch ; Invalidate TLB entries. mcr p15, 0, r4, c8, c7, 0 ; Fetch translated decode ; jump to kernel entry physical address. mov pc, r3 ; Fetch translated execute ; NOTREACHED nop ; Fetch nontranslated cache access nop ; Fetch nontranslated writeback mov pc, lr ; Fetch nontranslated DCD 0x00002030 ENDP ; |FlatJump| ; ; UART test ; ; boot_func (u_int32_t mapaddr, u_int32_t bootinfo, u_int32_t flags) ; EXPORT |boot_func| |boot_func| PROC nop ; Cop15 hazard nop ; Cop15 hazard nop ; Cop15 hazard mov sp, r2 ; set bootloader stack ; mov r4, r0 ; mov r5, r1 ; bl colorbar ; mov r0, r4 ; mov r1, r5 bl boot nop ; NOTREACHED nop ENDP ; |boot_func| EXPORT |colorbar| |colorbar| PROC stmea sp!, {r4-r7, lr} adr r4, |$FBADDR| ldr r4, [r4] mov r7, #8 add r0, r0, r7 |color_loop| mov r6, r0 and r6, r6, #7 orr r6, r6, r6, LSL #8 orr r6, r6, r6, LSL #16 add r5, r4, #0x9600 |fb_loop| str r6, [r4], #4 cmp r4, r5 blt |fb_loop| subs r7, r7, #1 bne |color_loop| ldmea sp!, {r4-r7, pc} |$FBADDR| DCD 0xc0003000 ; use WindowsCE default. ENDP ; |colorbar| EXPORT |boot| |boot| PROC ; ; UART test code ; ; ; print boot_info address (r0) and page_vector start address (r1). ; mov r4, r0 ; mov r5, r1 ; mov r0, #'I' ; bl btputc ; mov r0, r4 ; bl hexdump ; mov r0, #'P' ; bl btputc ; mov r0, r5 ; bl hexdump ; mov r7, r4 ; mov r2, r5 ; start mov r7, r0 ; if enabled above debug print, remove this. mov r2, r1 ; if enabled above debug print, remove this. |page_loop| mvn r0, #0 ; ~0 cmp r2, r0 beq |page_end| ; if (next == ~0) goto page_end mov r1, r2 ; p = next ldr r2, [r1] ; next ldr r3, [r1, #4] ; src ldr r4, [r1, #8] ; dst ldr r5, [r1, #12] ; sz cmp r3, r0 add r6, r4, r5 ; end address bne |page_memcpy4| ; if (src != ~0) goto page_memcpy4 mov r0, #0 |page_memset| ; memset (dst, 0, sz) uncached. str r0, [r4], #4 cmp r4, r6 blt |page_memset| b |page_loop| |page_memcpy4| ; memcpy (dst, src, sz) uncached. ldr r0, [r3], #4 ldr r5, [r3], #4 str r0, [r4], #4 cmp r4, r6 strlt r5, [r4], #4 cmplt r4, r6 blt |page_memcpy4| b |page_loop| |page_end| ; ; jump to kernel ; ; mov r0, #'E' ; bl btputc ; ldr r0, [r7] ; bl hexdump ; ldr r0, [r7] ; ldr r0, [r0] ; bl hexdump ; set stack pointer mov r5, #4096 add r6, r6, #8192 sub r5, r5, #1 bic sp, r6, r5 ; set bootargs ldr r4, [r7] ldr r0, [r7, #4] ldr r1, [r7, #8] ldr r2, [r7, #12] mov pc, r4 ; NOTREACHED |infinite_loop| nop nop nop nop nop b |infinite_loop| ENDP ; |boot| |btputc| PROC adr r1, |$UARTTXBSY| ldr r1, [r1] |btputc_busy| ldr r2, [r1] and r2, r2, #1 cmp r2, #1 beq |btputc_busy| adr r1, |$UARTTXADR| ldr r1, [r1] str r0, [r1] mov pc, lr ENDP ;|btputc| |hexdump| PROC stmea sp!, {r4-r5, lr} mov r4, r0 mov r0, #0x30 bl btputc mov r0, #0x78 bl btputc mov r0, r4 ; Transmit register address adr r1, |$UARTTXADR| ldr r1, [r1] ; Transmit busy register address adr r2, |$UARTTXBSY| ldr r2, [r2] mov r5, #8 |hex_loop| mov r3, r0, LSR #28 cmp r3, #9 addgt r3, r3, #0x41 - 10 addle r3, r3, #0x30 |hex_busyloop| ldr r4, [r2] and r4, r4, #1 cmp r4, #1 beq |hex_busyloop| str r3, [r1] mov r0, r0, LSL #4 subs r5, r5, #1 bne |hex_loop| mov r0, #0x0d bl btputc mov r0, #0x0a bl btputc ldmea sp!, {r4-r5, pc} ENDP ;|hexdump| |$UARTTXADR| DCD 0x80050014 |$UARTTXBSY| DCD 0x80050020 EXPORT |boot_func_end| [ DATA ] |boot_func_end| DCD 0x0 END @ 1.3.22.1 log @Sync with HEAD. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.3 2001/07/17 01:43:42 toshii Exp $ d37 1 a37 1 d45 1 a45 1 |dcachebuf| d49 1 a49 1 d86 1 a86 1 d98 1 a98 1 d110 1 a110 1 d116 1 a116 1 mcr p15, 0, r0, c7, c6, 0 d159 1 a159 1 d181 1 a181 1 EXPORT |SetCPSR| d214 1 a214 1 EXPORT |SetCop15Reg1| d222 3 a224 3 ; Reg2 Translation table base (R/W) EXPORT |GetCop15Reg2| d229 1 a229 1 EXPORT |SetCop15Reg2| d241 1 a241 1 EXPORT |SetCop15Reg3| d246 1 a246 1 d248 1 a248 1 EXPORT |GetCop15Reg5| d253 3 a255 3 ; Reg6 Fault address (R/W) EXPORT |GetCop15Reg6| d265 3 a267 3 ; Reg9 Read buffer operations (W) ; Reg13 Process ID (R/W) EXPORT |GetCop15Reg13| d272 1 a272 1 EXPORT |SetCop15Reg13| d277 1 a277 1 d279 1 a279 1 EXPORT |GetCop15Reg14| d285 1 a285 1 d291 1 a291 1 ; jump physical address of boot function d319 1 a319 1 ; d336 2 a337 2 ENDP ; |boot_func| d339 3 a341 3 |colorbar| PROC stmea sp!, {r4-r7, lr} adr r4, |$FBADDR| d343 1 a343 1 d349 1 a349 1 orr r6, r6, r6, LSL #8 d356 1 a356 1 d358 2 a359 2 bne |color_loop| d363 2 a364 2 ENDP ; |colorbar| d369 1 a369 1 ; d382 2 a383 2 ; mov r2, r5 ; start d386 1 a386 1 |page_loop| d390 1 a390 1 d396 1 a396 1 d401 1 a401 1 mov r0, #0 d407 1 a407 1 d421 1 a421 1 ; d443 1 a443 1 d452 1 a452 1 d482 1 a482 1 |hex_loop| d502 1 a502 1 d505 3 a507 3 |$UARTTXBSY| DCD 0x80050020 d509 1 a509 1 |boot_func_end| DCD 0x0 @ 1.3.22.2 log @Sync with HEAD. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.4 2004/08/06 18:33:09 uch Exp $ @ 1.3.22.3 log @Fix the sync with head I botched. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.3.22.1 2004/08/12 11:41:05 skrll Exp $ @ 1.2 log @Pass bootargs like usual function calls. Initialize sp register to more useful value. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.1 2001/02/09 18:34:49 uch Exp $ d288 1 a288 1 ; bootinfo boot infomation block address. @ 1.2.2.1 log @update to -current @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.3 2001/07/17 01:43:42 toshii Exp $ d288 1 a288 1 ; bootinfo boot information block address. @ 1.1 log @bootloader for SH3, SA-1100, TX39, VR41 based Windows CE(2.00 or later) @ text @d1 1 a1 1 ; $NetBSD$ d410 1 d413 2 d429 13 a441 3 ldr r0, [r7] mov pc, r0 @ 1.1.2.1 log @file arm.asm was added on branch thorpej_scsipi on 2001-02-11 19:09:57 +0000 @ text @d1 498 @ 1.1.2.2 log @Sync with HEAD. @ text @a0 498 ; $NetBSD: arm.asm,v 1.1.2.1 2001/02/11 19:09:57 bouyer Exp $ ; ; Copyright (c) 2001 The NetBSD Foundation, Inc. ; All rights reserved. ; ; This code is derived from software contributed to The NetBSD Foundation ; by UCHIYAMA Yasushi. ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions ; are met: ; 1. Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; 3. All advertising materials mentioning features or use of this software ; must display the following acknowledgement: ; This product includes software developed by the NetBSD ; Foundation, Inc. and its contributors. ; 4. Neither the name of The NetBSD Foundation nor the names of its ; contributors may be used to endorse or promote products derived ; from this software without specific prior written permission. ; ; THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS ; ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS ; BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ; ;armasm.exe $(InputPath) ;arm.obj ; ; dummy buffer for WritebackDCache EXPORT |dcachebuf| [DATA] AREA |.data|, DATA |dcachebuf| % 8192 ; D-cache size AREA |.text|, CODE, PIC ; ; Operation mode ops. ; EXPORT |SetSVCMode| |SetSVCMode| PROC mrs r0, cpsr bic r0, r0, #0x1f orr r0, r0, #0x13 msr cpsr, r0 mov pc, lr ENDP ; |SetSVCMode| EXPORT |SetSystemMode| |SetSystemMode| PROC mrs r0, cpsr orr r0, r0, #0x1f msr cpsr, r0 mov pc, lr ENDP ; |SetSystemMode| ; ; Interrupt ops. ; EXPORT |DI| |DI| PROC mrs r0, cpsr orr r0, r0, #0xc0 msr cpsr, r0 mov pc, lr ENDP ; |DI| EXPORT |EI| |EI| PROC mrs r0, cpsr bic r0, r0, #0xc0 msr cpsr, r0 mov pc, lr ENDP ; |EI| ; ; Cache ops. ; EXPORT |InvalidateICache| |InvalidateICache| PROC ; c7 (CRn) Cache Control Register ; c5, 0 (CRm, opcode_2) Flush I ; r0 (Rd) ignored mcr p15, 0, r0, c7, c5, 0 mov pc, lr ENDP ; |InvalidateICache| EXPORT |WritebackDCache| |WritebackDCache| PROC ldr r0, [pc, #16] ; dcachebuf add r1, r0, #8192 ; cache-size is 8Kbyte. |wbdc1| ldr r2, [r0], #32 ; line-size is 32byte. teq r1, r0 bne |wbdc1| mov pc, lr DCD |dcachebuf| ENDP ; |WritebackDCache| EXPORT |InvalidateDCache| |InvalidateDCache| PROC ; c7 (CRn) Cache Control Register ; c6, 0 (CRm, opcode_2) Flush D ; r0 (Rd) ignored mcr p15, 0, r0, c7, c6, 0 mov pc, lr ENDP ; |InvalidateDCache| EXPORT |WritebackInvalidateDCache| |WritebackInvalidateDCache| PROC ldr r0, [pc, #20] ; dcachebuf add r1, r0, #8192 |wbidc1| ldr r2, [r0], #32 teq r1, r0 bne |wbidc1| mcr p15, 0, r0, c7, c6, 0 mov pc, lr DCD |dcachebuf| ENDP ; |WritebackInvalidateDCache| ; ; WriteBuffer ops ; EXPORT |WritebufferFlush| |WritebufferFlush| PROC ; c7 (CRn) Cache Control Register ; c10, 4(CRm, opcode_2) Flush D ; r0 (Rd) ignored mcr p15, 0, r0, c7, c10, 4 mov pc, lr ENDP ; |WritebufferFlush| ; ; TLB ops. ; EXPORT |FlushIDTLB| |FlushIDTLB| PROC mcr p15, 0, r0, c8, c7, 0 mov pc, lr ENDP ; |FlushIDTLB| EXPORT |FlushITLB| |FlushITLB| PROC mcr p15, 0, r0, c8, c5, 0 mov pc, lr ENDP ; |FlushITLB| EXPORT |FlushDTLB| |FlushDTLB| PROC mcr p15, 0, r0, c8, c6, 0 mov pc, lr ENDP ; |FlushITLB| EXPORT |FlushDTLBS| |FlushDTLBS| PROC mcr p15, 0, r0, c8, c6, 1 mov pc, lr ENDP ; |FlushITLBS| ; ; CurrentProgramStatusRegister access. ; EXPORT |GetCPSR| |GetCPSR| PROC mrs r0, cpsr mov pc, lr ENDP ; |GetCPSR| EXPORT |SetCPSR| |SetCPSR| PROC msr cpsr, r0 mov pc, lr ENDP ; |SetCPSR| ; ; SA-1100 Coprocessor15 access. ; ; Reg0 ID (R) EXPORT |GetCop15Reg0| |GetCop15Reg0| PROC mrc p15, 0, r0, c0, c0, 0 ; 0x4401a119 (44|01 = version 4|A11 = SA1100|9 = E stepping) mov pc, lr ENDP ; |GetCop15Reg0| ; Reg1 Control (R/W) EXPORT |GetCop15Reg1| |GetCop15Reg1| PROC mrc p15, 0, r0, c1, c0, 0 ; 0xc007327f (||...........|||..||..|..|||||||) ; 0 (1)MMU enabled ; 1 (1)Address fault enabled ; 2 (1)D-cache enabled ; 3 (1)Write-buffer enabled ; 7 (0)little-endian ; 8 (0)MMU protection (System) ; 9 (1)MMU protection (ROM) ; 12 (1)I-cache enabled ; 13 (1)Base address of interrupt vector is 0xffff0000 mov pc, lr ENDP ; |GetCop15Reg1| EXPORT |SetCop15Reg1| |SetCop15Reg1| PROC mcr p15, 0, r0, c1, c0, 0 nop nop nop mov pc, lr ENDP ; |SetCop15Reg1| ; Reg2 Translation table base (R/W) EXPORT |GetCop15Reg2| |GetCop15Reg2| PROC mrc p15, 0, r0, c2, c0, 0 mov pc, lr ENDP ; |GetCop15Reg2| EXPORT |SetCop15Reg2| |SetCop15Reg2| PROC mcr p15, 0, r0, c2, c0, 0 mov pc, lr ENDP ; |SetCop15Reg2| ; Reg3 Domain access control (R/W) EXPORT |GetCop15Reg3| |GetCop15Reg3| PROC mrc p15, 0, r0, c3, c0, 0 mov pc, lr ENDP ; |GetCop15Reg3| EXPORT |SetCop15Reg3| |SetCop15Reg3| PROC mcr p15, 0, r0, c3, c0, 0 mov pc, lr ENDP ; |SetCop15Reg3| ; Reg5 Fault status (R/W) EXPORT |GetCop15Reg5| |GetCop15Reg5| PROC mrc p15, 0, r0, c5, c0, 0 mov pc, lr ENDP ; |GetCop15Reg5| ; Reg6 Fault address (R/W) EXPORT |GetCop15Reg6| |GetCop15Reg6| PROC mrc p15, 0, r0, c6, c0, 0 mov pc, lr ENDP ; |GetCop15Reg6| ; Reg7 Cache operations (W) ; -> Cache ops ; Reg8 TLB operations (Flush) (W) ; -> TLB ops ; Reg9 Read buffer operations (W) ; Reg13 Process ID (R/W) EXPORT |GetCop15Reg13| |GetCop15Reg13| PROC mrc p15, 0, r0, c13, c0, 0 mov pc, lr ENDP ; |GetCop15Reg13| EXPORT |SetCop15Reg13| |SetCop15Reg13| PROC mcr p15, 0, r0, c13, c0, 0 mov pc, lr ENDP ; |SetCop15Reg13| ; Reg14 Breakpoint (R/W) EXPORT |GetCop15Reg14| |GetCop15Reg14| PROC mrc p15, 0, r0, c14, c0, 0 mov pc, lr ENDP ; |GetCop15Reg14| ; Reg15 Test, clock, and idle (W) ; FlatJump (kaddr_t bootinfo, kaddr_t pvec, kaddr_t stack ; kaddr_t jump) ; bootinfo boot infomation block address. ; pvec page vector of kernel. ; stack physical address of stack ; jump physical address of boot function ; *** MMU and pipeline behavier are SA-1100 specific. *** EXPORT |FlatJump| |FlatJump| PROC ; disable interrupt mrs r4, cpsr orr r4, r4, #0xc0 msr cpsr, r4 ; disable MMU, I/D-Cache, Writebuffer. ; interrupt vector address is 0xffff0000 ; 32bit exception handler/address range. ldr r4, [pc, #24] ; Disable WB/Cache/MMU mcr p15, 0, r4, c1, c0, 0 ; Invalidate I/D-cache. mcr p15, 0, r4, c7, c7, 0 ; Fetch translated fetch ; Invalidate TLB entries. mcr p15, 0, r4, c8, c7, 0 ; Fetch translated decode ; jump to kernel entry physical address. mov pc, r3 ; Fetch translated execute ; NOTREACHED nop ; Fetch nontranslated cache access nop ; Fetch nontranslated writeback mov pc, lr ; Fetch nontranslated DCD 0x00002030 ENDP ; |FlatJump| ; ; UART test ; ; boot_func (u_int32_t mapaddr, u_int32_t bootinfo, u_int32_t flags) ; EXPORT |boot_func| |boot_func| PROC nop ; Cop15 hazard nop ; Cop15 hazard nop ; Cop15 hazard mov sp, r2 ; set bootloader stack ; mov r4, r0 ; mov r5, r1 ; bl colorbar ; mov r0, r4 ; mov r1, r5 bl boot nop ; NOTREACHED nop ENDP ; |boot_func| EXPORT |colorbar| |colorbar| PROC stmea sp!, {r4-r7, lr} adr r4, |$FBADDR| ldr r4, [r4] mov r7, #8 add r0, r0, r7 |color_loop| mov r6, r0 and r6, r6, #7 orr r6, r6, r6, LSL #8 orr r6, r6, r6, LSL #16 add r5, r4, #0x9600 |fb_loop| str r6, [r4], #4 cmp r4, r5 blt |fb_loop| subs r7, r7, #1 bne |color_loop| ldmea sp!, {r4-r7, pc} |$FBADDR| DCD 0xc0003000 ; use WindowsCE default. ENDP ; |colorbar| EXPORT |boot| |boot| PROC ; ; UART test code ; ; ; print boot_info address (r0) and page_vector start address (r1). ; mov r4, r0 ; mov r5, r1 ; mov r0, #'I' ; bl btputc ; mov r0, r4 ; bl hexdump ; mov r0, #'P' ; bl btputc ; mov r0, r5 ; bl hexdump ; mov r7, r4 ; mov r2, r5 ; start mov r7, r0 ; if enabled above debug print, remove this. mov r2, r1 ; if enabled above debug print, remove this. |page_loop| mvn r0, #0 ; ~0 cmp r2, r0 beq |page_end| ; if (next == ~0) goto page_end mov r1, r2 ; p = next ldr r2, [r1] ; next ldr r3, [r1, #4] ; src ldr r4, [r1, #8] ; dst ldr r5, [r1, #12] ; sz cmp r3, r0 add r6, r4, r5 ; end address bne |page_memcpy4| ; if (src != ~0) goto page_memcpy4 mov r0, #0 |page_memset| ; memset (dst, 0, sz) uncached. str r0, [r4], #4 cmp r4, r6 blt |page_memset| b |page_loop| |page_memcpy4| ; memcpy (dst, src, sz) uncached. ldr r0, [r3], #4 str r0, [r4], #4 cmp r4, r6 blt |page_memcpy4| b |page_loop| |page_end| ; ; jump to kernel ; ; mov r0, #'E' ; bl btputc ; ldr r0, [r7] ; bl hexdump ; ldr r0, [r7] ; ldr r0, [r0] ; bl hexdump ldr r0, [r7] mov pc, r0 ; NOTREACHED |infinite_loop| nop nop nop nop nop b |infinite_loop| ENDP ; |boot| |btputc| PROC adr r1, |$UARTTXBSY| ldr r1, [r1] |btputc_busy| ldr r2, [r1] and r2, r2, #1 cmp r2, #1 beq |btputc_busy| adr r1, |$UARTTXADR| ldr r1, [r1] str r0, [r1] mov pc, lr ENDP ;|btputc| |hexdump| PROC stmea sp!, {r4-r5, lr} mov r4, r0 mov r0, #0x30 bl btputc mov r0, #0x78 bl btputc mov r0, r4 ; Transmit register address adr r1, |$UARTTXADR| ldr r1, [r1] ; Transmit busy register address adr r2, |$UARTTXBSY| ldr r2, [r2] mov r5, #8 |hex_loop| mov r3, r0, LSR #28 cmp r3, #9 addgt r3, r3, #0x41 - 10 addle r3, r3, #0x30 |hex_busyloop| ldr r4, [r2] and r4, r4, #1 cmp r4, #1 beq |hex_busyloop| str r3, [r1] mov r0, r0, LSL #4 subs r5, r5, #1 bne |hex_loop| mov r0, #0x0d bl btputc mov r0, #0x0a bl btputc ldmea sp!, {r4-r5, pc} ENDP ;|hexdump| |$UARTTXADR| DCD 0x80050014 |$UARTTXBSY| DCD 0x80050020 EXPORT |boot_func_end| [ DATA ] |boot_func_end| DCD 0x0 END @ 1.1.2.3 log @Sync with HEAD. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.1.2.2 2001/03/27 15:30:49 bouyer Exp $ a409 1 ldr r5, [r3], #4 a411 2 strlt r5, [r4], #4 cmplt r4, r6 d426 3 a428 13 ; set stack pointer mov r5, #4096 add r6, r6, #8192 sub r5, r5, #1 bic sp, r6, r5 ; set bootargs ldr r4, [r7] ldr r0, [r7, #4] ldr r1, [r7, #8] ldr r2, [r7, #12] mov pc, r4 @ 1.1.4.1 log @Catch up with -current. @ text @d1 1 a1 1 ; $NetBSD: arm.asm,v 1.2 2001/03/23 08:48:12 toshii Exp $ a409 1 ldr r5, [r3], #4 a411 2 strlt r5, [r4], #4 cmplt r4, r6 d426 3 a428 13 ; set stack pointer mov r5, #4096 add r6, r6, #8192 sub r5, r5, #1 bic sp, r6, r5 ; set bootargs ldr r4, [r7] ldr r0, [r7, #4] ldr r1, [r7, #8] ldr r2, [r7, #12] mov pc, r4 @