head 1.2; access; symbols perseant-exfatfs-base-20250801:1.2 perseant-exfatfs-base-20240630:1.2 cjep_sun2x:1.2.0.24 cjep_sun2x-base:1.2 cjep_staticlib_x-base1:1.2 cjep_staticlib_x:1.2.0.22 cjep_staticlib_x-base:1.2 phil-wifi-20200421:1.2 phil-wifi-20200411:1.2 phil-wifi-20200406:1.2 pgoyette-compat-merge-20190127:1.2 pgoyette-compat-20190127:1.2 pgoyette-compat-20190118:1.2 pgoyette-compat-1226:1.2 pgoyette-compat-1126:1.2 pgoyette-compat-1020:1.2 pgoyette-compat-0930:1.2 pgoyette-compat-0906:1.2 pgoyette-compat-0728:1.2 pgoyette-compat-0625:1.2 pgoyette-compat-0521:1.2 pgoyette-compat-0502:1.2 pgoyette-compat-0422:1.2 pgoyette-compat-0415:1.2 pgoyette-compat-0407:1.2 pgoyette-compat-0330:1.2 pgoyette-compat-0322:1.2 pgoyette-compat-0315:1.2 pgoyette-compat:1.2.0.20 pgoyette-compat-base:1.2 perseant-stdc-iso10646:1.2.0.18 perseant-stdc-iso10646-base:1.2 prg-localcount2-base3:1.2 prg-localcount2-base2:1.2 prg-localcount2-base1:1.2 prg-localcount2:1.2.0.16 prg-localcount2-base:1.2 pgoyette-localcount-20170426:1.2 bouyer-socketcan-base1:1.2 pgoyette-localcount-20170320:1.2 bouyer-socketcan:1.2.0.14 bouyer-socketcan-base:1.2 pgoyette-localcount-20170107:1.2 pgoyette-localcount-20161104:1.2 localcount-20160914:1.2 pgoyette-localcount-20160806:1.2 pgoyette-localcount-20160726:1.2 pgoyette-localcount:1.2.0.12 pgoyette-localcount-base:1.2 netbsd-5-2-3-RELEASE:1.1.1.2 netbsd-5-1-5-RELEASE:1.1.1.2 yamt-pagecache-base9:1.2 yamt-pagecache-tag8:1.2 tls-earlyentropy:1.2.0.8 tls-earlyentropy-base:1.2 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.2 riastradh-drm2-base3:1.2 netbsd-5-2-2-RELEASE:1.1.1.2 netbsd-5-1-4-RELEASE:1.1.1.2 netbsd-5-2-1-RELEASE:1.1.1.2 netbsd-5-1-3-RELEASE:1.1.1.2 agc-symver:1.2.0.10 agc-symver-base:1.2 tls-maxphys-base:1.2 yamt-pagecache-base8:1.2 netbsd-5-2:1.1.1.2.0.38 yamt-pagecache-base7:1.2 netbsd-5-2-RELEASE:1.1.1.2 matt-nb6-plus-base:1.1.1.2 matt-nb6-plus:1.2.0.6 matt-nb6-plus-nbase:1.1.1.2 netbsd-5-2-RC1:1.1.1.2 yamt-pagecache-base6:1.2 yamt-pagecache-base5:1.2 yamt-pagecache-base4:1.2 netbsd-5-1-2-RELEASE:1.1.1.2 netbsd-5-1-1-RELEASE:1.1.1.2 yamt-pagecache-base3:1.2 yamt-pagecache-base2:1.2 yamt-pagecache:1.2.0.4 yamt-pagecache-base:1.2 bouyer-quota2-nbase:1.2 bouyer-quota2:1.2.0.2 bouyer-quota2-base:1.2 matt-nb5-mips64-premerge-20101231:1.1.1.2 matt-nb5-pq3:1.1.1.2.0.36 matt-nb5-pq3-base:1.1.1.2 netbsd-5-1:1.1.1.2.0.34 netbsd-5-1-RELEASE:1.1.1.2 netbsd-5-1-RC4:1.1.1.2 matt-nb5-mips64-k15:1.1.1.2 netbsd-5-1-RC3:1.1.1.2 netbsd-5-1-RC2:1.1.1.2 netbsd-5-1-RC1:1.1.1.2 netbsd-5-0-2-RELEASE:1.1.1.2 matt-nb5-mips64-premerge-20091211:1.1.1.2 matt-nb5-mips64-u2-k2-k4-k7-k8-k9:1.1.1.2 matt-nb4-mips64-k7-u2a-k9b:1.1.1.2 matt-nb5-mips64-u1-k1-k5:1.1.1.2 matt-nb5-mips64:1.1.1.2.0.32 netbsd-5-0-1-RELEASE:1.1.1.2 jym-xensuspend-nbase:1.1.1.2 netbsd-5-0:1.1.1.2.0.30 netbsd-5-0-RELEASE:1.1.1.2 netbsd-5-0-RC4:1.1.1.2 netbsd-5-0-RC3:1.1.1.2 netbsd-5-0-RC2:1.1.1.2 jym-xensuspend:1.1.1.2.0.28 jym-xensuspend-base:1.1.1.2 netbsd-5-0-RC1:1.1.1.2 netbsd-5:1.1.1.2.0.26 netbsd-5-base:1.1.1.2 matt-mips64-base2:1.1.1.2 matt-mips64:1.1.1.2.0.24 mjf-devfs2:1.1.1.2.0.22 mjf-devfs2-base:1.1.1.2 netbsd-4-0-1-RELEASE:1.1.1.2 wrstuden-revivesa-base-3:1.1.1.2 wrstuden-revivesa-base-2:1.1.1.2 wrstuden-fixsa-newbase:1.1.1.2 wrstuden-revivesa-base-1:1.1.1.2 yamt-pf42-base4:1.1.1.2 yamt-pf42-base3:1.1.1.2 hpcarm-cleanup-nbase:1.1.1.2 yamt-pf42-baseX:1.1.1.2 yamt-pf42-base2:1.1.1.2 wrstuden-revivesa:1.1.1.2.0.20 wrstuden-revivesa-base:1.1.1.2 yamt-pf42:1.1.1.2.0.18 yamt-pf42-base:1.1.1.2 keiichi-mipv6:1.1.1.2.0.16 keiichi-mipv6-base:1.1.1.2 matt-armv6-nbase:1.1.1.2 matt-armv6-prevmlocking:1.1.1.2 wrstuden-fixsa-base-1:1.1.1.2 netbsd-4-0:1.1.1.2.0.14 netbsd-4-0-RELEASE:1.1.1.2 cube-autoconf:1.1.1.2.0.12 cube-autoconf-base:1.1.1.2 netbsd-4-0-RC5:1.1.1.2 netbsd-4-0-RC4:1.1.1.2 netbsd-4-0-RC3:1.1.1.2 netbsd-4-0-RC2:1.1.1.2 netbsd-4-0-RC1:1.1.1.2 matt-armv6:1.1.1.2.0.10 matt-armv6-base:1.1.1.2 matt-mips64-base:1.1.1.2 hpcarm-cleanup:1.1.1.2.0.8 hpcarm-cleanup-base:1.1.1.2 netbsd-3-1-1-RELEASE:1.1.1.1 netbsd-3-0-3-RELEASE:1.1.1.1 wrstuden-fixsa:1.1.1.2.0.6 wrstuden-fixsa-base:1.1.1.2 abandoned-netbsd-4-base:1.1.1.2 abandoned-netbsd-4:1.1.1.2.0.2 netbsd-3-1:1.1.1.1.0.12 netbsd-3-1-RELEASE:1.1.1.1 netbsd-3-0-2-RELEASE:1.1.1.1 netbsd-3-1-RC4:1.1.1.1 netbsd-3-1-RC3:1.1.1.1 netbsd-3-1-RC2:1.1.1.1 netbsd-3-1-RC1:1.1.1.1 netbsd-4:1.1.1.2.0.4 netbsd-4-base:1.1.1.2 netbsd-3-0-1-RELEASE:1.1.1.1 binutils-2-16-1:1.1.1.2 netbsd-3-0:1.1.1.1.0.10 netbsd-3-0-RELEASE:1.1.1.1 netbsd-3-0-RC6:1.1.1.1 netbsd-3-0-RC5:1.1.1.1 netbsd-3-0-RC4:1.1.1.1 netbsd-3-0-RC3:1.1.1.1 netbsd-3-0-RC2:1.1.1.1 netbsd-3-0-RC1:1.1.1.1 netbsd-2-0-3-RELEASE:1.1.1.1 netbsd-2-1:1.1.1.1.0.8 netbsd-2-1-RELEASE:1.1.1.1 netbsd-2-1-RC6:1.1.1.1 netbsd-2-1-RC5:1.1.1.1 netbsd-2-1-RC4:1.1.1.1 netbsd-2-1-RC3:1.1.1.1 netbsd-2-1-RC2:1.1.1.1 netbsd-2-1-RC1:1.1.1.1 netbsd-2-0-2-RELEASE:1.1.1.1 netbsd-3:1.1.1.1.0.6 netbsd-3-base:1.1.1.1 netbsd-2-0-1-RELEASE:1.1.1.1 netbsd-2:1.1.1.1.0.4 netbsd-2-base:1.1.1.1 binutils-2-15-20041204:1.1.1.1 netbsd-2-0-RELEASE:1.1.1.1 netbsd-2-0-RC5:1.1.1.1 netbsd-2-0-RC4:1.1.1.1 netbsd-2-0-RC3:1.1.1.1 netbsd-2-0-RC2:1.1.1.1 netbsd-2-0-RC1:1.1.1.1 netbsd-2-0:1.1.1.1.0.2 netbsd-2-0-base:1.1.1.1 binutils-2-14:1.1.1.1 FSF:1.1.1; locks; strict; comment @# @; 1.2 date 2009.11.07.17.58.53; author skrll; state dead; branches 1.2.6.1; next 1.1; 1.1 date 2003.11.26.11.35.06; author mrg; state Exp; branches 1.1.1.1; next ; 1.2.6.1 date 2009.11.07.17.58.53; author matt; state dead; branches; next 1.2.6.2; 1.2.6.2 date 2012.11.20.18.42.19; author matt; state Exp; branches; next ; 1.1.1.1 date 2003.11.26.11.35.06; author mrg; state Exp; branches; next 1.1.1.2; 1.1.1.2 date 2006.02.02.20.59.29; author skrll; state Exp; branches; next ; desc @@ 1.2 log @Remove old binutils. @ text @@@c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. @@c This is part of the GAS manual. @@c For copying conditions, see the file as.texinfo. @@page @@node H8/500-Dependent @@chapter H8/500 Dependent Features @@cindex H8/500 support @@menu * H8/500 Options:: Options * H8/500 Syntax:: Syntax * H8/500 Floating Point:: Floating Point * H8/500 Directives:: H8/500 Machine Directives * H8/500 Opcodes:: Opcodes @@end menu @@node H8/500 Options @@section Options @@cindex H8/500 options (none) @@cindex options, H8/500 (none) @@code{@@value{AS}} has no additional command-line options for the Renesas (formerly Hitachi) H8/500 family. @@node H8/500 Syntax @@section Syntax @@menu * H8/500-Chars:: Special Characters * H8/500-Regs:: Register Names * H8/500-Addressing:: Addressing Modes @@end menu @@node H8/500-Chars @@subsection Special Characters @@cindex line comment character, H8/500 @@cindex H8/500 line comment character @@samp{!} is the line comment character. @@cindex line separator, H8/500 @@cindex statement separator, H8/500 @@cindex H8/500 line separator @@samp{;} can be used instead of a newline to separate statements. @@cindex symbol names, @@samp{$} in @@cindex @@code{$} in symbol names Since @@samp{$} has no special meaning, you may use it in symbol names. @@node H8/500-Regs @@subsection Register Names @@cindex H8/500 registers @@cindex registers, H8/500 You can use the predefined symbols @@samp{r0}, @@samp{r1}, @@samp{r2}, @@samp{r3}, @@samp{r4}, @@samp{r5}, @@samp{r6}, and @@samp{r7} to refer to the H8/500 registers. The H8/500 also has these control registers: @@table @@code @@item cp code pointer @@item dp data pointer @@item bp base pointer @@item tp stack top pointer @@item ep extra pointer @@item sr status register @@item ccr condition code register @@end table All registers are 16 bits long. To represent 32 bit numbers, use two adjacent registers; for distant memory addresses, use one of the segment pointers (@@code{cp} for the program counter; @@code{dp} for @@code{r0}--@@code{r3}; @@code{ep} for @@code{r4} and @@code{r5}; and @@code{tp} for @@code{r6} and @@code{r7}. @@node H8/500-Addressing @@subsection Addressing Modes @@cindex addressing modes, H8/500 @@cindex H8/500 addressing modes @@value{AS} understands the following addressing modes for the H8/500: @@table @@code @@item R@@var{n} Register direct @@item @@@@R@@var{n} Register indirect @@item @@@@(d:8, R@@var{n}) Register indirect with 8 bit signed displacement @@item @@@@(d:16, R@@var{n}) Register indirect with 16 bit signed displacement @@item @@@@-R@@var{n} Register indirect with pre-decrement @@item @@@@R@@var{n}+ Register indirect with post-increment @@item @@@@@@var{aa}:8 8 bit absolute address @@item @@@@@@var{aa}:16 16 bit absolute address @@item #@@var{xx}:8 8 bit immediate @@item #@@var{xx}:16 16 bit immediate @@end table @@node H8/500 Floating Point @@section Floating Point @@cindex floating point, H8/500 (@@sc{ieee}) @@cindex H8/500 floating point (@@sc{ieee}) The H8/500 family has no hardware floating point, but the @@code{.float} directive generates @@sc{ieee} floating-point numbers for compatibility with other development tools. @@node H8/500 Directives @@section H8/500 Machine Directives @@cindex H8/500 machine directives (none) @@cindex machine directives, H8/500 (none) @@cindex @@code{word} directive, H8/500 @@cindex @@code{int} directive, H8/500 @@code{@@value{AS}} has no machine-dependent directives for the H8/500. However, on this platform the @@samp{.int} and @@samp{.word} directives generate 16-bit numbers. @@node H8/500 Opcodes @@section Opcodes @@cindex H8/500 opcode summary @@cindex opcode summary, H8/500 @@cindex mnemonics, H8/500 @@cindex instruction summary, H8/500 For detailed information on the H8/500 machine instruction set, see @@cite{H8/500 Series Programming Manual} (Renesas M21T001). @@code{@@value{AS}} implements all the standard H8/500 opcodes. No additional pseudo-instructions are needed on this family. @@ifset SMALL @@c this table, due to the multi-col faking and hardcoded order, looks silly @@c except in smallbook. See comments below "@@set SMALL" near top of this file. The following table summarizes H8/500 opcodes and their operands: @@c Use @@group if it ever works, instead of @@page @@page @@smallexample @@i{Legend:} abs8 @@r{8-bit absolute address} abs16 @@r{16-bit absolute address} abs24 @@r{24-bit absolute address} crb @@r{@@code{ccr}, @@code{br}, @@code{ep}, @@code{dp}, @@code{tp}, @@code{dp}} disp8 @@r{8-bit displacement} ea @@r{@@code{rn}, @@code{@@@@rn}, @@code{@@@@(d:8, rn)}, @@code{@@@@(d:16, rn)},} @@r{@@code{@@@@-rn}, @@code{@@@@rn+}, @@code{@@@@aa:8}, @@code{@@@@aa:16},} @@r{@@code{#xx:8}, @@code{#xx:16}} ea_mem @@r{@@code{@@@@rn}, @@code{@@@@(d:8, rn)}, @@code{@@@@(d:16, rn)},} @@r{@@code{@@@@-rn}, @@code{@@@@rn+}, @@code{@@@@aa:8}, @@code{@@@@aa:16}} ea_noimm @@r{@@code{rn}, @@code{@@@@rn}, @@code{@@@@(d:8, rn)}, @@code{@@@@(d:16, rn)},} @@r{@@code{@@@@-rn}, @@code{@@@@rn+}, @@code{@@@@aa:8}, @@code{@@@@aa:16}} fp r6 imm4 @@r{4-bit immediate data} imm8 @@r{8-bit immediate data} imm16 @@r{16-bit immediate data} pcrel8 @@r{8-bit offset from program counter} pcrel16 @@r{16-bit offset from program counter} qim @@r{@@code{-2}, @@code{-1}, @@code{1}, @@code{2}} rd @@r{any register} rs @@r{a register distinct from rd} rlist @@r{comma-separated list of registers in parentheses;} @@r{register ranges @@code{rd-rs} are allowed} sp @@r{stack pointer (@@code{r7})} sr @@r{status register} sz @@r{size; @@samp{.b} or @@samp{.w}. If omitted, default @@samp{.w}} ldc[.b] ea,crb bcc[.w] pcrel16 ldc[.w] ea,sr bcc[.b] pcrel8 add[:q] sz qim,ea_noimm bhs[.w] pcrel16 add[:g] sz ea,rd bhs[.b] pcrel8 adds sz ea,rd bcs[.w] pcrel16 addx sz ea,rd bcs[.b] pcrel8 and sz ea,rd blo[.w] pcrel16 andc[.b] imm8,crb blo[.b] pcrel8 andc[.w] imm16,sr bne[.w] pcrel16 bpt bne[.b] pcrel8 bra[.w] pcrel16 beq[.w] pcrel16 bra[.b] pcrel8 beq[.b] pcrel8 bt[.w] pcrel16 bvc[.w] pcrel16 bt[.b] pcrel8 bvc[.b] pcrel8 brn[.w] pcrel16 bvs[.w] pcrel16 brn[.b] pcrel8 bvs[.b] pcrel8 bf[.w] pcrel16 bpl[.w] pcrel16 bf[.b] pcrel8 bpl[.b] pcrel8 bhi[.w] pcrel16 bmi[.w] pcrel16 bhi[.b] pcrel8 bmi[.b] pcrel8 bls[.w] pcrel16 bge[.w] pcrel16 bls[.b] pcrel8 bge[.b] pcrel8 @@page blt[.w] pcrel16 mov[:g][.b] imm8,ea_mem blt[.b] pcrel8 mov[:g][.w] imm16,ea_mem bgt[.w] pcrel16 movfpe[.b] ea,rd bgt[.b] pcrel8 movtpe[.b] rs,ea_noimm ble[.w] pcrel16 mulxu sz ea,rd ble[.b] pcrel8 neg sz ea bclr sz imm4,ea_noimm nop bclr sz rs,ea_noimm not sz ea bnot sz imm4,ea_noimm or sz ea,rd bnot sz rs,ea_noimm orc[.b] imm8,crb bset sz imm4,ea_noimm orc[.w] imm16,sr bset sz rs,ea_noimm pjmp abs24 bsr[.b] pcrel8 pjmp @@@@rd bsr[.w] pcrel16 pjsr abs24 btst sz imm4,ea_noimm pjsr @@@@rd btst sz rs,ea_noimm prtd imm8 clr sz ea prtd imm16 cmp[:e][.b] imm8,rd prts cmp[:i][.w] imm16,rd rotl sz ea cmp[:g].b imm8,ea_noimm rotr sz ea cmp[:g][.w] imm16,ea_noimm rotxl sz ea Cmp[:g] sz ea,rd rotxr sz ea dadd rs,rd rtd imm8 divxu sz ea,rd rtd imm16 dsub rs,rd rts exts[.b] rd scb/f rs,pcrel8 extu[.b] rd scb/ne rs,pcrel8 jmp @@@@rd scb/eq rs,pcrel8 jmp @@@@(imm8,rd) shal sz ea jmp @@@@(imm16,rd) shar sz ea jmp abs16 shll sz ea jsr @@@@rd shlr sz ea jsr @@@@(imm8,rd) sleep jsr @@@@(imm16,rd) stc[.b] crb,ea_noimm jsr abs16 stc[.w] sr,ea_noimm ldm @@@@sp+,(rlist) stm (rlist),@@@@-sp link fp,imm8 sub sz ea,rd link fp,imm16 subs sz ea,rd mov[:e][.b] imm8,rd subx sz ea,rd mov[:i][.w] imm16,rd swap[.b] rd mov[:l][.w] abs8,rd tas[.b] ea mov[:l].b abs8,rd trapa imm4 mov[:s][.w] rs,abs8 trap/vs mov[:s].b rs,abs8 tst sz ea mov[:f][.w] @@@@(disp8,fp),rd unlk fp mov[:f][.w] rs,@@@@(disp8,fp) xch[.w] rs,rd mov[:f].b @@@@(disp8,fp),rd xor sz ea,rd mov[:f].b rs,@@@@(disp8,fp) xorc.b imm8,crb mov[:g] sz rs,ea_mem xorc.w imm16,sr mov[:g] sz ea,rd @@end smallexample @@end ifset @ 1.2.6.1 log @file c-h8500.texi was added on branch matt-nb6-plus on 2012-11-20 18:42:19 +0000 @ text @d1 272 @ 1.2.6.2 log @Bring back GPL2 version of binutils. @ text @a0 273 @@c Copyright (C) 1991, 1992, 1993, 1994, 1995, 2003 @@c Free Software Foundation, Inc. @@c This is part of the GAS manual. @@c For copying conditions, see the file as.texinfo. @@page @@node H8/500-Dependent @@chapter H8/500 Dependent Features @@cindex H8/500 support @@menu * H8/500 Options:: Options * H8/500 Syntax:: Syntax * H8/500 Floating Point:: Floating Point * H8/500 Directives:: H8/500 Machine Directives * H8/500 Opcodes:: Opcodes @@end menu @@node H8/500 Options @@section Options @@cindex H8/500 options (none) @@cindex options, H8/500 (none) @@code{@@value{AS}} has no additional command-line options for the Renesas (formerly Hitachi) H8/500 family. @@node H8/500 Syntax @@section Syntax @@menu * H8/500-Chars:: Special Characters * H8/500-Regs:: Register Names * H8/500-Addressing:: Addressing Modes @@end menu @@node H8/500-Chars @@subsection Special Characters @@cindex line comment character, H8/500 @@cindex H8/500 line comment character @@samp{!} is the line comment character. @@cindex line separator, H8/500 @@cindex statement separator, H8/500 @@cindex H8/500 line separator @@samp{;} can be used instead of a newline to separate statements. @@cindex symbol names, @@samp{$} in @@cindex @@code{$} in symbol names Since @@samp{$} has no special meaning, you may use it in symbol names. @@node H8/500-Regs @@subsection Register Names @@cindex H8/500 registers @@cindex registers, H8/500 You can use the predefined symbols @@samp{r0}, @@samp{r1}, @@samp{r2}, @@samp{r3}, @@samp{r4}, @@samp{r5}, @@samp{r6}, and @@samp{r7} to refer to the H8/500 registers. The H8/500 also has these control registers: @@table @@code @@item cp code pointer @@item dp data pointer @@item bp base pointer @@item tp stack top pointer @@item ep extra pointer @@item sr status register @@item ccr condition code register @@end table All registers are 16 bits long. To represent 32 bit numbers, use two adjacent registers; for distant memory addresses, use one of the segment pointers (@@code{cp} for the program counter; @@code{dp} for @@code{r0}--@@code{r3}; @@code{ep} for @@code{r4} and @@code{r5}; and @@code{tp} for @@code{r6} and @@code{r7}. @@node H8/500-Addressing @@subsection Addressing Modes @@cindex addressing modes, H8/500 @@cindex H8/500 addressing modes @@value{AS} understands the following addressing modes for the H8/500: @@table @@code @@item R@@var{n} Register direct @@item @@@@R@@var{n} Register indirect @@item @@@@(d:8, R@@var{n}) Register indirect with 8 bit signed displacement @@item @@@@(d:16, R@@var{n}) Register indirect with 16 bit signed displacement @@item @@@@-R@@var{n} Register indirect with pre-decrement @@item @@@@R@@var{n}+ Register indirect with post-increment @@item @@@@@@var{aa}:8 8 bit absolute address @@item @@@@@@var{aa}:16 16 bit absolute address @@item #@@var{xx}:8 8 bit immediate @@item #@@var{xx}:16 16 bit immediate @@end table @@node H8/500 Floating Point @@section Floating Point @@cindex floating point, H8/500 (@@sc{ieee}) @@cindex H8/500 floating point (@@sc{ieee}) The H8/500 family has no hardware floating point, but the @@code{.float} directive generates @@sc{ieee} floating-point numbers for compatibility with other development tools. @@node H8/500 Directives @@section H8/500 Machine Directives @@cindex H8/500 machine directives (none) @@cindex machine directives, H8/500 (none) @@cindex @@code{word} directive, H8/500 @@cindex @@code{int} directive, H8/500 @@code{@@value{AS}} has no machine-dependent directives for the H8/500. However, on this platform the @@samp{.int} and @@samp{.word} directives generate 16-bit numbers. @@node H8/500 Opcodes @@section Opcodes @@cindex H8/500 opcode summary @@cindex opcode summary, H8/500 @@cindex mnemonics, H8/500 @@cindex instruction summary, H8/500 For detailed information on the H8/500 machine instruction set, see @@cite{H8/500 Series Programming Manual} (Renesas M21T001). @@code{@@value{AS}} implements all the standard H8/500 opcodes. No additional pseudo-instructions are needed on this family. @@ifset SMALL @@c this table, due to the multi-col faking and hardcoded order, looks silly @@c except in smallbook. See comments below "@@set SMALL" near top of this file. The following table summarizes H8/500 opcodes and their operands: @@c Use @@group if it ever works, instead of @@page @@page @@smallexample @@i{Legend:} abs8 @@r{8-bit absolute address} abs16 @@r{16-bit absolute address} abs24 @@r{24-bit absolute address} crb @@r{@@code{ccr}, @@code{br}, @@code{ep}, @@code{dp}, @@code{tp}, @@code{dp}} disp8 @@r{8-bit displacement} ea @@r{@@code{rn}, @@code{@@@@rn}, @@code{@@@@(d:8, rn)}, @@code{@@@@(d:16, rn)},} @@r{@@code{@@@@-rn}, @@code{@@@@rn+}, @@code{@@@@aa:8}, @@code{@@@@aa:16},} @@r{@@code{#xx:8}, @@code{#xx:16}} ea_mem @@r{@@code{@@@@rn}, @@code{@@@@(d:8, rn)}, @@code{@@@@(d:16, rn)},} @@r{@@code{@@@@-rn}, @@code{@@@@rn+}, @@code{@@@@aa:8}, @@code{@@@@aa:16}} ea_noimm @@r{@@code{rn}, @@code{@@@@rn}, @@code{@@@@(d:8, rn)}, @@code{@@@@(d:16, rn)},} @@r{@@code{@@@@-rn}, @@code{@@@@rn+}, @@code{@@@@aa:8}, @@code{@@@@aa:16}} fp r6 imm4 @@r{4-bit immediate data} imm8 @@r{8-bit immediate data} imm16 @@r{16-bit immediate data} pcrel8 @@r{8-bit offset from program counter} pcrel16 @@r{16-bit offset from program counter} qim @@r{@@code{-2}, @@code{-1}, @@code{1}, @@code{2}} rd @@r{any register} rs @@r{a register distinct from rd} rlist @@r{comma-separated list of registers in parentheses;} @@r{register ranges @@code{rd-rs} are allowed} sp @@r{stack pointer (@@code{r7})} sr @@r{status register} sz @@r{size; @@samp{.b} or @@samp{.w}. If omitted, default @@samp{.w}} ldc[.b] ea,crb bcc[.w] pcrel16 ldc[.w] ea,sr bcc[.b] pcrel8 add[:q] sz qim,ea_noimm bhs[.w] pcrel16 add[:g] sz ea,rd bhs[.b] pcrel8 adds sz ea,rd bcs[.w] pcrel16 addx sz ea,rd bcs[.b] pcrel8 and sz ea,rd blo[.w] pcrel16 andc[.b] imm8,crb blo[.b] pcrel8 andc[.w] imm16,sr bne[.w] pcrel16 bpt bne[.b] pcrel8 bra[.w] pcrel16 beq[.w] pcrel16 bra[.b] pcrel8 beq[.b] pcrel8 bt[.w] pcrel16 bvc[.w] pcrel16 bt[.b] pcrel8 bvc[.b] pcrel8 brn[.w] pcrel16 bvs[.w] pcrel16 brn[.b] pcrel8 bvs[.b] pcrel8 bf[.w] pcrel16 bpl[.w] pcrel16 bf[.b] pcrel8 bpl[.b] pcrel8 bhi[.w] pcrel16 bmi[.w] pcrel16 bhi[.b] pcrel8 bmi[.b] pcrel8 bls[.w] pcrel16 bge[.w] pcrel16 bls[.b] pcrel8 bge[.b] pcrel8 @@page blt[.w] pcrel16 mov[:g][.b] imm8,ea_mem blt[.b] pcrel8 mov[:g][.w] imm16,ea_mem bgt[.w] pcrel16 movfpe[.b] ea,rd bgt[.b] pcrel8 movtpe[.b] rs,ea_noimm ble[.w] pcrel16 mulxu sz ea,rd ble[.b] pcrel8 neg sz ea bclr sz imm4,ea_noimm nop bclr sz rs,ea_noimm not sz ea bnot sz imm4,ea_noimm or sz ea,rd bnot sz rs,ea_noimm orc[.b] imm8,crb bset sz imm4,ea_noimm orc[.w] imm16,sr bset sz rs,ea_noimm pjmp abs24 bsr[.b] pcrel8 pjmp @@@@rd bsr[.w] pcrel16 pjsr abs24 btst sz imm4,ea_noimm pjsr @@@@rd btst sz rs,ea_noimm prtd imm8 clr sz ea prtd imm16 cmp[:e][.b] imm8,rd prts cmp[:i][.w] imm16,rd rotl sz ea cmp[:g].b imm8,ea_noimm rotr sz ea cmp[:g][.w] imm16,ea_noimm rotxl sz ea Cmp[:g] sz ea,rd rotxr sz ea dadd rs,rd rtd imm8 divxu sz ea,rd rtd imm16 dsub rs,rd rts exts[.b] rd scb/f rs,pcrel8 extu[.b] rd scb/ne rs,pcrel8 jmp @@@@rd scb/eq rs,pcrel8 jmp @@@@(imm8,rd) shal sz ea jmp @@@@(imm16,rd) shar sz ea jmp abs16 shll sz ea jsr @@@@rd shlr sz ea jsr @@@@(imm8,rd) sleep jsr @@@@(imm16,rd) stc[.b] crb,ea_noimm jsr abs16 stc[.w] sr,ea_noimm ldm @@@@sp+,(rlist) stm (rlist),@@@@-sp link fp,imm8 sub sz ea,rd link fp,imm16 subs sz ea,rd mov[:e][.b] imm8,rd subx sz ea,rd mov[:i][.w] imm16,rd swap[.b] rd mov[:l][.w] abs8,rd tas[.b] ea mov[:l].b abs8,rd trapa imm4 mov[:s][.w] rs,abs8 trap/vs mov[:s].b rs,abs8 tst sz ea mov[:f][.w] @@@@(disp8,fp),rd unlk fp mov[:f][.w] rs,@@@@(disp8,fp) xch[.w] rs,rd mov[:f].b @@@@(disp8,fp),rd xor sz ea,rd mov[:f].b rs,@@@@(disp8,fp) xorc.b imm8,crb mov[:g] sz rs,ea_mem xorc.w imm16,sr mov[:g] sz ea,rd @@end smallexample @@end ifset @ 1.1 log @Initial revision @ text @@ 1.1.1.1 log @initial import of binutils 2.14 into gnu/dist/binutils. @ text @@ 1.1.1.2 log @Import binutils 2.16.1. @ text @d1 1 a1 2 @@c Copyright (C) 1991, 1992, 1993, 1994, 1995, 2003 @@c Free Software Foundation, Inc. @