head	1.1;
branch	1.1.1;
access;
symbols
	netbsd-11-0-RC4:1.1.1.3
	netbsd-11-0-RC3:1.1.1.3
	netbsd-11-0-RC2:1.1.1.3
	netbsd-11-0-RC1:1.1.1.3
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	pgoyette-localcount-base:1.1.1.1
	netbsd-7-0-1-RELEASE:1.1.1.1
	netbsd-7-0:1.1.1.1.0.10
	netbsd-7-0-RELEASE:1.1.1.1
	netbsd-7-0-RC3:1.1.1.1
	netbsd-7-0-RC2:1.1.1.1
	netbsd-7-0-RC1:1.1.1.1
	tls-maxphys-base:1.1.1.1
	tls-maxphys:1.1.1.1.0.8
	netbsd-7:1.1.1.1.0.6
	netbsd-7-base:1.1.1.1
	yamt-pagecache:1.1.1.1.0.4
	yamt-pagecache-base9:1.1.1.1
	tls-earlyentropy:1.1.1.1.0.2
	tls-earlyentropy-base:1.1.1.1
	riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.1.1.1
	riastradh-drm2-base3:1.1.1.1
	gmp-5-1-3:1.1.1.1
	gmp:1.1.1;
locks; strict;
comment	@;; @;


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desc
@@


1.1
log
@Initial revision
@
text
@dnl  AMD64 mpn_lshiftc optimised for CPUs with fast SSE.

dnl  Contributed to the GNU project by David Harvey and Torbjorn Granlund.

dnl  Copyright 2010, 2011, 2012 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')


C	     cycles/limb	     cycles/limb	      good
C          16-byte aligned         16-byte unaligned	    for cpu?
C AMD K8,K9	 ?			 ?
C AMD K10	 1.85  (1.635)		 1.9   (1.67)		Y
C AMD bd1	 1.82  (1.75)		 1.82  (1.75)		Y
C AMD bobcat	 4.5			 4.5
C Intel P4	 3.6   (3.125)		 3.6   (3.125)		Y
C Intel core2	 2.05  (1.67)		 2.55  (1.75)
C Intel NHM	 2.05  (1.875)		 2.6   (2.25)
C Intel SBR	 1.55  (1.44)		 2     (1.57)		Y
C Intel atom	 ?			 ?
C VIA nano	 2.5   (2.5)		 2.5   (2.5)		Y

C We try to do as many 16-byte operations as possible.  The top-most and
C bottom-most writes might need 8-byte operations.  We always write using
C 16-byte operations, we read with both 8-byte and 16-byte operations.

C There are two inner-loops, one for when rp = ap (mod 16) and one when this is
C not true.  The aligned case reads 16+8 bytes, the unaligned case reads
C 16+8+X bytes, where X is 8 or 16 depending on how punpcklqdq is implemented.

C This is not yet great code:
C   (1) The unaligned case makes too many reads.
C   (2) We should do some unrolling, at least 2-way.
C With 2-way unrolling but no scheduling we reach 1.5 c/l on K10 and 2 c/l on
C Nano.

C INPUT PARAMETERS
define(`rp',  `%rdi')
define(`ap',  `%rsi')
define(`n',   `%rdx')
define(`cnt', `%rcx')

ASM_START()
	TEXT
	ALIGN(16)
PROLOGUE(mpn_lshiftc)
	movd	R32(%rcx), %xmm4
	mov	$64, R32(%rax)
	sub	R32(%rcx), R32(%rax)
	movd	R32(%rax), %xmm5

	neg	R32(%rcx)
	mov	-8(ap,n,8), %rax
	shr	R8(%rcx), %rax

	pcmpeqb	%xmm7, %xmm7		C set to 111...111

	cmp	$2, n
	jle	L(le2)

	lea	(rp,n,8), R32(%rcx)
	test	$8, R8(%rcx)
	je	L(rp_aligned)

C Do one initial limb in order to make rp aligned
	movq	-8(ap,n,8), %xmm0
	movq	-16(ap,n,8), %xmm1
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movq	%xmm0, -8(rp,n,8)
	dec	n

L(rp_aligned):
	lea	(ap,n,8), R32(%rcx)
	test	$8, R8(%rcx)
	je	L(aent)
	jmp	L(uent)
C *****************************************************************************

C Handle the case when ap != rp (mod 16).

	ALIGN(16)
L(utop):movq	(ap,n,8), %xmm1
	punpcklqdq  8(ap,n,8), %xmm1
	movdqa	-8(ap,n,8), %xmm0
	psllq	%xmm4, %xmm1
	psrlq	%xmm5, %xmm0
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp,n,8)
L(uent):sub	$2, n
	ja	L(utop)

	jne	L(end8)

	movq	(ap), %xmm1
	pxor	%xmm0, %xmm0
	punpcklqdq  %xmm1, %xmm0
	punpcklqdq  8(ap), %xmm1
	psllq	%xmm4, %xmm1
	psrlq	%xmm5, %xmm0
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp)
	ret
C *****************************************************************************

C Handle the case when ap = rp (mod 16).

	ALIGN(16)
L(atop):movdqa	(ap,n,8), %xmm0		C xmm0 = B*ap[n-1] + ap[n-2]
	movq	-8(ap,n,8), %xmm1	C xmm1 = ap[n-3]
	punpcklqdq  %xmm0, %xmm1	C xmm1 = B*ap[n-2] + ap[n-3]
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp,n,8)
L(aent):sub	$2, n
	ja	L(atop)

	jne	L(end8)

	movdqa	(ap), %xmm0
	pxor	%xmm1, %xmm1
	punpcklqdq  %xmm0, %xmm1
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp)
	ret
C *****************************************************************************

	ALIGN(16)
L(le2):	jne	L(end8)

	movq	8(ap), %xmm0
	movq	(ap), %xmm1
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movq	%xmm0, 8(rp)

L(end8):movq	(ap), %xmm0
	psllq	%xmm4, %xmm0
	pxor	%xmm7, %xmm0
	movq	%xmm0, (rp)
	ret
EPILOGUE()
@


1.1.1.1
log
@initial import GMP 5.1.3 sources.  changes include:

fixes for:
- mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec
- mpz_powm_ui
- AMD family 11h
- mpz_powm_sec and mpn_powm_sec
- ASSERT() fixes
- gcd, gcdext, and invert function fixes
- some PPC division operations
@
text
@@


1.1.1.2
log
@initial import of GMP 6.1.2.  main changes from 5.1.3 below.

notes:
 - support for thumb-less ARM chips was in our port of 5.1.3, but a
   similar method has been provided upstream now
 - someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

  FEATURES
  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
    on Skylake Pentiums).
  * Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

  BUGS FIXED
  * The public function mpn_com is now correctly declared in gmp.h.
  * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
    some obsolete CPUs.
  * Various problems related to precision for mpf have been fixed.
  * Fixed ABI incompatible stack alignment in calls from assembly code.
  * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
  SPEEDUPS
  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    new ADX instructions.
  * Square root is now faster when the remainder is not needed. Also the speed
    to compute the k-th root improved, for small sizes.
  FEATURES
  * New C++ functions gcd and lcm for mpz_class.
  * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
  * New public mpq_cmp_z function, to efficiently compare rationals with
    integers.
  * Support for more 32-bit arm processors.
  * Support for AVX-less modern x86 CPUs. (Such support might be missing either
    because the CPU vendor chose to disable AVX, or because the running kernel
    lacks AVX context switch support.)
  * Support for NetBSD under Xen; we switch off AVX unconditionally under
    NetBSD since a bug in NetBSD makes AVX fail under Xen.
  MISC
  * Tuned values for FFT multiplications are provided for larger number on
    many platforms.

Changes between GMP version 5.1.* and 6.0.0
  BUGS FIXED
  * The function mpz_invert now considers any number invertible in Z/1Z.
  * The mpn multiply code now handles operands of more than 2^31 limbs
    correctly.  (Note however that the mpz code is limited to 2^32 bits on
    32-bit hosts and 2^37 bits on 64-bit hosts.)
  SPEEDUPS
  * Plain division of large operands is faster and more monotonous in operand
    size.
  * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
    assembly.
  * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
    and vastly expanded assembly support.  Speedup also for the older Core 2
    and Nehalem.
  * Faster mixed arithmetic between mpq_class and double.
  FEATURES
  * Support for new Intel and AMD CPUs.
  * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
    silent multiplication and squaring.
  * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
    side-channel silent division.
  * New public functions mpn_cnd_add_n and mpn_cnd_sub_n.  Side-channel silent
    conditional addition and subtraction.
  * New public function mpn_sec_powm, implementing side-channel silent modexp.
  * New public function mpn_sec_invert, implementing side-channel silent
    modular inversion.
  * Better support for applications which use the mpz_t type, but nevertheless
    need to call some of the lower-level mpn functions.  See the documentation
    for mpz_limbs_read and related functions.
@
text
@d5 1
a5 1
dnl  Copyright 2010-2012 Free Software Foundation, Inc.
d8 1
a8 1
dnl
d10 4
a13 14
dnl  it under the terms of either:
dnl
dnl    * the GNU Lesser General Public License as published by the Free
dnl      Software Foundation; either version 3 of the License, or (at your
dnl      option) any later version.
dnl
dnl  or
dnl
dnl    * the GNU General Public License as published by the Free Software
dnl      Foundation; either version 2 of the License, or (at your option) any
dnl      later version.
dnl
dnl  or both in parallel, as here.
dnl
d16 5
a20 6
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
dnl  for more details.
dnl
dnl  You should have received copies of the GNU General Public License and the
dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
dnl  see https://www.gnu.org/licenses/.
@


1.1.1.3
log
@initial import of GMP 6.2.0.  changes include:

- Bug fixes to gmp_snprintf, conversion to double, mpz_powm,
  and mpf_set_str.
- New functions for factorial, primorial, fibonacci, mpz_2fac_ui,
  and mpz_mfac_uiui.
- MIPS r6 cores are now supported.
- Various speeds ups.
@
text
@d5 1
a5 1
dnl  Copyright 2010-2012, 2018 Free Software Foundation, Inc.
a72 1
	FUNC_ENTRY(4)
d82 1
a82 1
	pcmpeqb	%xmm2, %xmm2		C set to 111...111
d97 1
a97 1
	pxor	%xmm2, %xmm0
d117 1
a117 1
	pxor	%xmm2, %xmm0
d131 1
a131 1
	pxor	%xmm2, %xmm0
a132 1
	FUNC_EXIT()
d145 1
a145 1
	pxor	%xmm2, %xmm0
d158 1
a158 1
	pxor	%xmm2, %xmm0
a159 1
	FUNC_EXIT()
d171 1
a171 1
	pxor	%xmm2, %xmm0
d176 1
a176 1
	pxor	%xmm2, %xmm0
a177 1
	FUNC_EXIT()
@


1.1.1.1.8.1
log
@file lshiftc.asm was added on branch tls-maxphys on 2014-08-19 23:59:56 +0000
@
text
@d1 168
@


1.1.1.1.8.2
log
@Rebase to HEAD as of a few days ago.
@
text
@a0 168
dnl  AMD64 mpn_lshiftc optimised for CPUs with fast SSE.

dnl  Contributed to the GNU project by David Harvey and Torbjorn Granlund.

dnl  Copyright 2010, 2011, 2012 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')


C	     cycles/limb	     cycles/limb	      good
C          16-byte aligned         16-byte unaligned	    for cpu?
C AMD K8,K9	 ?			 ?
C AMD K10	 1.85  (1.635)		 1.9   (1.67)		Y
C AMD bd1	 1.82  (1.75)		 1.82  (1.75)		Y
C AMD bobcat	 4.5			 4.5
C Intel P4	 3.6   (3.125)		 3.6   (3.125)		Y
C Intel core2	 2.05  (1.67)		 2.55  (1.75)
C Intel NHM	 2.05  (1.875)		 2.6   (2.25)
C Intel SBR	 1.55  (1.44)		 2     (1.57)		Y
C Intel atom	 ?			 ?
C VIA nano	 2.5   (2.5)		 2.5   (2.5)		Y

C We try to do as many 16-byte operations as possible.  The top-most and
C bottom-most writes might need 8-byte operations.  We always write using
C 16-byte operations, we read with both 8-byte and 16-byte operations.

C There are two inner-loops, one for when rp = ap (mod 16) and one when this is
C not true.  The aligned case reads 16+8 bytes, the unaligned case reads
C 16+8+X bytes, where X is 8 or 16 depending on how punpcklqdq is implemented.

C This is not yet great code:
C   (1) The unaligned case makes too many reads.
C   (2) We should do some unrolling, at least 2-way.
C With 2-way unrolling but no scheduling we reach 1.5 c/l on K10 and 2 c/l on
C Nano.

C INPUT PARAMETERS
define(`rp',  `%rdi')
define(`ap',  `%rsi')
define(`n',   `%rdx')
define(`cnt', `%rcx')

ASM_START()
	TEXT
	ALIGN(16)
PROLOGUE(mpn_lshiftc)
	movd	R32(%rcx), %xmm4
	mov	$64, R32(%rax)
	sub	R32(%rcx), R32(%rax)
	movd	R32(%rax), %xmm5

	neg	R32(%rcx)
	mov	-8(ap,n,8), %rax
	shr	R8(%rcx), %rax

	pcmpeqb	%xmm7, %xmm7		C set to 111...111

	cmp	$2, n
	jle	L(le2)

	lea	(rp,n,8), R32(%rcx)
	test	$8, R8(%rcx)
	je	L(rp_aligned)

C Do one initial limb in order to make rp aligned
	movq	-8(ap,n,8), %xmm0
	movq	-16(ap,n,8), %xmm1
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movq	%xmm0, -8(rp,n,8)
	dec	n

L(rp_aligned):
	lea	(ap,n,8), R32(%rcx)
	test	$8, R8(%rcx)
	je	L(aent)
	jmp	L(uent)
C *****************************************************************************

C Handle the case when ap != rp (mod 16).

	ALIGN(16)
L(utop):movq	(ap,n,8), %xmm1
	punpcklqdq  8(ap,n,8), %xmm1
	movdqa	-8(ap,n,8), %xmm0
	psllq	%xmm4, %xmm1
	psrlq	%xmm5, %xmm0
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp,n,8)
L(uent):sub	$2, n
	ja	L(utop)

	jne	L(end8)

	movq	(ap), %xmm1
	pxor	%xmm0, %xmm0
	punpcklqdq  %xmm1, %xmm0
	punpcklqdq  8(ap), %xmm1
	psllq	%xmm4, %xmm1
	psrlq	%xmm5, %xmm0
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp)
	ret
C *****************************************************************************

C Handle the case when ap = rp (mod 16).

	ALIGN(16)
L(atop):movdqa	(ap,n,8), %xmm0		C xmm0 = B*ap[n-1] + ap[n-2]
	movq	-8(ap,n,8), %xmm1	C xmm1 = ap[n-3]
	punpcklqdq  %xmm0, %xmm1	C xmm1 = B*ap[n-2] + ap[n-3]
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp,n,8)
L(aent):sub	$2, n
	ja	L(atop)

	jne	L(end8)

	movdqa	(ap), %xmm0
	pxor	%xmm1, %xmm1
	punpcklqdq  %xmm0, %xmm1
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp)
	ret
C *****************************************************************************

	ALIGN(16)
L(le2):	jne	L(end8)

	movq	8(ap), %xmm0
	movq	(ap), %xmm1
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movq	%xmm0, 8(rp)

L(end8):movq	(ap), %xmm0
	psllq	%xmm4, %xmm0
	pxor	%xmm7, %xmm0
	movq	%xmm0, (rp)
	ret
EPILOGUE()
@


1.1.1.1.4.1
log
@file lshiftc.asm was added on branch yamt-pagecache on 2014-05-22 14:09:07 +0000
@
text
@d1 168
@


1.1.1.1.4.2
log
@sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")
@
text
@a0 168
dnl  AMD64 mpn_lshiftc optimised for CPUs with fast SSE.

dnl  Contributed to the GNU project by David Harvey and Torbjorn Granlund.

dnl  Copyright 2010, 2011, 2012 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')


C	     cycles/limb	     cycles/limb	      good
C          16-byte aligned         16-byte unaligned	    for cpu?
C AMD K8,K9	 ?			 ?
C AMD K10	 1.85  (1.635)		 1.9   (1.67)		Y
C AMD bd1	 1.82  (1.75)		 1.82  (1.75)		Y
C AMD bobcat	 4.5			 4.5
C Intel P4	 3.6   (3.125)		 3.6   (3.125)		Y
C Intel core2	 2.05  (1.67)		 2.55  (1.75)
C Intel NHM	 2.05  (1.875)		 2.6   (2.25)
C Intel SBR	 1.55  (1.44)		 2     (1.57)		Y
C Intel atom	 ?			 ?
C VIA nano	 2.5   (2.5)		 2.5   (2.5)		Y

C We try to do as many 16-byte operations as possible.  The top-most and
C bottom-most writes might need 8-byte operations.  We always write using
C 16-byte operations, we read with both 8-byte and 16-byte operations.

C There are two inner-loops, one for when rp = ap (mod 16) and one when this is
C not true.  The aligned case reads 16+8 bytes, the unaligned case reads
C 16+8+X bytes, where X is 8 or 16 depending on how punpcklqdq is implemented.

C This is not yet great code:
C   (1) The unaligned case makes too many reads.
C   (2) We should do some unrolling, at least 2-way.
C With 2-way unrolling but no scheduling we reach 1.5 c/l on K10 and 2 c/l on
C Nano.

C INPUT PARAMETERS
define(`rp',  `%rdi')
define(`ap',  `%rsi')
define(`n',   `%rdx')
define(`cnt', `%rcx')

ASM_START()
	TEXT
	ALIGN(16)
PROLOGUE(mpn_lshiftc)
	movd	R32(%rcx), %xmm4
	mov	$64, R32(%rax)
	sub	R32(%rcx), R32(%rax)
	movd	R32(%rax), %xmm5

	neg	R32(%rcx)
	mov	-8(ap,n,8), %rax
	shr	R8(%rcx), %rax

	pcmpeqb	%xmm7, %xmm7		C set to 111...111

	cmp	$2, n
	jle	L(le2)

	lea	(rp,n,8), R32(%rcx)
	test	$8, R8(%rcx)
	je	L(rp_aligned)

C Do one initial limb in order to make rp aligned
	movq	-8(ap,n,8), %xmm0
	movq	-16(ap,n,8), %xmm1
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movq	%xmm0, -8(rp,n,8)
	dec	n

L(rp_aligned):
	lea	(ap,n,8), R32(%rcx)
	test	$8, R8(%rcx)
	je	L(aent)
	jmp	L(uent)
C *****************************************************************************

C Handle the case when ap != rp (mod 16).

	ALIGN(16)
L(utop):movq	(ap,n,8), %xmm1
	punpcklqdq  8(ap,n,8), %xmm1
	movdqa	-8(ap,n,8), %xmm0
	psllq	%xmm4, %xmm1
	psrlq	%xmm5, %xmm0
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp,n,8)
L(uent):sub	$2, n
	ja	L(utop)

	jne	L(end8)

	movq	(ap), %xmm1
	pxor	%xmm0, %xmm0
	punpcklqdq  %xmm1, %xmm0
	punpcklqdq  8(ap), %xmm1
	psllq	%xmm4, %xmm1
	psrlq	%xmm5, %xmm0
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp)
	ret
C *****************************************************************************

C Handle the case when ap = rp (mod 16).

	ALIGN(16)
L(atop):movdqa	(ap,n,8), %xmm0		C xmm0 = B*ap[n-1] + ap[n-2]
	movq	-8(ap,n,8), %xmm1	C xmm1 = ap[n-3]
	punpcklqdq  %xmm0, %xmm1	C xmm1 = B*ap[n-2] + ap[n-3]
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp,n,8)
L(aent):sub	$2, n
	ja	L(atop)

	jne	L(end8)

	movdqa	(ap), %xmm0
	pxor	%xmm1, %xmm1
	punpcklqdq  %xmm0, %xmm1
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movdqa	%xmm0, (rp)
	ret
C *****************************************************************************

	ALIGN(16)
L(le2):	jne	L(end8)

	movq	8(ap), %xmm0
	movq	(ap), %xmm1
	psllq	%xmm4, %xmm0
	psrlq	%xmm5, %xmm1
	por	%xmm1, %xmm0
	pxor	%xmm7, %xmm0
	movq	%xmm0, 8(rp)

L(end8):movq	(ap), %xmm0
	psllq	%xmm4, %xmm0
	pxor	%xmm7, %xmm0
	movq	%xmm0, (rp)
	ret
EPILOGUE()
@