head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.2 netbsd-11-0-RC3:1.1.1.2 netbsd-11-0-RC2:1.1.1.2 netbsd-11-0-RC1:1.1.1.2 perseant-exfatfs-base-20250801:1.1.1.2 netbsd-11:1.1.1.2.0.18 netbsd-11-base:1.1.1.2 netbsd-10-1-RELEASE:1.1.1.2 perseant-exfatfs-base-20240630:1.1.1.2 perseant-exfatfs:1.1.1.2.0.16 perseant-exfatfs-base:1.1.1.2 netbsd-8-3-RELEASE:1.1.1.1 netbsd-9-4-RELEASE:1.1.1.2 netbsd-10-0-RELEASE:1.1.1.2 netbsd-10-0-RC6:1.1.1.2 netbsd-10-0-RC5:1.1.1.2 netbsd-10-0-RC4:1.1.1.2 netbsd-10-0-RC3:1.1.1.2 netbsd-10-0-RC2:1.1.1.2 netbsd-10-0-RC1:1.1.1.2 netbsd-10:1.1.1.2.0.14 netbsd-10-base:1.1.1.2 netbsd-9-3-RELEASE:1.1.1.2 gmp-6-2-1:1.1.1.2 cjep_sun2x-base1:1.1.1.2 cjep_sun2x:1.1.1.2.0.12 cjep_sun2x-base:1.1.1.2 cjep_staticlib_x-base1:1.1.1.2 netbsd-9-2-RELEASE:1.1.1.2 cjep_staticlib_x:1.1.1.2.0.10 cjep_staticlib_x-base:1.1.1.2 netbsd-9-1-RELEASE:1.1.1.2 gmp-6-2-0:1.1.1.2 phil-wifi-20200421:1.1.1.2 phil-wifi-20200411:1.1.1.2 is-mlppp:1.1.1.2.0.8 is-mlppp-base:1.1.1.2 phil-wifi-20200406:1.1.1.2 netbsd-8-2-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.2 netbsd-9-0-RC2:1.1.1.2 netbsd-9-0-RC1:1.1.1.2 phil-wifi-20191119:1.1.1.2 netbsd-9:1.1.1.2.0.6 netbsd-9-base:1.1.1.2 phil-wifi-20190609:1.1.1.2 netbsd-8-1-RELEASE:1.1.1.1 netbsd-8-1-RC1:1.1.1.1 pgoyette-compat-merge-20190127:1.1.1.2 pgoyette-compat-20190127:1.1.1.2 pgoyette-compat-20190118:1.1.1.2 pgoyette-compat-1226:1.1.1.2 pgoyette-compat-1126:1.1.1.2 pgoyette-compat-1020:1.1.1.2 pgoyette-compat-0930:1.1.1.2 pgoyette-compat-0906:1.1.1.2 netbsd-7-2-RELEASE:1.1.1.1 pgoyette-compat-0728:1.1.1.2 netbsd-8-0-RELEASE:1.1.1.1 phil-wifi:1.1.1.2.0.4 phil-wifi-base:1.1.1.2 pgoyette-compat-0625:1.1.1.2 netbsd-8-0-RC2:1.1.1.1 pgoyette-compat-0521:1.1.1.2 pgoyette-compat-0502:1.1.1.2 pgoyette-compat-0422:1.1.1.2 netbsd-8-0-RC1:1.1.1.1 pgoyette-compat-0415:1.1.1.2 pgoyette-compat-0407:1.1.1.2 pgoyette-compat-0330:1.1.1.2 pgoyette-compat-0322:1.1.1.2 pgoyette-compat-0315:1.1.1.2 netbsd-7-1-2-RELEASE:1.1.1.1 pgoyette-compat:1.1.1.2.0.2 pgoyette-compat-base:1.1.1.2 netbsd-7-1-1-RELEASE:1.1.1.1 matt-nb8-mediatek:1.1.1.1.0.26 matt-nb8-mediatek-base:1.1.1.1 gmp-6-1-2:1.1.1.2 perseant-stdc-iso10646:1.1.1.1.0.24 perseant-stdc-iso10646-base:1.1.1.1 netbsd-8:1.1.1.1.0.22 netbsd-8-base:1.1.1.1 prg-localcount2-base3:1.1.1.1 prg-localcount2-base2:1.1.1.1 prg-localcount2-base1:1.1.1.1 prg-localcount2:1.1.1.1.0.20 prg-localcount2-base:1.1.1.1 pgoyette-localcount-20170426:1.1.1.1 bouyer-socketcan-base1:1.1.1.1 pgoyette-localcount-20170320:1.1.1.1 netbsd-7-1:1.1.1.1.0.18 netbsd-7-1-RELEASE:1.1.1.1 netbsd-7-1-RC2:1.1.1.1 netbsd-7-nhusb-base-20170116:1.1.1.1 bouyer-socketcan:1.1.1.1.0.16 bouyer-socketcan-base:1.1.1.1 pgoyette-localcount-20170107:1.1.1.1 netbsd-7-1-RC1:1.1.1.1 pgoyette-localcount-20161104:1.1.1.1 netbsd-7-0-2-RELEASE:1.1.1.1 localcount-20160914:1.1.1.1 netbsd-7-nhusb:1.1.1.1.0.14 netbsd-7-nhusb-base:1.1.1.1 pgoyette-localcount-20160806:1.1.1.1 pgoyette-localcount-20160726:1.1.1.1 pgoyette-localcount:1.1.1.1.0.12 pgoyette-localcount-base:1.1.1.1 netbsd-7-0-1-RELEASE:1.1.1.1 netbsd-7-0:1.1.1.1.0.10 netbsd-7-0-RELEASE:1.1.1.1 netbsd-7-0-RC3:1.1.1.1 netbsd-7-0-RC2:1.1.1.1 netbsd-7-0-RC1:1.1.1.1 tls-maxphys-base:1.1.1.1 tls-maxphys:1.1.1.1.0.8 netbsd-7:1.1.1.1.0.6 netbsd-7-base:1.1.1.1 yamt-pagecache:1.1.1.1.0.4 yamt-pagecache-base9:1.1.1.1 tls-earlyentropy:1.1.1.1.0.2 tls-earlyentropy-base:1.1.1.1 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.1.1.1 riastradh-drm2-base3:1.1.1.1 gmp-5-1-3:1.1.1.1 gmp:1.1.1; locks; strict; comment @;; @; 1.1 date 2013.11.29.07.49.48; author mrg; state Exp; branches 1.1.1.1; next ; commitid L2Av4PuGmdoL39fx; 1.1.1.1 date 2013.11.29.07.49.48; author mrg; state Exp; branches 1.1.1.1.4.1 1.1.1.1.8.1; next 1.1.1.2; commitid L2Av4PuGmdoL39fx; 1.1.1.2 date 2017.08.22.09.40.49; author mrg; state Exp; branches; next ; commitid W5kmAIk8hwVpSb4A; 1.1.1.1.4.1 date 2013.11.29.07.49.48; author yamt; state dead; branches; next 1.1.1.1.4.2; commitid nx2BSsHy0NPeAxBx; 1.1.1.1.4.2 date 2014.05.22.14.09.07; author yamt; state Exp; branches; next ; commitid nx2BSsHy0NPeAxBx; 1.1.1.1.8.1 date 2013.11.29.07.49.48; author tls; state dead; branches; next 1.1.1.1.8.2; commitid jTnpym9Qu0o4R1Nx; 1.1.1.1.8.2 date 2014.08.19.23.59.56; author tls; state Exp; branches; next ; commitid jTnpym9Qu0o4R1Nx; desc @@ 1.1 log @Initial revision @ text @dnl AMD64 mpn_lshiftc optimised for CPUs with fast SSE including fast movdqu. dnl Contributed to the GNU project by Torbjorn Granlund. dnl Copyright 2010, 2011, 2012 Free Software Foundation, Inc. dnl This file is part of the GNU MP Library. dnl The GNU MP Library is free software; you can redistribute it and/or modify dnl it under the terms of the GNU Lesser General Public License as published dnl by the Free Software Foundation; either version 3 of the License, or (at dnl your option) any later version. dnl The GNU MP Library is distributed in the hope that it will be useful, but dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public dnl License for more details. dnl You should have received a copy of the GNU Lesser General Public License dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. include(`../config.m4') C cycles/limb cycles/limb cycles/limb good C aligned unaligned best seen for cpu? C AMD K8,K9 3 3 ? no, use shl/shr C AMD K10 1.8-2.0 1.8-2.0 ? yes C AMD bd1 1.9 1.9 ? yes C AMD bobcat 3.67 3.67 yes, bad for n < 20 C Intel P4 4.75 4.75 ? no, slow movdqu C Intel core2 2.27 2.27 ? no, use shld/shrd C Intel NHM 2.15 2.15 ? no, use shld/shrd C Intel SBR 1.45 1.45 ? yes, bad for n = 4-6 C Intel atom 12.9 12.9 ? no C VIA nano 6.18 6.44 ? no, slow movdqu C We try to do as many aligned 16-byte operations as possible. The top-most C and bottom-most writes might need 8-byte operations. C C This variant rely on fast load movdqu, and uses it even for aligned operands, C in order to avoid the need for two separate loops. C C TODO C * Could 2-limb wind-down code be simplified? C * Improve basecase code, using shld/shrd for SBR, discrete integer shifts C for other affected CPUs. C INPUT PARAMETERS define(`rp', `%rdi') define(`ap', `%rsi') define(`n', `%rdx') define(`cnt', `%rcx') ASM_START() TEXT ALIGN(64) PROLOGUE(mpn_lshiftc) FUNC_ENTRY(4) movd R32(%rcx), %xmm4 mov $64, R32(%rax) sub R32(%rcx), R32(%rax) movd R32(%rax), %xmm5 neg R32(%rcx) mov -8(ap,n,8), %rax shr R8(%rcx), %rax pcmpeqb %xmm3, %xmm3 C set to 111...111 cmp $3, n jle L(bc) lea (rp,n,8), R32(%rcx) bt $3, R32(%rcx) jnc L(rp_aligned) C Do one initial limb in order to make rp aligned movq -8(ap,n,8), %xmm0 movq -16(ap,n,8), %xmm1 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, -8(rp,n,8) dec n L(rp_aligned): lea 1(n), %r8d and $6, R32(%r8) jz L(ba0) cmp $4, R32(%r8) jz L(ba4) jc L(ba2) L(ba6): add $-4, n jmp L(i56) L(ba0): add $-6, n jmp L(i70) L(ba4): add $-2, n jmp L(i34) L(ba2): add $-8, n jle L(end) ALIGN(16) L(top): movdqu 40(ap,n,8), %xmm1 movdqu 48(ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, 48(rp,n,8) L(i70): movdqu 24(ap,n,8), %xmm1 movdqu 32(ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, 32(rp,n,8) L(i56): movdqu 8(ap,n,8), %xmm1 movdqu 16(ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, 16(rp,n,8) L(i34): movdqu -8(ap,n,8), %xmm1 movdqu (ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, (rp,n,8) sub $8, n jg L(top) L(end): bt $0, R32(n) jc L(end8) movdqu (ap), %xmm1 pxor %xmm0, %xmm0 punpcklqdq %xmm1, %xmm0 psllq %xmm4, %xmm1 psrlq %xmm5, %xmm0 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, (rp) FUNC_EXIT() ret C Basecase ALIGN(16) L(bc): dec R32(n) jz L(end8) movq (ap,n,8), %xmm1 movq -8(ap,n,8), %xmm0 psllq %xmm4, %xmm1 psrlq %xmm5, %xmm0 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, (rp,n,8) sub $2, R32(n) jl L(end8) movq 8(ap), %xmm1 movq (ap), %xmm0 psllq %xmm4, %xmm1 psrlq %xmm5, %xmm0 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, 8(rp) L(end8):movq (ap), %xmm0 psllq %xmm4, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, (rp) FUNC_EXIT() ret EPILOGUE() @ 1.1.1.1 log @initial import GMP 5.1.3 sources. changes include: fixes for: - mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec - mpz_powm_ui - AMD family 11h - mpz_powm_sec and mpn_powm_sec - ASSERT() fixes - gcd, gcdext, and invert function fixes - some PPC division operations @ text @@ 1.1.1.2 log @initial import of GMP 6.1.2. main changes from 5.1.3 below. notes: - support for thumb-less ARM chips was in our port of 5.1.3, but a similar method has been provided upstream now - someone should look at the AVX failure reports, and fix them Changes between GMP version 6.1.0 and 6.1.1 FEATURES * Work around faulty cpuid on some recent Intel chips (this allows GMP to run on Skylake Pentiums). * Support thumb-less ARM chips. Changes between GMP version 6.0.* and 6.1.0 BUGS FIXED * The public function mpn_com is now correctly declared in gmp.h. * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for some obsolete CPUs. * Various problems related to precision for mpf have been fixed. * Fixed ABI incompatible stack alignment in calls from assembly code. * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI. SPEEDUPS * Speedup for Intel Broadwell and Skylake through assembly code making use of new ADX instructions. * Square root is now faster when the remainder is not needed. Also the speed to compute the k-th root improved, for small sizes. FEATURES * New C++ functions gcd and lcm for mpz_class. * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap. * New public mpq_cmp_z function, to efficiently compare rationals with integers. * Support for more 32-bit arm processors. * Support for AVX-less modern x86 CPUs. (Such support might be missing either because the CPU vendor chose to disable AVX, or because the running kernel lacks AVX context switch support.) * Support for NetBSD under Xen; we switch off AVX unconditionally under NetBSD since a bug in NetBSD makes AVX fail under Xen. MISC * Tuned values for FFT multiplications are provided for larger number on many platforms. Changes between GMP version 5.1.* and 6.0.0 BUGS FIXED * The function mpz_invert now considers any number invertible in Z/1Z. * The mpn multiply code now handles operands of more than 2^31 limbs correctly. (Note however that the mpz code is limited to 2^32 bits on 32-bit hosts and 2^37 bits on 64-bit hosts.) SPEEDUPS * Plain division of large operands is faster and more monotonous in operand size. * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved assembly. * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten and vastly expanded assembly support. Speedup also for the older Core 2 and Nehalem. * Faster mixed arithmetic between mpq_class and double. FEATURES * Support for new Intel and AMD CPUs. * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel silent multiplication and squaring. * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing side-channel silent division. * New public functions mpn_cnd_add_n and mpn_cnd_sub_n. Side-channel silent conditional addition and subtraction. * New public function mpn_sec_powm, implementing side-channel silent modexp. * New public function mpn_sec_invert, implementing side-channel silent modular inversion. * Better support for applications which use the mpz_t type, but nevertheless need to call some of the lower-level mpn functions. See the documentation for mpz_limbs_read and related functions. @ text @d5 1 a5 1 dnl Copyright 2010-2012 Free Software Foundation, Inc. d8 1 a8 1 dnl d10 4 a13 14 dnl it under the terms of either: dnl dnl * the GNU Lesser General Public License as published by the Free dnl Software Foundation; either version 3 of the License, or (at your dnl option) any later version. dnl dnl or dnl dnl * the GNU General Public License as published by the Free Software dnl Foundation; either version 2 of the License, or (at your option) any dnl later version. dnl dnl or both in parallel, as here. dnl d16 5 a20 6 dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License dnl for more details. dnl dnl You should have received copies of the GNU General Public License and the dnl GNU Lesser General Public License along with the GNU MP Library. If not, dnl see https://www.gnu.org/licenses/. d75 2 a76 2 test $8, R8(%rcx) jz L(rp_aligned) d140 2 a141 2 L(end): test $1, R8(n) jnz L(end8) @ 1.1.1.1.8.1 log @file lshiftc-movdqu2.asm was added on branch tls-maxphys on 2014-08-19 23:59:56 +0000 @ text @d1 182 @ 1.1.1.1.8.2 log @Rebase to HEAD as of a few days ago. @ text @a0 182 dnl AMD64 mpn_lshiftc optimised for CPUs with fast SSE including fast movdqu. dnl Contributed to the GNU project by Torbjorn Granlund. dnl Copyright 2010, 2011, 2012 Free Software Foundation, Inc. dnl This file is part of the GNU MP Library. dnl The GNU MP Library is free software; you can redistribute it and/or modify dnl it under the terms of the GNU Lesser General Public License as published dnl by the Free Software Foundation; either version 3 of the License, or (at dnl your option) any later version. dnl The GNU MP Library is distributed in the hope that it will be useful, but dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public dnl License for more details. dnl You should have received a copy of the GNU Lesser General Public License dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. include(`../config.m4') C cycles/limb cycles/limb cycles/limb good C aligned unaligned best seen for cpu? C AMD K8,K9 3 3 ? no, use shl/shr C AMD K10 1.8-2.0 1.8-2.0 ? yes C AMD bd1 1.9 1.9 ? yes C AMD bobcat 3.67 3.67 yes, bad for n < 20 C Intel P4 4.75 4.75 ? no, slow movdqu C Intel core2 2.27 2.27 ? no, use shld/shrd C Intel NHM 2.15 2.15 ? no, use shld/shrd C Intel SBR 1.45 1.45 ? yes, bad for n = 4-6 C Intel atom 12.9 12.9 ? no C VIA nano 6.18 6.44 ? no, slow movdqu C We try to do as many aligned 16-byte operations as possible. The top-most C and bottom-most writes might need 8-byte operations. C C This variant rely on fast load movdqu, and uses it even for aligned operands, C in order to avoid the need for two separate loops. C C TODO C * Could 2-limb wind-down code be simplified? C * Improve basecase code, using shld/shrd for SBR, discrete integer shifts C for other affected CPUs. C INPUT PARAMETERS define(`rp', `%rdi') define(`ap', `%rsi') define(`n', `%rdx') define(`cnt', `%rcx') ASM_START() TEXT ALIGN(64) PROLOGUE(mpn_lshiftc) FUNC_ENTRY(4) movd R32(%rcx), %xmm4 mov $64, R32(%rax) sub R32(%rcx), R32(%rax) movd R32(%rax), %xmm5 neg R32(%rcx) mov -8(ap,n,8), %rax shr R8(%rcx), %rax pcmpeqb %xmm3, %xmm3 C set to 111...111 cmp $3, n jle L(bc) lea (rp,n,8), R32(%rcx) bt $3, R32(%rcx) jnc L(rp_aligned) C Do one initial limb in order to make rp aligned movq -8(ap,n,8), %xmm0 movq -16(ap,n,8), %xmm1 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, -8(rp,n,8) dec n L(rp_aligned): lea 1(n), %r8d and $6, R32(%r8) jz L(ba0) cmp $4, R32(%r8) jz L(ba4) jc L(ba2) L(ba6): add $-4, n jmp L(i56) L(ba0): add $-6, n jmp L(i70) L(ba4): add $-2, n jmp L(i34) L(ba2): add $-8, n jle L(end) ALIGN(16) L(top): movdqu 40(ap,n,8), %xmm1 movdqu 48(ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, 48(rp,n,8) L(i70): movdqu 24(ap,n,8), %xmm1 movdqu 32(ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, 32(rp,n,8) L(i56): movdqu 8(ap,n,8), %xmm1 movdqu 16(ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, 16(rp,n,8) L(i34): movdqu -8(ap,n,8), %xmm1 movdqu (ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, (rp,n,8) sub $8, n jg L(top) L(end): bt $0, R32(n) jc L(end8) movdqu (ap), %xmm1 pxor %xmm0, %xmm0 punpcklqdq %xmm1, %xmm0 psllq %xmm4, %xmm1 psrlq %xmm5, %xmm0 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, (rp) FUNC_EXIT() ret C Basecase ALIGN(16) L(bc): dec R32(n) jz L(end8) movq (ap,n,8), %xmm1 movq -8(ap,n,8), %xmm0 psllq %xmm4, %xmm1 psrlq %xmm5, %xmm0 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, (rp,n,8) sub $2, R32(n) jl L(end8) movq 8(ap), %xmm1 movq (ap), %xmm0 psllq %xmm4, %xmm1 psrlq %xmm5, %xmm0 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, 8(rp) L(end8):movq (ap), %xmm0 psllq %xmm4, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, (rp) FUNC_EXIT() ret EPILOGUE() @ 1.1.1.1.4.1 log @file lshiftc-movdqu2.asm was added on branch yamt-pagecache on 2014-05-22 14:09:07 +0000 @ text @d1 182 @ 1.1.1.1.4.2 log @sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments") @ text @a0 182 dnl AMD64 mpn_lshiftc optimised for CPUs with fast SSE including fast movdqu. dnl Contributed to the GNU project by Torbjorn Granlund. dnl Copyright 2010, 2011, 2012 Free Software Foundation, Inc. dnl This file is part of the GNU MP Library. dnl The GNU MP Library is free software; you can redistribute it and/or modify dnl it under the terms of the GNU Lesser General Public License as published dnl by the Free Software Foundation; either version 3 of the License, or (at dnl your option) any later version. dnl The GNU MP Library is distributed in the hope that it will be useful, but dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public dnl License for more details. dnl You should have received a copy of the GNU Lesser General Public License dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. include(`../config.m4') C cycles/limb cycles/limb cycles/limb good C aligned unaligned best seen for cpu? C AMD K8,K9 3 3 ? no, use shl/shr C AMD K10 1.8-2.0 1.8-2.0 ? yes C AMD bd1 1.9 1.9 ? yes C AMD bobcat 3.67 3.67 yes, bad for n < 20 C Intel P4 4.75 4.75 ? no, slow movdqu C Intel core2 2.27 2.27 ? no, use shld/shrd C Intel NHM 2.15 2.15 ? no, use shld/shrd C Intel SBR 1.45 1.45 ? yes, bad for n = 4-6 C Intel atom 12.9 12.9 ? no C VIA nano 6.18 6.44 ? no, slow movdqu C We try to do as many aligned 16-byte operations as possible. The top-most C and bottom-most writes might need 8-byte operations. C C This variant rely on fast load movdqu, and uses it even for aligned operands, C in order to avoid the need for two separate loops. C C TODO C * Could 2-limb wind-down code be simplified? C * Improve basecase code, using shld/shrd for SBR, discrete integer shifts C for other affected CPUs. C INPUT PARAMETERS define(`rp', `%rdi') define(`ap', `%rsi') define(`n', `%rdx') define(`cnt', `%rcx') ASM_START() TEXT ALIGN(64) PROLOGUE(mpn_lshiftc) FUNC_ENTRY(4) movd R32(%rcx), %xmm4 mov $64, R32(%rax) sub R32(%rcx), R32(%rax) movd R32(%rax), %xmm5 neg R32(%rcx) mov -8(ap,n,8), %rax shr R8(%rcx), %rax pcmpeqb %xmm3, %xmm3 C set to 111...111 cmp $3, n jle L(bc) lea (rp,n,8), R32(%rcx) bt $3, R32(%rcx) jnc L(rp_aligned) C Do one initial limb in order to make rp aligned movq -8(ap,n,8), %xmm0 movq -16(ap,n,8), %xmm1 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, -8(rp,n,8) dec n L(rp_aligned): lea 1(n), %r8d and $6, R32(%r8) jz L(ba0) cmp $4, R32(%r8) jz L(ba4) jc L(ba2) L(ba6): add $-4, n jmp L(i56) L(ba0): add $-6, n jmp L(i70) L(ba4): add $-2, n jmp L(i34) L(ba2): add $-8, n jle L(end) ALIGN(16) L(top): movdqu 40(ap,n,8), %xmm1 movdqu 48(ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, 48(rp,n,8) L(i70): movdqu 24(ap,n,8), %xmm1 movdqu 32(ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, 32(rp,n,8) L(i56): movdqu 8(ap,n,8), %xmm1 movdqu 16(ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, 16(rp,n,8) L(i34): movdqu -8(ap,n,8), %xmm1 movdqu (ap,n,8), %xmm0 psllq %xmm4, %xmm0 psrlq %xmm5, %xmm1 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, (rp,n,8) sub $8, n jg L(top) L(end): bt $0, R32(n) jc L(end8) movdqu (ap), %xmm1 pxor %xmm0, %xmm0 punpcklqdq %xmm1, %xmm0 psllq %xmm4, %xmm1 psrlq %xmm5, %xmm0 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movdqa %xmm0, (rp) FUNC_EXIT() ret C Basecase ALIGN(16) L(bc): dec R32(n) jz L(end8) movq (ap,n,8), %xmm1 movq -8(ap,n,8), %xmm0 psllq %xmm4, %xmm1 psrlq %xmm5, %xmm0 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, (rp,n,8) sub $2, R32(n) jl L(end8) movq 8(ap), %xmm1 movq (ap), %xmm0 psllq %xmm4, %xmm1 psrlq %xmm5, %xmm0 por %xmm1, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, 8(rp) L(end8):movq (ap), %xmm0 psllq %xmm4, %xmm0 pxor %xmm3, %xmm0 movq %xmm0, (rp) FUNC_EXIT() ret EPILOGUE() @