head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.2 netbsd-11-0-RC3:1.1.1.2 netbsd-11-0-RC2:1.1.1.2 netbsd-11-0-RC1:1.1.1.2 perseant-exfatfs-base-20250801:1.1.1.2 netbsd-11:1.1.1.2.0.10 netbsd-11-base:1.1.1.2 netbsd-10-1-RELEASE:1.1.1.2 perseant-exfatfs-base-20240630:1.1.1.2 perseant-exfatfs:1.1.1.2.0.8 perseant-exfatfs-base:1.1.1.2 netbsd-9-4-RELEASE:1.1.1.1 netbsd-10-0-RELEASE:1.1.1.2 netbsd-10-0-RC6:1.1.1.2 netbsd-10-0-RC5:1.1.1.2 netbsd-10-0-RC4:1.1.1.2 netbsd-10-0-RC3:1.1.1.2 netbsd-10-0-RC2:1.1.1.2 netbsd-10-0-RC1:1.1.1.2 netbsd-10:1.1.1.2.0.6 netbsd-10-base:1.1.1.2 netbsd-9-3-RELEASE:1.1.1.1 gmp-6-2-1:1.1.1.2 cjep_sun2x-base1:1.1.1.2 cjep_sun2x:1.1.1.2.0.4 cjep_sun2x-base:1.1.1.2 cjep_staticlib_x-base1:1.1.1.2 netbsd-9-2-RELEASE:1.1.1.1 cjep_staticlib_x:1.1.1.2.0.2 cjep_staticlib_x-base:1.1.1.2 netbsd-9-1-RELEASE:1.1.1.1 gmp-6-2-0:1.1.1.2 phil-wifi-20200421:1.1.1.1 phil-wifi-20200411:1.1.1.1 is-mlppp:1.1.1.1.0.8 is-mlppp-base:1.1.1.1 phil-wifi-20200406:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.1 netbsd-9-0-RC2:1.1.1.1 netbsd-9-0-RC1:1.1.1.1 phil-wifi-20191119:1.1.1.1 netbsd-9:1.1.1.1.0.6 netbsd-9-base:1.1.1.1 phil-wifi-20190609:1.1.1.1 pgoyette-compat-merge-20190127:1.1.1.1 pgoyette-compat-20190127:1.1.1.1 pgoyette-compat-20190118:1.1.1.1 pgoyette-compat-1226:1.1.1.1 pgoyette-compat-1126:1.1.1.1 pgoyette-compat-1020:1.1.1.1 pgoyette-compat-0930:1.1.1.1 pgoyette-compat-0906:1.1.1.1 pgoyette-compat-0728:1.1.1.1 phil-wifi:1.1.1.1.0.4 phil-wifi-base:1.1.1.1 pgoyette-compat-0625:1.1.1.1 pgoyette-compat-0521:1.1.1.1 pgoyette-compat-0502:1.1.1.1 pgoyette-compat-0422:1.1.1.1 pgoyette-compat-0415:1.1.1.1 pgoyette-compat-0407:1.1.1.1 pgoyette-compat-0330:1.1.1.1 pgoyette-compat-0322:1.1.1.1 pgoyette-compat-0315:1.1.1.1 pgoyette-compat:1.1.1.1.0.2 pgoyette-compat-base:1.1.1.1 gmp-6-1-2:1.1.1.1 gmp:1.1.1; locks; strict; comment @;; @; 1.1 date 2017.08.22.09.40.49; author mrg; state Exp; branches 1.1.1.1; next ; commitid W5kmAIk8hwVpSb4A; 1.1.1.1 date 2017.08.22.09.40.49; author mrg; state Exp; branches; next 1.1.1.2; commitid W5kmAIk8hwVpSb4A; 1.1.1.2 date 2020.09.27.00.27.05; author mrg; state Exp; branches; next ; commitid BWuUFuEU17KgrCpC; desc @@ 1.1 log @Initial revision @ text @dnl AMD64 mpn_mul_2 optimised for AMD Bulldozer. dnl Contributed to the GNU project by Torbjörn Granlund. dnl Copyright 2008, 2011-2013 Free Software Foundation, Inc. dnl This file is part of the GNU MP Library. dnl dnl The GNU MP Library is free software; you can redistribute it and/or modify dnl it under the terms of either: dnl dnl * the GNU Lesser General Public License as published by the Free dnl Software Foundation; either version 3 of the License, or (at your dnl option) any later version. dnl dnl or dnl dnl * the GNU General Public License as published by the Free Software dnl Foundation; either version 2 of the License, or (at your option) any dnl later version. dnl dnl or both in parallel, as here. dnl dnl The GNU MP Library is distributed in the hope that it will be useful, but dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License dnl for more details. dnl dnl You should have received copies of the GNU General Public License and the dnl GNU Lesser General Public License along with the GNU MP Library. If not, dnl see https://www.gnu.org/licenses/. include(`../config.m4') C cycles/limb C AMD K8,K9 C AMD K10 C AMD bull 4.36 average, quite fluctuating C AMD pile 4.38 slighty fluctuating C AMD steam C AMD bobcat C AMD jaguar C Intel P4 C Intel core C Intel NHM C Intel SBR C Intel IBR C Intel HWL C Intel BWL C Intel atom C VIA nano C The loop of this code is the result of running a code generation and C optimisation tool suite written by David Harvey and Torbjorn Granlund. C Scheme: genxmul --mul define(`rp', `%rdi') C rcx define(`up', `%rsi') C rdx define(`n_param', `%rdx') C r8 define(`vp', `%rcx') C r9 define(`v0', `%r8') define(`v1', `%r9') define(`w0', `%rbx') define(`w1', `%rcx') define(`w2', `%rbp') define(`w3', `%r10') define(`n', `%r11') ABI_SUPPORT(DOS64) ABI_SUPPORT(STD64) ASM_START() TEXT ALIGN(32) PROLOGUE(mpn_mul_2) FUNC_ENTRY(4) push %rbx push %rbp mov (up), %rax mov (vp), v0 mov 8(vp), v1 lea (up,n_param,8), up lea (rp,n_param,8), rp mov n_param, n mul v0 neg n test $1, R8(n) jnz L(bx1) L(bx0): test $2, R8(n) jnz L(b10) L(b00): mov %rax, w0 mov %rdx, w1 xor R32(w2), R32(w2) mov (up,n,8), %rax jmp L(lo0) L(b10): mov %rax, w2 mov %rdx, w3 mov (up,n,8), %rax xor R32(w0), R32(w0) mul v1 add $-2, n jmp L(lo2) L(bx1): test $2, R8(n) jz L(b11) L(b01): mov %rax, w3 mov %rdx, w0 mov (up,n,8), %rax mul v1 xor R32(w1), R32(w1) inc n jmp L(lo1) L(b11): mov %rax, w1 mov %rdx, w2 mov (up,n,8), %rax xor R32(w3), R32(w3) dec n jmp L(lo3) ALIGN(32) L(top): mov -8(up,n,8), %rax mul v1 mov w2, -16(rp,n,8) L(lo1): add %rax, w0 mov w3, -8(rp,n,8) adc %rdx, w1 mov (up,n,8), %rax mul v0 mov $0, R32(w2) add %rax, w0 adc %rdx, w1 adc $0, R32(w2) mov (up,n,8), %rax L(lo0): mul v1 add %rax, w1 adc %rdx, w2 mov 8(up,n,8), %rax mul v0 add %rax, w1 mov w0, (rp,n,8) mov $0, R32(w3) mov 8(up,n,8), %rax adc %rdx, w2 adc $0, R32(w3) L(lo3): mul v1 add %rax, w2 mov 16(up,n,8), %rax adc %rdx, w3 mul v0 add %rax, w2 mov 16(up,n,8), %rax mov $0, R32(w0) adc %rdx, w3 adc $0, R32(w0) mul v1 mov w1, 8(rp,n,8) L(lo2): add %rax, w3 adc %rdx, w0 mov 24(up,n,8), %rax mul v0 add %rax, w3 adc %rdx, w0 mov $0, R32(w1) adc $0, R32(w1) add $4, n jnc L(top) L(end): mov -8(up,n,8), %rax mul v1 mov w2, -16(rp,n,8) add %rax, w0 mov w3, -8(rp,n,8) adc %rdx, w1 mov w0, (rp,n,8) mov w1, %rax pop %rbp pop %rbx FUNC_EXIT() ret EPILOGUE() @ 1.1.1.1 log @initial import of GMP 6.1.2. main changes from 5.1.3 below. notes: - support for thumb-less ARM chips was in our port of 5.1.3, but a similar method has been provided upstream now - someone should look at the AVX failure reports, and fix them Changes between GMP version 6.1.0 and 6.1.1 FEATURES * Work around faulty cpuid on some recent Intel chips (this allows GMP to run on Skylake Pentiums). * Support thumb-less ARM chips. Changes between GMP version 6.0.* and 6.1.0 BUGS FIXED * The public function mpn_com is now correctly declared in gmp.h. * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for some obsolete CPUs. * Various problems related to precision for mpf have been fixed. * Fixed ABI incompatible stack alignment in calls from assembly code. * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI. SPEEDUPS * Speedup for Intel Broadwell and Skylake through assembly code making use of new ADX instructions. * Square root is now faster when the remainder is not needed. Also the speed to compute the k-th root improved, for small sizes. FEATURES * New C++ functions gcd and lcm for mpz_class. * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap. * New public mpq_cmp_z function, to efficiently compare rationals with integers. * Support for more 32-bit arm processors. * Support for AVX-less modern x86 CPUs. (Such support might be missing either because the CPU vendor chose to disable AVX, or because the running kernel lacks AVX context switch support.) * Support for NetBSD under Xen; we switch off AVX unconditionally under NetBSD since a bug in NetBSD makes AVX fail under Xen. MISC * Tuned values for FFT multiplications are provided for larger number on many platforms. Changes between GMP version 5.1.* and 6.0.0 BUGS FIXED * The function mpz_invert now considers any number invertible in Z/1Z. * The mpn multiply code now handles operands of more than 2^31 limbs correctly. (Note however that the mpz code is limited to 2^32 bits on 32-bit hosts and 2^37 bits on 64-bit hosts.) SPEEDUPS * Plain division of large operands is faster and more monotonous in operand size. * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved assembly. * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten and vastly expanded assembly support. Speedup also for the older Core 2 and Nehalem. * Faster mixed arithmetic between mpq_class and double. FEATURES * Support for new Intel and AMD CPUs. * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel silent multiplication and squaring. * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing side-channel silent division. * New public functions mpn_cnd_add_n and mpn_cnd_sub_n. Side-channel silent conditional addition and subtraction. * New public function mpn_sec_powm, implementing side-channel silent modexp. * New public function mpn_sec_invert, implementing side-channel silent modular inversion. * Better support for applications which use the mpz_t type, but nevertheless need to call some of the lower-level mpn functions. See the documentation for mpz_limbs_read and related functions. @ text @@ 1.1.1.2 log @initial import of GMP 6.2.0. changes include: - Bug fixes to gmp_snprintf, conversion to double, mpz_powm, and mpf_set_str. - New functions for factorial, primorial, fibonacci, mpz_2fac_ui, and mpz_mfac_uiui. - MIPS r6 cores are now supported. - Various speeds ups. @ text @d36 15 a50 19 C AMD K8,K9 6.78 C AMD K10 6.78 C AMD bd1 8.39 8.65 C AMD bd2 8.47 C AMD bd3 C AMD bd4 C AMD zen C AMD bt1 12.1 C AMD bt2 11.5 C Intel P4 24.0 C Intel PNR 8.14 C Intel NHM 7.78 C Intel SBR 6.34 C Intel IBR 6.15 C Intel HWL 6.04 C Intel BWL 4.33 C Intel SKL 4.41 C Intel atom 39.5 C Intel SLM 27.8 d55 1 d179 1 a179 1 L(end): mov -8(up), %rax d181 1 a181 1 mov w2, -16(rp) d183 1 a183 1 mov w3, -8(rp) d185 1 a185 1 mov w0, (rp) @