head	1.1;
branch	1.1.1;
access;
symbols
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	tls-maxphys:1.1.1.1.0.8
	netbsd-7:1.1.1.1.0.6
	netbsd-7-base:1.1.1.1
	yamt-pagecache:1.1.1.1.0.4
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	tls-earlyentropy:1.1.1.1.0.2
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	gmp-5-1-3:1.1.1.1
	gmp:1.1.1;
locks; strict;
comment	@;; @;


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desc
@@


1.1
log
@Initial revision
@
text
@dnl  Intel Pentium-4 mpn_divexact_1 -- mpn by limb exact division.

dnl  Copyright 2001, 2002, 2007, 2011 Free Software Foundation, Inc.
dnl
dnl  This file is part of the GNU MP Library.
dnl
dnl  Rearranged from mpn/x86/pentium4/sse2/dive_1.asm by Marco Bodrato.
dnl
dnl  The GNU MP Library is free software; you can redistribute it and/or
dnl  modify it under the terms of the GNU Lesser General Public License as
dnl  published by the Free Software Foundation; either version 3 of the
dnl  License, or (at your option) any later version.
dnl
dnl  The GNU MP Library is distributed in the hope that it will be useful,
dnl  but WITHOUT ANY WARRANTY; without even the implied warranty of
dnl  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
dnl  Lesser General Public License for more details.
dnl
dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')


C P4: 19.0 cycles/limb

C Pairs of movd's are used to avoid unaligned loads.  Despite the loads not
C being on the dependent chain and there being plenty of cycles available,
C using an unaligned movq on every second iteration measured about 23 c/l.
C

defframe(PARAM_SHIFT,  24)
defframe(PARAM_INVERSE,20)
defframe(PARAM_DIVISOR,16)
defframe(PARAM_SIZE,   12)
defframe(PARAM_SRC,    8)
defframe(PARAM_DST,    4)

	TEXT

C mp_limb_t
C mpn_pi1_bdiv_q_1 (mp_ptr dst, mp_srcptr src, mp_size_t size, mp_limb_t divisor,
C		    mp_limb_t inverse, int shift)
	ALIGN(32)
PROLOGUE(mpn_pi1_bdiv_q_1)
deflit(`FRAME',0)

	movl	PARAM_SIZE, %edx

	movl	PARAM_SRC, %eax

	movl	PARAM_DIVISOR, %ecx

	movd	%ecx, %mm6
	movl	PARAM_SHIFT, %ecx

	movd	%ecx, %mm7		C shift

	C

	movl	PARAM_INVERSE, %ecx
	movd	%ecx, %mm5		C inv

	movl	PARAM_DST, %ecx
	pxor	%mm1, %mm1		C initial carry limb
	pxor	%mm0, %mm0		C initial carry bit

	subl	$1, %edx
	jz	L(done)

	pcmpeqd	%mm4, %mm4
	psrlq	$32, %mm4		C 0x00000000FFFFFFFF

C The dependent chain here is as follows.
C
C					latency
C	psubq	 s = (src-cbit) - climb	   2
C	pmuludq	 q = s*inverse		   8
C	pmuludq	 prod = q*divisor	   8
C	psrlq	 climb = high(prod)	   2
C					  --
C					  20
C
C Yet the loop measures 19.0 c/l, so obviously there's something gained
C there over a straight reading of the chip documentation.

L(top):
	C eax	src, incrementing
	C ebx
	C ecx	dst, incrementing
	C edx	counter, size-1 iterations
	C
	C mm0	carry bit
	C mm1	carry limb
	C mm4	0x00000000FFFFFFFF
	C mm5	inverse
	C mm6	divisor
	C mm7	shift

	movd	(%eax), %mm2
	movd	4(%eax), %mm3
	addl	$4, %eax
	punpckldq %mm3, %mm2

	psrlq	%mm7, %mm2
	pand	%mm4, %mm2		C src
	psubq	%mm0, %mm2		C src - cbit

	psubq	%mm1, %mm2		C src - cbit - climb
	movq	%mm2, %mm0
	psrlq	$63, %mm0		C new cbit

	pmuludq	%mm5, %mm2		C s*inverse
	movd	%mm2, (%ecx)		C q
	addl	$4, %ecx

	movq	%mm6, %mm1
	pmuludq	%mm2, %mm1		C q*divisor
	psrlq	$32, %mm1		C new climb

L(entry):
	subl	$1, %edx
	jnz	L(top)

L(done):
	movd	(%eax), %mm2
	psrlq	%mm7, %mm2		C src
	psubq	%mm0, %mm2		C src - cbit

	psubq	%mm1, %mm2		C src - cbit - climb

	pmuludq	%mm5, %mm2		C s*inverse
	movd	%mm2, (%ecx)		C q

	emms
	ret

EPILOGUE()

	ALIGN(16)
C mp_limb_t mpn_bdiv_q_1 (mp_ptr dst, mp_srcptr src, mp_size_t size,
C                           mp_limb_t divisor);
C
PROLOGUE(mpn_bdiv_q_1)
deflit(`FRAME',0)

	movl	PARAM_SIZE, %edx

	movl	PARAM_DIVISOR, %ecx

	C eax	src
	C ebx
	C ecx	divisor
	C edx	size-1

	movl	%ecx, %eax
	bsfl	%ecx, %ecx		C trailing twos

	shrl	%cl, %eax		C d = divisor without twos
	movd	%eax, %mm6
	movd	%ecx, %mm7		C shift

	shrl	%eax			C d/2

	andl	$127, %eax		C d/2, 7 bits

ifdef(`PIC',`
	LEA(	binvert_limb_table, %ecx)
	movzbl	(%eax,%ecx), %eax		C inv 8 bits
',`
	movzbl	binvert_limb_table(%eax), %eax	C inv 8 bits
')

	C

	movd	%eax, %mm5		C inv

	movd	%eax, %mm0		C inv

	pmuludq	%mm5, %mm5		C inv*inv

	C

	pmuludq	%mm6, %mm5		C inv*inv*d
	paddd	%mm0, %mm0		C 2*inv

	C

	psubd	%mm5, %mm0		C inv = 2*inv - inv*inv*d
	pxor	%mm5, %mm5

	paddd	%mm0, %mm5
	pmuludq	%mm0, %mm0		C inv*inv

	pcmpeqd	%mm4, %mm4
	psrlq	$32, %mm4		C 0x00000000FFFFFFFF

	C

	pmuludq	%mm6, %mm0		C inv*inv*d
	paddd	%mm5, %mm5		C 2*inv

	movl	PARAM_SRC, %eax
	movl	PARAM_DST, %ecx
	pxor	%mm1, %mm1		C initial carry limb

	C

	psubd	%mm0, %mm5		C inv = 2*inv - inv*inv*d

	ASSERT(e,`	C expect d*inv == 1 mod 2^GMP_LIMB_BITS
	pushl	%eax	FRAME_pushl()
	movq	%mm6, %mm0
	pmuludq	%mm5, %mm0
	movd	%mm0, %eax
	cmpl	$1, %eax
	popl	%eax	FRAME_popl()')

	pxor	%mm0, %mm0		C initial carry bit
	jmp	L(entry)

EPILOGUE()
@


1.1.1.1
log
@initial import GMP 5.1.3 sources.  changes include:

fixes for:
- mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec
- mpz_powm_ui
- AMD family 11h
- mpz_powm_sec and mpn_powm_sec
- ASSERT() fixes
- gcd, gcdext, and invert function fixes
- some PPC division operations
@
text
@@


1.1.1.2
log
@initial import of GMP 6.1.2.  main changes from 5.1.3 below.

notes:
 - support for thumb-less ARM chips was in our port of 5.1.3, but a
   similar method has been provided upstream now
 - someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

  FEATURES
  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
    on Skylake Pentiums).
  * Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

  BUGS FIXED
  * The public function mpn_com is now correctly declared in gmp.h.
  * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
    some obsolete CPUs.
  * Various problems related to precision for mpf have been fixed.
  * Fixed ABI incompatible stack alignment in calls from assembly code.
  * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
  SPEEDUPS
  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    new ADX instructions.
  * Square root is now faster when the remainder is not needed. Also the speed
    to compute the k-th root improved, for small sizes.
  FEATURES
  * New C++ functions gcd and lcm for mpz_class.
  * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
  * New public mpq_cmp_z function, to efficiently compare rationals with
    integers.
  * Support for more 32-bit arm processors.
  * Support for AVX-less modern x86 CPUs. (Such support might be missing either
    because the CPU vendor chose to disable AVX, or because the running kernel
    lacks AVX context switch support.)
  * Support for NetBSD under Xen; we switch off AVX unconditionally under
    NetBSD since a bug in NetBSD makes AVX fail under Xen.
  MISC
  * Tuned values for FFT multiplications are provided for larger number on
    many platforms.

Changes between GMP version 5.1.* and 6.0.0
  BUGS FIXED
  * The function mpz_invert now considers any number invertible in Z/1Z.
  * The mpn multiply code now handles operands of more than 2^31 limbs
    correctly.  (Note however that the mpz code is limited to 2^32 bits on
    32-bit hosts and 2^37 bits on 64-bit hosts.)
  SPEEDUPS
  * Plain division of large operands is faster and more monotonous in operand
    size.
  * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
    assembly.
  * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
    and vastly expanded assembly support.  Speedup also for the older Core 2
    and Nehalem.
  * Faster mixed arithmetic between mpq_class and double.
  FEATURES
  * Support for new Intel and AMD CPUs.
  * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
    silent multiplication and squaring.
  * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
    side-channel silent division.
  * New public functions mpn_cnd_add_n and mpn_cnd_sub_n.  Side-channel silent
    conditional addition and subtraction.
  * New public function mpn_sec_powm, implementing side-channel silent modexp.
  * New public function mpn_sec_invert, implementing side-channel silent
    modular inversion.
  * Better support for applications which use the mpz_t type, but nevertheless
    need to call some of the lower-level mpn functions.  See the documentation
    for mpz_limbs_read and related functions.
@
text
@a2 2
dnl  Rearranged from mpn/x86/pentium4/sse2/dive_1.asm by Marco Bodrato.

d4 1
a4 1

d7 1
a7 14
dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of either:
dnl
dnl    * the GNU Lesser General Public License as published by the Free
dnl      Software Foundation; either version 3 of the License, or (at your
dnl      option) any later version.
dnl
dnl  or
dnl
dnl    * the GNU General Public License as published by the Free Software
dnl      Foundation; either version 2 of the License, or (at your option) any
dnl      later version.
dnl
dnl  or both in parallel, as here.
d9 9
a17 4
dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
dnl  for more details.
d19 2
a20 3
dnl  You should have received copies of the GNU General Public License and the
dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
dnl  see https://www.gnu.org/licenses/.
a222 1
ASM_END()
@


1.1.1.1.8.1
log
@file bdiv_q_1.asm was added on branch tls-maxphys on 2014-08-19 23:59:55 +0000
@
text
@d1 222
@


1.1.1.1.8.2
log
@Rebase to HEAD as of a few days ago.
@
text
@a0 222
dnl  Intel Pentium-4 mpn_divexact_1 -- mpn by limb exact division.

dnl  Copyright 2001, 2002, 2007, 2011 Free Software Foundation, Inc.
dnl
dnl  This file is part of the GNU MP Library.
dnl
dnl  Rearranged from mpn/x86/pentium4/sse2/dive_1.asm by Marco Bodrato.
dnl
dnl  The GNU MP Library is free software; you can redistribute it and/or
dnl  modify it under the terms of the GNU Lesser General Public License as
dnl  published by the Free Software Foundation; either version 3 of the
dnl  License, or (at your option) any later version.
dnl
dnl  The GNU MP Library is distributed in the hope that it will be useful,
dnl  but WITHOUT ANY WARRANTY; without even the implied warranty of
dnl  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
dnl  Lesser General Public License for more details.
dnl
dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')


C P4: 19.0 cycles/limb

C Pairs of movd's are used to avoid unaligned loads.  Despite the loads not
C being on the dependent chain and there being plenty of cycles available,
C using an unaligned movq on every second iteration measured about 23 c/l.
C

defframe(PARAM_SHIFT,  24)
defframe(PARAM_INVERSE,20)
defframe(PARAM_DIVISOR,16)
defframe(PARAM_SIZE,   12)
defframe(PARAM_SRC,    8)
defframe(PARAM_DST,    4)

	TEXT

C mp_limb_t
C mpn_pi1_bdiv_q_1 (mp_ptr dst, mp_srcptr src, mp_size_t size, mp_limb_t divisor,
C		    mp_limb_t inverse, int shift)
	ALIGN(32)
PROLOGUE(mpn_pi1_bdiv_q_1)
deflit(`FRAME',0)

	movl	PARAM_SIZE, %edx

	movl	PARAM_SRC, %eax

	movl	PARAM_DIVISOR, %ecx

	movd	%ecx, %mm6
	movl	PARAM_SHIFT, %ecx

	movd	%ecx, %mm7		C shift

	C

	movl	PARAM_INVERSE, %ecx
	movd	%ecx, %mm5		C inv

	movl	PARAM_DST, %ecx
	pxor	%mm1, %mm1		C initial carry limb
	pxor	%mm0, %mm0		C initial carry bit

	subl	$1, %edx
	jz	L(done)

	pcmpeqd	%mm4, %mm4
	psrlq	$32, %mm4		C 0x00000000FFFFFFFF

C The dependent chain here is as follows.
C
C					latency
C	psubq	 s = (src-cbit) - climb	   2
C	pmuludq	 q = s*inverse		   8
C	pmuludq	 prod = q*divisor	   8
C	psrlq	 climb = high(prod)	   2
C					  --
C					  20
C
C Yet the loop measures 19.0 c/l, so obviously there's something gained
C there over a straight reading of the chip documentation.

L(top):
	C eax	src, incrementing
	C ebx
	C ecx	dst, incrementing
	C edx	counter, size-1 iterations
	C
	C mm0	carry bit
	C mm1	carry limb
	C mm4	0x00000000FFFFFFFF
	C mm5	inverse
	C mm6	divisor
	C mm7	shift

	movd	(%eax), %mm2
	movd	4(%eax), %mm3
	addl	$4, %eax
	punpckldq %mm3, %mm2

	psrlq	%mm7, %mm2
	pand	%mm4, %mm2		C src
	psubq	%mm0, %mm2		C src - cbit

	psubq	%mm1, %mm2		C src - cbit - climb
	movq	%mm2, %mm0
	psrlq	$63, %mm0		C new cbit

	pmuludq	%mm5, %mm2		C s*inverse
	movd	%mm2, (%ecx)		C q
	addl	$4, %ecx

	movq	%mm6, %mm1
	pmuludq	%mm2, %mm1		C q*divisor
	psrlq	$32, %mm1		C new climb

L(entry):
	subl	$1, %edx
	jnz	L(top)

L(done):
	movd	(%eax), %mm2
	psrlq	%mm7, %mm2		C src
	psubq	%mm0, %mm2		C src - cbit

	psubq	%mm1, %mm2		C src - cbit - climb

	pmuludq	%mm5, %mm2		C s*inverse
	movd	%mm2, (%ecx)		C q

	emms
	ret

EPILOGUE()

	ALIGN(16)
C mp_limb_t mpn_bdiv_q_1 (mp_ptr dst, mp_srcptr src, mp_size_t size,
C                           mp_limb_t divisor);
C
PROLOGUE(mpn_bdiv_q_1)
deflit(`FRAME',0)

	movl	PARAM_SIZE, %edx

	movl	PARAM_DIVISOR, %ecx

	C eax	src
	C ebx
	C ecx	divisor
	C edx	size-1

	movl	%ecx, %eax
	bsfl	%ecx, %ecx		C trailing twos

	shrl	%cl, %eax		C d = divisor without twos
	movd	%eax, %mm6
	movd	%ecx, %mm7		C shift

	shrl	%eax			C d/2

	andl	$127, %eax		C d/2, 7 bits

ifdef(`PIC',`
	LEA(	binvert_limb_table, %ecx)
	movzbl	(%eax,%ecx), %eax		C inv 8 bits
',`
	movzbl	binvert_limb_table(%eax), %eax	C inv 8 bits
')

	C

	movd	%eax, %mm5		C inv

	movd	%eax, %mm0		C inv

	pmuludq	%mm5, %mm5		C inv*inv

	C

	pmuludq	%mm6, %mm5		C inv*inv*d
	paddd	%mm0, %mm0		C 2*inv

	C

	psubd	%mm5, %mm0		C inv = 2*inv - inv*inv*d
	pxor	%mm5, %mm5

	paddd	%mm0, %mm5
	pmuludq	%mm0, %mm0		C inv*inv

	pcmpeqd	%mm4, %mm4
	psrlq	$32, %mm4		C 0x00000000FFFFFFFF

	C

	pmuludq	%mm6, %mm0		C inv*inv*d
	paddd	%mm5, %mm5		C 2*inv

	movl	PARAM_SRC, %eax
	movl	PARAM_DST, %ecx
	pxor	%mm1, %mm1		C initial carry limb

	C

	psubd	%mm0, %mm5		C inv = 2*inv - inv*inv*d

	ASSERT(e,`	C expect d*inv == 1 mod 2^GMP_LIMB_BITS
	pushl	%eax	FRAME_pushl()
	movq	%mm6, %mm0
	pmuludq	%mm5, %mm0
	movd	%mm0, %eax
	cmpl	$1, %eax
	popl	%eax	FRAME_popl()')

	pxor	%mm0, %mm0		C initial carry bit
	jmp	L(entry)

EPILOGUE()
@


1.1.1.1.4.1
log
@file bdiv_q_1.asm was added on branch yamt-pagecache on 2014-05-22 14:09:06 +0000
@
text
@d1 222
@


1.1.1.1.4.2
log
@sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")
@
text
@a0 222
dnl  Intel Pentium-4 mpn_divexact_1 -- mpn by limb exact division.

dnl  Copyright 2001, 2002, 2007, 2011 Free Software Foundation, Inc.
dnl
dnl  This file is part of the GNU MP Library.
dnl
dnl  Rearranged from mpn/x86/pentium4/sse2/dive_1.asm by Marco Bodrato.
dnl
dnl  The GNU MP Library is free software; you can redistribute it and/or
dnl  modify it under the terms of the GNU Lesser General Public License as
dnl  published by the Free Software Foundation; either version 3 of the
dnl  License, or (at your option) any later version.
dnl
dnl  The GNU MP Library is distributed in the hope that it will be useful,
dnl  but WITHOUT ANY WARRANTY; without even the implied warranty of
dnl  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
dnl  Lesser General Public License for more details.
dnl
dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')


C P4: 19.0 cycles/limb

C Pairs of movd's are used to avoid unaligned loads.  Despite the loads not
C being on the dependent chain and there being plenty of cycles available,
C using an unaligned movq on every second iteration measured about 23 c/l.
C

defframe(PARAM_SHIFT,  24)
defframe(PARAM_INVERSE,20)
defframe(PARAM_DIVISOR,16)
defframe(PARAM_SIZE,   12)
defframe(PARAM_SRC,    8)
defframe(PARAM_DST,    4)

	TEXT

C mp_limb_t
C mpn_pi1_bdiv_q_1 (mp_ptr dst, mp_srcptr src, mp_size_t size, mp_limb_t divisor,
C		    mp_limb_t inverse, int shift)
	ALIGN(32)
PROLOGUE(mpn_pi1_bdiv_q_1)
deflit(`FRAME',0)

	movl	PARAM_SIZE, %edx

	movl	PARAM_SRC, %eax

	movl	PARAM_DIVISOR, %ecx

	movd	%ecx, %mm6
	movl	PARAM_SHIFT, %ecx

	movd	%ecx, %mm7		C shift

	C

	movl	PARAM_INVERSE, %ecx
	movd	%ecx, %mm5		C inv

	movl	PARAM_DST, %ecx
	pxor	%mm1, %mm1		C initial carry limb
	pxor	%mm0, %mm0		C initial carry bit

	subl	$1, %edx
	jz	L(done)

	pcmpeqd	%mm4, %mm4
	psrlq	$32, %mm4		C 0x00000000FFFFFFFF

C The dependent chain here is as follows.
C
C					latency
C	psubq	 s = (src-cbit) - climb	   2
C	pmuludq	 q = s*inverse		   8
C	pmuludq	 prod = q*divisor	   8
C	psrlq	 climb = high(prod)	   2
C					  --
C					  20
C
C Yet the loop measures 19.0 c/l, so obviously there's something gained
C there over a straight reading of the chip documentation.

L(top):
	C eax	src, incrementing
	C ebx
	C ecx	dst, incrementing
	C edx	counter, size-1 iterations
	C
	C mm0	carry bit
	C mm1	carry limb
	C mm4	0x00000000FFFFFFFF
	C mm5	inverse
	C mm6	divisor
	C mm7	shift

	movd	(%eax), %mm2
	movd	4(%eax), %mm3
	addl	$4, %eax
	punpckldq %mm3, %mm2

	psrlq	%mm7, %mm2
	pand	%mm4, %mm2		C src
	psubq	%mm0, %mm2		C src - cbit

	psubq	%mm1, %mm2		C src - cbit - climb
	movq	%mm2, %mm0
	psrlq	$63, %mm0		C new cbit

	pmuludq	%mm5, %mm2		C s*inverse
	movd	%mm2, (%ecx)		C q
	addl	$4, %ecx

	movq	%mm6, %mm1
	pmuludq	%mm2, %mm1		C q*divisor
	psrlq	$32, %mm1		C new climb

L(entry):
	subl	$1, %edx
	jnz	L(top)

L(done):
	movd	(%eax), %mm2
	psrlq	%mm7, %mm2		C src
	psubq	%mm0, %mm2		C src - cbit

	psubq	%mm1, %mm2		C src - cbit - climb

	pmuludq	%mm5, %mm2		C s*inverse
	movd	%mm2, (%ecx)		C q

	emms
	ret

EPILOGUE()

	ALIGN(16)
C mp_limb_t mpn_bdiv_q_1 (mp_ptr dst, mp_srcptr src, mp_size_t size,
C                           mp_limb_t divisor);
C
PROLOGUE(mpn_bdiv_q_1)
deflit(`FRAME',0)

	movl	PARAM_SIZE, %edx

	movl	PARAM_DIVISOR, %ecx

	C eax	src
	C ebx
	C ecx	divisor
	C edx	size-1

	movl	%ecx, %eax
	bsfl	%ecx, %ecx		C trailing twos

	shrl	%cl, %eax		C d = divisor without twos
	movd	%eax, %mm6
	movd	%ecx, %mm7		C shift

	shrl	%eax			C d/2

	andl	$127, %eax		C d/2, 7 bits

ifdef(`PIC',`
	LEA(	binvert_limb_table, %ecx)
	movzbl	(%eax,%ecx), %eax		C inv 8 bits
',`
	movzbl	binvert_limb_table(%eax), %eax	C inv 8 bits
')

	C

	movd	%eax, %mm5		C inv

	movd	%eax, %mm0		C inv

	pmuludq	%mm5, %mm5		C inv*inv

	C

	pmuludq	%mm6, %mm5		C inv*inv*d
	paddd	%mm0, %mm0		C 2*inv

	C

	psubd	%mm5, %mm0		C inv = 2*inv - inv*inv*d
	pxor	%mm5, %mm5

	paddd	%mm0, %mm5
	pmuludq	%mm0, %mm0		C inv*inv

	pcmpeqd	%mm4, %mm4
	psrlq	$32, %mm4		C 0x00000000FFFFFFFF

	C

	pmuludq	%mm6, %mm0		C inv*inv*d
	paddd	%mm5, %mm5		C 2*inv

	movl	PARAM_SRC, %eax
	movl	PARAM_DST, %ecx
	pxor	%mm1, %mm1		C initial carry limb

	C

	psubd	%mm0, %mm5		C inv = 2*inv - inv*inv*d

	ASSERT(e,`	C expect d*inv == 1 mod 2^GMP_LIMB_BITS
	pushl	%eax	FRAME_pushl()
	movq	%mm6, %mm0
	pmuludq	%mm5, %mm0
	movd	%mm0, %eax
	cmpl	$1, %eax
	popl	%eax	FRAME_popl()')

	pxor	%mm0, %mm0		C initial carry bit
	jmp	L(entry)

EPILOGUE()
@