head	1.1;
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access;
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	netbsd-11-0-RC4:1.1.1.2
	netbsd-11-0-RC3:1.1.1.2
	netbsd-11-0-RC2:1.1.1.2
	netbsd-11-0-RC1:1.1.1.2
	perseant-exfatfs-base-20250801:1.1.1.2
	netbsd-11:1.1.1.2.0.10
	netbsd-11-base:1.1.1.2
	netbsd-10-1-RELEASE:1.1.1.2
	perseant-exfatfs-base-20240630:1.1.1.2
	perseant-exfatfs:1.1.1.2.0.8
	perseant-exfatfs-base:1.1.1.2
	netbsd-9-4-RELEASE:1.1.1.1
	netbsd-10-0-RELEASE:1.1.1.2
	netbsd-10-0-RC6:1.1.1.2
	netbsd-10-0-RC5:1.1.1.2
	netbsd-10-0-RC4:1.1.1.2
	netbsd-10-0-RC3:1.1.1.2
	netbsd-10-0-RC2:1.1.1.2
	netbsd-10-0-RC1:1.1.1.2
	netbsd-10:1.1.1.2.0.6
	netbsd-10-base:1.1.1.2
	netbsd-9-3-RELEASE:1.1.1.1
	gmp-6-2-1:1.1.1.2
	cjep_sun2x-base1:1.1.1.2
	cjep_sun2x:1.1.1.2.0.4
	cjep_sun2x-base:1.1.1.2
	cjep_staticlib_x-base1:1.1.1.2
	netbsd-9-2-RELEASE:1.1.1.1
	cjep_staticlib_x:1.1.1.2.0.2
	cjep_staticlib_x-base:1.1.1.2
	netbsd-9-1-RELEASE:1.1.1.1
	gmp-6-2-0:1.1.1.2
	phil-wifi-20200421:1.1.1.1
	phil-wifi-20200411:1.1.1.1
	is-mlppp:1.1.1.1.0.8
	is-mlppp-base:1.1.1.1
	phil-wifi-20200406:1.1.1.1
	netbsd-9-0-RELEASE:1.1.1.1
	netbsd-9-0-RC2:1.1.1.1
	netbsd-9-0-RC1:1.1.1.1
	phil-wifi-20191119:1.1.1.1
	netbsd-9:1.1.1.1.0.6
	netbsd-9-base:1.1.1.1
	phil-wifi-20190609:1.1.1.1
	pgoyette-compat-merge-20190127:1.1.1.1
	pgoyette-compat-20190127:1.1.1.1
	pgoyette-compat-20190118:1.1.1.1
	pgoyette-compat-1226:1.1.1.1
	pgoyette-compat-1126:1.1.1.1
	pgoyette-compat-1020:1.1.1.1
	pgoyette-compat-0930:1.1.1.1
	pgoyette-compat-0906:1.1.1.1
	pgoyette-compat-0728:1.1.1.1
	phil-wifi:1.1.1.1.0.4
	phil-wifi-base:1.1.1.1
	pgoyette-compat-0625:1.1.1.1
	pgoyette-compat-0521:1.1.1.1
	pgoyette-compat-0502:1.1.1.1
	pgoyette-compat-0422:1.1.1.1
	pgoyette-compat-0415:1.1.1.1
	pgoyette-compat-0407:1.1.1.1
	pgoyette-compat-0330:1.1.1.1
	pgoyette-compat-0322:1.1.1.1
	pgoyette-compat-0315:1.1.1.1
	pgoyette-compat:1.1.1.1.0.2
	pgoyette-compat-base:1.1.1.1
	gmp-6-1-2:1.1.1.1
	gmp:1.1.1;
locks; strict;
comment	@;; @;


1.1
date	2017.08.22.09.40.48;	author mrg;	state Exp;
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1.1.1.1
date	2017.08.22.09.40.48;	author mrg;	state Exp;
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1.1.1.2
date	2020.09.27.00.27.05;	author mrg;	state Exp;
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desc
@@


1.1
log
@Initial revision
@
text
@dnl  ARM64 mpn_mul_1

dnl  Contributed to the GNU project by Torbjörn Granlund.

dnl  Copyright 2013 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.
dnl
dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of either:
dnl
dnl    * the GNU Lesser General Public License as published by the Free
dnl      Software Foundation; either version 3 of the License, or (at your
dnl      option) any later version.
dnl
dnl  or
dnl
dnl    * the GNU General Public License as published by the Free Software
dnl      Foundation; either version 2 of the License, or (at your option) any
dnl      later version.
dnl
dnl  or both in parallel, as here.
dnl
dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
dnl  for more details.
dnl
dnl  You should have received copies of the GNU General Public License and the
dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
dnl  see https://www.gnu.org/licenses/.

include(`../config.m4')

C	     cycles/limb
C Cortex-A53	 ?
C Cortex-A57	 ?

define(`rp', `x0')
define(`up', `x1')
define(`n',  `x2')
define(`v0', `x3')

ASM_START()
PROLOGUE(mpn_mul_1)
	ldr	x12, [up], #8
	and	x6, n, #3
	and	n, n, #-4
	cbz	x6, L(fi0)
	cmp	x6, #2
	b.cc	L(fi1)
	b.eq	L(fi2)

L(fi3):	mul	x8, x12, v0
	umulh	x13, x12, v0
	cmn	xzr, xzr
	b	L(L3)
L(fi2):	mul	x7, x12, v0
	umulh	x5, x12, v0
	cmn	xzr, xzr
	b	L(L2)
L(fi0):	mul	x9, x12, v0
	umulh	x5, x12, v0
	sub	n, n, #4
	cmn	xzr, xzr
	b	L(L0)
L(fi1):	mul	x10, x12, v0
	umulh	x13, x12, v0
	cmn	xzr, xzr
	cbz	n, L(end)

L(top):	sub	n, n, #4
	ldr	x12, [up], #8
	mul	x6, x12, v0
	umulh	x5, x12, v0
	str	x10, [rp], #8
	adcs	x9, x6, x13
L(L0):	ldr	x12, [up], #8
	mul	x6, x12, v0
	umulh	x13, x12, v0
	str	x9, [rp] ,#8
	adcs	x8, x6, x5
L(L3):	ldr	x12, [up], #8
	mul	x6, x12, v0
	umulh	x5, x12, v0
	str	x8, [rp], #8
	adcs	x7, x6, x13
L(L2):	ldr	x12, [up], #8
	mul	x6, x12, v0
	umulh	x13, x12, v0
	str	x7, [rp], #8
	adcs	x10, x6, x5
	cbnz	n, L(top)

L(end):	str	x10, [rp]
	adc	x0, x13, xzr
	ret
EPILOGUE()
@


1.1.1.1
log
@initial import of GMP 6.1.2.  main changes from 5.1.3 below.

notes:
 - support for thumb-less ARM chips was in our port of 5.1.3, but a
   similar method has been provided upstream now
 - someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

  FEATURES
  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
    on Skylake Pentiums).
  * Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

  BUGS FIXED
  * The public function mpn_com is now correctly declared in gmp.h.
  * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
    some obsolete CPUs.
  * Various problems related to precision for mpf have been fixed.
  * Fixed ABI incompatible stack alignment in calls from assembly code.
  * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
  SPEEDUPS
  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    new ADX instructions.
  * Square root is now faster when the remainder is not needed. Also the speed
    to compute the k-th root improved, for small sizes.
  FEATURES
  * New C++ functions gcd and lcm for mpz_class.
  * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
  * New public mpq_cmp_z function, to efficiently compare rationals with
    integers.
  * Support for more 32-bit arm processors.
  * Support for AVX-less modern x86 CPUs. (Such support might be missing either
    because the CPU vendor chose to disable AVX, or because the running kernel
    lacks AVX context switch support.)
  * Support for NetBSD under Xen; we switch off AVX unconditionally under
    NetBSD since a bug in NetBSD makes AVX fail under Xen.
  MISC
  * Tuned values for FFT multiplications are provided for larger number on
    many platforms.

Changes between GMP version 5.1.* and 6.0.0
  BUGS FIXED
  * The function mpz_invert now considers any number invertible in Z/1Z.
  * The mpn multiply code now handles operands of more than 2^31 limbs
    correctly.  (Note however that the mpz code is limited to 2^32 bits on
    32-bit hosts and 2^37 bits on 64-bit hosts.)
  SPEEDUPS
  * Plain division of large operands is faster and more monotonous in operand
    size.
  * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
    assembly.
  * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
    and vastly expanded assembly support.  Speedup also for the older Core 2
    and Nehalem.
  * Faster mixed arithmetic between mpq_class and double.
  FEATURES
  * Support for new Intel and AMD CPUs.
  * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
    silent multiplication and squaring.
  * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
    side-channel silent division.
  * New public functions mpn_cnd_add_n and mpn_cnd_sub_n.  Side-channel silent
    conditional addition and subtraction.
  * New public function mpn_sec_powm, implementing side-channel silent modexp.
  * New public function mpn_sec_invert, implementing side-channel silent
    modular inversion.
  * Better support for applications which use the mpz_t type, but nevertheless
    need to call some of the lower-level mpn functions.  See the documentation
    for mpz_limbs_read and related functions.
@
text
@@


1.1.1.2
log
@initial import of GMP 6.2.0.  changes include:

- Bug fixes to gmp_snprintf, conversion to double, mpz_powm,
  and mpf_set_str.
- New functions for factorial, primorial, fibonacci, mpz_2fac_ui,
  and mpz_mfac_uiui.
- MIPS r6 cores are now supported.
- Various speeds ups.
@
text
@d5 1
a5 1
dnl  Copyright 2013, 2015, 2017 Free Software Foundation, Inc.
d36 2
a37 9
C Cortex-A53	7.5-8
C Cortex-A57	 7
C Cortex-A72
C X-Gene	 4

C TODO
C  * Start first multiply earlier.

changecom(blah)
d44 50
d95 2
a96 74
PROLOGUE(mpn_mul_1c)
	adds	xzr, xzr, xzr		C clear cy flag
	b	L(com)
EPILOGUE()

PROLOGUE(mpn_mul_1)
	adds	x4, xzr, xzr		C clear register and cy flag
L(com):	lsr	x18, n, #2
	tbnz	n, #0, L(bx1)

L(bx0):	mov	x11, x4
	tbz	n, #1, L(b00)

L(b10):	ldp	x4, x5, [up]
	mul	x8, x4, v0
	umulh	x10, x4, v0
	cbz	x18, L(2)
	ldp	x6, x7, [up,#16]!
	mul	x9, x5, v0
	b	L(mid)-8

L(2):	mul	x9, x5, v0
	b	L(2e)

L(bx1):	ldr	x7, [up],#8
	mul	x9, x7, v0
	umulh	x11, x7, v0
	adds	x9, x9, x4
	str	x9, [rp],#8
	tbnz	n, #1, L(b10)

L(b01):	cbz	x18, L(1)

L(b00):	ldp	x6, x7, [up]
	mul	x8, x6, v0
	umulh	x10, x6, v0
	ldp	x4, x5, [up,#16]
	mul	x9, x7, v0
	adcs	x12, x8, x11
	umulh	x11, x7, v0
	add	rp, rp, #16
	sub	x18, x18, #1
	cbz	x18, L(end)

	ALIGN(16)
L(top):	mul	x8, x4, v0
	ldp	x6, x7, [up,#32]!
	adcs	x13, x9, x10
	umulh	x10, x4, v0
	mul	x9, x5, v0
	stp	x12, x13, [rp,#-16]
	adcs	x12, x8, x11
	umulh	x11, x5, v0
L(mid):	mul	x8, x6, v0
	ldp	x4, x5, [up,#16]
	adcs	x13, x9, x10
	umulh	x10, x6, v0
	mul	x9, x7, v0
	stp	x12, x13, [rp],#32
	adcs	x12, x8, x11
	umulh	x11, x7, v0
	sub	x18, x18, #1
	cbnz	x18, L(top)

L(end):	mul	x8, x4, v0
	adcs	x13, x9, x10
	umulh	x10, x4, v0
	mul	x9, x5, v0
	stp	x12, x13, [rp,#-16]
L(2e):	adcs	x12, x8, x11
	umulh	x11, x5, v0
	adcs	x13, x9, x10
	stp	x12, x13, [rp]
L(1):	adc	x0, x11, xzr
@