head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.2 netbsd-11-0-RC3:1.1.1.2 netbsd-11-0-RC2:1.1.1.2 netbsd-11-0-RC1:1.1.1.2 perseant-exfatfs-base-20250801:1.1.1.2 netbsd-11:1.1.1.2.0.18 netbsd-11-base:1.1.1.2 netbsd-10-1-RELEASE:1.1.1.2 perseant-exfatfs-base-20240630:1.1.1.2 perseant-exfatfs:1.1.1.2.0.16 perseant-exfatfs-base:1.1.1.2 netbsd-8-3-RELEASE:1.1.1.1 netbsd-9-4-RELEASE:1.1.1.2 netbsd-10-0-RELEASE:1.1.1.2 netbsd-10-0-RC6:1.1.1.2 netbsd-10-0-RC5:1.1.1.2 netbsd-10-0-RC4:1.1.1.2 netbsd-10-0-RC3:1.1.1.2 netbsd-10-0-RC2:1.1.1.2 netbsd-10-0-RC1:1.1.1.2 netbsd-10:1.1.1.2.0.14 netbsd-10-base:1.1.1.2 netbsd-9-3-RELEASE:1.1.1.2 gmp-6-2-1:1.1.1.2 cjep_sun2x-base1:1.1.1.2 cjep_sun2x:1.1.1.2.0.12 cjep_sun2x-base:1.1.1.2 cjep_staticlib_x-base1:1.1.1.2 netbsd-9-2-RELEASE:1.1.1.2 cjep_staticlib_x:1.1.1.2.0.10 cjep_staticlib_x-base:1.1.1.2 netbsd-9-1-RELEASE:1.1.1.2 gmp-6-2-0:1.1.1.2 phil-wifi-20200421:1.1.1.2 phil-wifi-20200411:1.1.1.2 is-mlppp:1.1.1.2.0.8 is-mlppp-base:1.1.1.2 phil-wifi-20200406:1.1.1.2 netbsd-8-2-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.2 netbsd-9-0-RC2:1.1.1.2 netbsd-9-0-RC1:1.1.1.2 phil-wifi-20191119:1.1.1.2 netbsd-9:1.1.1.2.0.6 netbsd-9-base:1.1.1.2 phil-wifi-20190609:1.1.1.2 netbsd-8-1-RELEASE:1.1.1.1 netbsd-8-1-RC1:1.1.1.1 pgoyette-compat-merge-20190127:1.1.1.2 pgoyette-compat-20190127:1.1.1.2 pgoyette-compat-20190118:1.1.1.2 pgoyette-compat-1226:1.1.1.2 pgoyette-compat-1126:1.1.1.2 pgoyette-compat-1020:1.1.1.2 pgoyette-compat-0930:1.1.1.2 pgoyette-compat-0906:1.1.1.2 netbsd-7-2-RELEASE:1.1.1.1 pgoyette-compat-0728:1.1.1.2 netbsd-8-0-RELEASE:1.1.1.1 phil-wifi:1.1.1.2.0.4 phil-wifi-base:1.1.1.2 pgoyette-compat-0625:1.1.1.2 netbsd-8-0-RC2:1.1.1.1 pgoyette-compat-0521:1.1.1.2 pgoyette-compat-0502:1.1.1.2 pgoyette-compat-0422:1.1.1.2 netbsd-8-0-RC1:1.1.1.1 pgoyette-compat-0415:1.1.1.2 pgoyette-compat-0407:1.1.1.2 pgoyette-compat-0330:1.1.1.2 pgoyette-compat-0322:1.1.1.2 pgoyette-compat-0315:1.1.1.2 netbsd-7-1-2-RELEASE:1.1.1.1 pgoyette-compat:1.1.1.2.0.2 pgoyette-compat-base:1.1.1.2 netbsd-7-1-1-RELEASE:1.1.1.1 matt-nb8-mediatek:1.1.1.1.0.26 matt-nb8-mediatek-base:1.1.1.1 gmp-6-1-2:1.1.1.2 perseant-stdc-iso10646:1.1.1.1.0.24 perseant-stdc-iso10646-base:1.1.1.1 netbsd-8:1.1.1.1.0.22 netbsd-8-base:1.1.1.1 prg-localcount2-base3:1.1.1.1 prg-localcount2-base2:1.1.1.1 prg-localcount2-base1:1.1.1.1 prg-localcount2:1.1.1.1.0.20 prg-localcount2-base:1.1.1.1 pgoyette-localcount-20170426:1.1.1.1 bouyer-socketcan-base1:1.1.1.1 pgoyette-localcount-20170320:1.1.1.1 netbsd-7-1:1.1.1.1.0.18 netbsd-7-1-RELEASE:1.1.1.1 netbsd-7-1-RC2:1.1.1.1 netbsd-7-nhusb-base-20170116:1.1.1.1 bouyer-socketcan:1.1.1.1.0.16 bouyer-socketcan-base:1.1.1.1 pgoyette-localcount-20170107:1.1.1.1 netbsd-7-1-RC1:1.1.1.1 pgoyette-localcount-20161104:1.1.1.1 netbsd-7-0-2-RELEASE:1.1.1.1 localcount-20160914:1.1.1.1 netbsd-7-nhusb:1.1.1.1.0.14 netbsd-7-nhusb-base:1.1.1.1 pgoyette-localcount-20160806:1.1.1.1 pgoyette-localcount-20160726:1.1.1.1 pgoyette-localcount:1.1.1.1.0.12 pgoyette-localcount-base:1.1.1.1 netbsd-7-0-1-RELEASE:1.1.1.1 netbsd-7-0:1.1.1.1.0.10 netbsd-7-0-RELEASE:1.1.1.1 netbsd-7-0-RC3:1.1.1.1 netbsd-7-0-RC2:1.1.1.1 netbsd-7-0-RC1:1.1.1.1 tls-maxphys-base:1.1.1.1 tls-maxphys:1.1.1.1.0.8 netbsd-7:1.1.1.1.0.6 netbsd-7-base:1.1.1.1 yamt-pagecache:1.1.1.1.0.4 yamt-pagecache-base9:1.1.1.1 tls-earlyentropy:1.1.1.1.0.2 tls-earlyentropy-base:1.1.1.1 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.1.1.1 riastradh-drm2-base3:1.1.1.1 gmp-5-1-3:1.1.1.1 gmp:1.1.1; locks; strict; comment @;; @; 1.1 date 2013.11.29.07.49.48; author mrg; state Exp; branches 1.1.1.1; next ; commitid L2Av4PuGmdoL39fx; 1.1.1.1 date 2013.11.29.07.49.48; author mrg; state Exp; branches 1.1.1.1.4.1 1.1.1.1.8.1; next 1.1.1.2; commitid L2Av4PuGmdoL39fx; 1.1.1.2 date 2017.08.22.09.40.48; author mrg; state Exp; branches; next ; commitid W5kmAIk8hwVpSb4A; 1.1.1.1.4.1 date 2013.11.29.07.49.48; author yamt; state dead; branches; next 1.1.1.1.4.2; commitid nx2BSsHy0NPeAxBx; 1.1.1.1.4.2 date 2014.05.22.14.09.00; author yamt; state Exp; branches; next ; commitid nx2BSsHy0NPeAxBx; 1.1.1.1.8.1 date 2013.11.29.07.49.48; author tls; state dead; branches; next 1.1.1.1.8.2; commitid jTnpym9Qu0o4R1Nx; 1.1.1.1.8.2 date 2014.08.19.23.59.49; author tls; state Exp; branches; next ; commitid jTnpym9Qu0o4R1Nx; desc @@ 1.1 log @Initial revision @ text @dnl ARM v6t2 mpn_divrem_1 and mpn_preinv_divrem_1. dnl Contributed to the GNU project by Torbjorn Granlund. dnl Copyright 2012 Free Software Foundation, Inc. dnl This file is part of the GNU MP Library. dnl The GNU MP Library is free software; you can redistribute it and/or modify dnl it under the terms of the GNU Lesser General Public License as published dnl by the Free Software Foundation; either version 3 of the License, or (at dnl your option) any later version. dnl The GNU MP Library is distributed in the hope that it will be useful, but dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public dnl License for more details. dnl You should have received a copy of the GNU Lesser General Public License dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. include(`../config.m4') C norm unorm frac C StrongARM ? C XScale ? C Cortex-A8 ? C Cortex-A9 13 14 13 C Cortex-A15 ? C TODO C * Optimise inner-loops better, they could likely run a cycle or two faster. C * Decrease register usage, streamline non-loop code. define(`qp_arg', `r0') define(`fn', `r1') define(`up_arg', `r2') define(`n_arg', `r3') define(`d_arg', `0') define(`dinv_arg',`4') define(`cnt_arg', `8') define(`n', `r9') define(`qp', `r5') define(`up', `r6') define(`cnt', `r7') define(`tnc', `r10') define(`dinv', `r0') define(`d', `r4') ASM_START() PROLOGUE(mpn_preinv_divrem_1) stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} ldr d, [sp, #9*4+d_arg] ldr cnt, [sp, #9*4+cnt_arg] str r1, [sp, #9*4+d_arg] C reuse d stack slot for fn sub n, r3, #1 add r3, r1, n cmp d, #0 add qp, qp_arg, r3, lsl #2 C put qp at Q[] end add up, up_arg, n, lsl #2 C put up at U[] end ldr dinv, [sp, #9*4+dinv_arg] blt L(nent) b L(uent) EPILOGUE() PROLOGUE(mpn_divrem_1) stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} sub n, r3, #1 ldr d, [sp, #9*4+d_arg] C d str r1, [sp, #9*4+d_arg] C reuse d stack slot for fn add r3, r1, n cmp d, #0 add qp, qp_arg, r3, lsl #2 C put qp at Q[] end add up, up_arg, n, lsl #2 C put up at U[] end blt L(normalised) L(unnorm): clz cnt, d mov r0, d, lsl cnt C pass d << cnt bl mpn_invert_limb L(uent): mov d, d, lsl cnt C d <<= cnt cmp n, #0 mov r1, #0 C r blt L(frac) ldr r11, [up, #0] rsb tnc, cnt, #32 mov r1, r11, lsr tnc mov r11, r11, lsl cnt beq L(uend) ldr r3, [up, #-4]! orr r2, r11, r3, lsr tnc b L(mid) L(utop): mls r1, d, r8, r11 mov r11, r3, lsl cnt ldr r3, [up, #-4]! cmp r1, r2 addhi r1, r1, d subhi r8, r8, #1 orr r2, r11, r3, lsr tnc cmp r1, d bcs L(ufx) L(uok): str r8, [qp], #-4 L(mid): add r8, r1, #1 mov r11, r2 umlal r2, r8, r1, dinv subs n, n, #1 bne L(utop) mls r1, d, r8, r11 mov r11, r3, lsl cnt cmp r1, r2 addhi r1, r1, d subhi r8, r8, #1 cmp r1, d rsbcs r1, d, r1 addcs r8, r8, #1 str r8, [qp], #-4 L(uend):add r8, r1, #1 mov r2, r11 umlal r2, r8, r1, dinv mls r1, d, r8, r11 cmp r1, r2 addhi r1, r1, d subhi r8, r8, #1 cmp r1, d rsbcs r1, d, r1 addcs r8, r8, #1 str r8, [qp], #-4 L(frac): ldr r2, [sp, #9*4+d_arg] C fn cmp r2, #0 beq L(fend) L(ftop):mov r6, #0 add r3, r1, #1 umlal r6, r3, r1, dinv mov r8, #0 mls r1, d, r3, r8 cmp r1, r6 addhi r1, r1, d subhi r3, r3, #1 subs r2, r2, #1 str r3, [qp], #-4 bne L(ftop) L(fend):mov r11, r1, lsr cnt L(rtn): mov r0, r11 ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} L(normalised): mov r0, d bl mpn_invert_limb L(nent): cmp n, #0 mov r11, #0 C r blt L(nend) ldr r11, [up, #0] cmp r11, d movlo r2, #0 C hi q limb movhs r2, #1 C hi q limb subhs r11, r11, d str r2, [qp], #-4 cmp n, #0 beq L(nend) L(ntop):ldr r1, [up, #-4]! add r12, r11, #1 umlal r1, r12, r11, dinv ldr r3, [up, #0] mls r11, d, r12, r3 cmp r11, r1 addhi r11, r11, d subhi r12, r12, #1 cmp d, r11 bls L(nfx) L(nok): str r12, [qp], #-4 subs n, n, #1 bne L(ntop) L(nend):mov r1, r11 C r mov cnt, #0 C shift cnt b L(frac) L(nfx): add r12, r12, #1 rsb r11, d, r11 b L(nok) L(ufx): rsb r1, d, r1 add r8, r8, #1 b L(uok) EPILOGUE() @ 1.1.1.1 log @initial import GMP 5.1.3 sources. changes include: fixes for: - mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec - mpz_powm_ui - AMD family 11h - mpz_powm_sec and mpn_powm_sec - ASSERT() fixes - gcd, gcdext, and invert function fixes - some PPC division operations @ text @@ 1.1.1.2 log @initial import of GMP 6.1.2. main changes from 5.1.3 below. notes: - support for thumb-less ARM chips was in our port of 5.1.3, but a similar method has been provided upstream now - someone should look at the AVX failure reports, and fix them Changes between GMP version 6.1.0 and 6.1.1 FEATURES * Work around faulty cpuid on some recent Intel chips (this allows GMP to run on Skylake Pentiums). * Support thumb-less ARM chips. Changes between GMP version 6.0.* and 6.1.0 BUGS FIXED * The public function mpn_com is now correctly declared in gmp.h. * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for some obsolete CPUs. * Various problems related to precision for mpf have been fixed. * Fixed ABI incompatible stack alignment in calls from assembly code. * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI. SPEEDUPS * Speedup for Intel Broadwell and Skylake through assembly code making use of new ADX instructions. * Square root is now faster when the remainder is not needed. Also the speed to compute the k-th root improved, for small sizes. FEATURES * New C++ functions gcd and lcm for mpz_class. * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap. * New public mpq_cmp_z function, to efficiently compare rationals with integers. * Support for more 32-bit arm processors. * Support for AVX-less modern x86 CPUs. (Such support might be missing either because the CPU vendor chose to disable AVX, or because the running kernel lacks AVX context switch support.) * Support for NetBSD under Xen; we switch off AVX unconditionally under NetBSD since a bug in NetBSD makes AVX fail under Xen. MISC * Tuned values for FFT multiplications are provided for larger number on many platforms. Changes between GMP version 5.1.* and 6.0.0 BUGS FIXED * The function mpz_invert now considers any number invertible in Z/1Z. * The mpn multiply code now handles operands of more than 2^31 limbs correctly. (Note however that the mpz code is limited to 2^32 bits on 32-bit hosts and 2^37 bits on 64-bit hosts.) SPEEDUPS * Plain division of large operands is faster and more monotonous in operand size. * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved assembly. * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten and vastly expanded assembly support. Speedup also for the older Core 2 and Nehalem. * Faster mixed arithmetic between mpq_class and double. FEATURES * Support for new Intel and AMD CPUs. * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel silent multiplication and squaring. * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing side-channel silent division. * New public functions mpn_cnd_add_n and mpn_cnd_sub_n. Side-channel silent conditional addition and subtraction. * New public function mpn_sec_powm, implementing side-channel silent modexp. * New public function mpn_sec_invert, implementing side-channel silent modular inversion. * Better support for applications which use the mpz_t type, but nevertheless need to call some of the lower-level mpn functions. See the documentation for mpz_limbs_read and related functions. @ text @d3 1 a3 1 dnl Contributed to the GNU project by Torbjörn Granlund. d8 1 a8 1 dnl d10 4 a13 14 dnl it under the terms of either: dnl dnl * the GNU Lesser General Public License as published by the Free dnl Software Foundation; either version 3 of the License, or (at your dnl option) any later version. dnl dnl or dnl dnl * the GNU General Public License as published by the Free Software dnl Foundation; either version 2 of the License, or (at your option) any dnl later version. dnl dnl or both in parallel, as here. dnl d16 5 a20 6 dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License dnl for more details. dnl dnl You should have received copies of the GNU General Public License and the dnl GNU Lesser General Public License along with the GNU MP Library. If not, dnl see https://www.gnu.org/licenses/. d25 5 a29 6 C StrongARM - - - C XScale - - - C Cortex-A7 ? ? ? C Cortex-A8 ? ? ? C Cortex-A9 13 14 13 C Cortex-A15 11.4 11.8 11.1 @ 1.1.1.1.8.1 log @file divrem_1.asm was added on branch tls-maxphys on 2014-08-19 23:59:49 +0000 @ text @d1 200 @ 1.1.1.1.8.2 log @Rebase to HEAD as of a few days ago. @ text @a0 200 dnl ARM v6t2 mpn_divrem_1 and mpn_preinv_divrem_1. dnl Contributed to the GNU project by Torbjorn Granlund. dnl Copyright 2012 Free Software Foundation, Inc. dnl This file is part of the GNU MP Library. dnl The GNU MP Library is free software; you can redistribute it and/or modify dnl it under the terms of the GNU Lesser General Public License as published dnl by the Free Software Foundation; either version 3 of the License, or (at dnl your option) any later version. dnl The GNU MP Library is distributed in the hope that it will be useful, but dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public dnl License for more details. dnl You should have received a copy of the GNU Lesser General Public License dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. include(`../config.m4') C norm unorm frac C StrongARM ? C XScale ? C Cortex-A8 ? C Cortex-A9 13 14 13 C Cortex-A15 ? C TODO C * Optimise inner-loops better, they could likely run a cycle or two faster. C * Decrease register usage, streamline non-loop code. define(`qp_arg', `r0') define(`fn', `r1') define(`up_arg', `r2') define(`n_arg', `r3') define(`d_arg', `0') define(`dinv_arg',`4') define(`cnt_arg', `8') define(`n', `r9') define(`qp', `r5') define(`up', `r6') define(`cnt', `r7') define(`tnc', `r10') define(`dinv', `r0') define(`d', `r4') ASM_START() PROLOGUE(mpn_preinv_divrem_1) stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} ldr d, [sp, #9*4+d_arg] ldr cnt, [sp, #9*4+cnt_arg] str r1, [sp, #9*4+d_arg] C reuse d stack slot for fn sub n, r3, #1 add r3, r1, n cmp d, #0 add qp, qp_arg, r3, lsl #2 C put qp at Q[] end add up, up_arg, n, lsl #2 C put up at U[] end ldr dinv, [sp, #9*4+dinv_arg] blt L(nent) b L(uent) EPILOGUE() PROLOGUE(mpn_divrem_1) stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} sub n, r3, #1 ldr d, [sp, #9*4+d_arg] C d str r1, [sp, #9*4+d_arg] C reuse d stack slot for fn add r3, r1, n cmp d, #0 add qp, qp_arg, r3, lsl #2 C put qp at Q[] end add up, up_arg, n, lsl #2 C put up at U[] end blt L(normalised) L(unnorm): clz cnt, d mov r0, d, lsl cnt C pass d << cnt bl mpn_invert_limb L(uent): mov d, d, lsl cnt C d <<= cnt cmp n, #0 mov r1, #0 C r blt L(frac) ldr r11, [up, #0] rsb tnc, cnt, #32 mov r1, r11, lsr tnc mov r11, r11, lsl cnt beq L(uend) ldr r3, [up, #-4]! orr r2, r11, r3, lsr tnc b L(mid) L(utop): mls r1, d, r8, r11 mov r11, r3, lsl cnt ldr r3, [up, #-4]! cmp r1, r2 addhi r1, r1, d subhi r8, r8, #1 orr r2, r11, r3, lsr tnc cmp r1, d bcs L(ufx) L(uok): str r8, [qp], #-4 L(mid): add r8, r1, #1 mov r11, r2 umlal r2, r8, r1, dinv subs n, n, #1 bne L(utop) mls r1, d, r8, r11 mov r11, r3, lsl cnt cmp r1, r2 addhi r1, r1, d subhi r8, r8, #1 cmp r1, d rsbcs r1, d, r1 addcs r8, r8, #1 str r8, [qp], #-4 L(uend):add r8, r1, #1 mov r2, r11 umlal r2, r8, r1, dinv mls r1, d, r8, r11 cmp r1, r2 addhi r1, r1, d subhi r8, r8, #1 cmp r1, d rsbcs r1, d, r1 addcs r8, r8, #1 str r8, [qp], #-4 L(frac): ldr r2, [sp, #9*4+d_arg] C fn cmp r2, #0 beq L(fend) L(ftop):mov r6, #0 add r3, r1, #1 umlal r6, r3, r1, dinv mov r8, #0 mls r1, d, r3, r8 cmp r1, r6 addhi r1, r1, d subhi r3, r3, #1 subs r2, r2, #1 str r3, [qp], #-4 bne L(ftop) L(fend):mov r11, r1, lsr cnt L(rtn): mov r0, r11 ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} L(normalised): mov r0, d bl mpn_invert_limb L(nent): cmp n, #0 mov r11, #0 C r blt L(nend) ldr r11, [up, #0] cmp r11, d movlo r2, #0 C hi q limb movhs r2, #1 C hi q limb subhs r11, r11, d str r2, [qp], #-4 cmp n, #0 beq L(nend) L(ntop):ldr r1, [up, #-4]! add r12, r11, #1 umlal r1, r12, r11, dinv ldr r3, [up, #0] mls r11, d, r12, r3 cmp r11, r1 addhi r11, r11, d subhi r12, r12, #1 cmp d, r11 bls L(nfx) L(nok): str r12, [qp], #-4 subs n, n, #1 bne L(ntop) L(nend):mov r1, r11 C r mov cnt, #0 C shift cnt b L(frac) L(nfx): add r12, r12, #1 rsb r11, d, r11 b L(nok) L(ufx): rsb r1, d, r1 add r8, r8, #1 b L(uok) EPILOGUE() @ 1.1.1.1.4.1 log @file divrem_1.asm was added on branch yamt-pagecache on 2014-05-22 14:09:00 +0000 @ text @d1 200 @ 1.1.1.1.4.2 log @sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments") @ text @a0 200 dnl ARM v6t2 mpn_divrem_1 and mpn_preinv_divrem_1. dnl Contributed to the GNU project by Torbjorn Granlund. dnl Copyright 2012 Free Software Foundation, Inc. dnl This file is part of the GNU MP Library. dnl The GNU MP Library is free software; you can redistribute it and/or modify dnl it under the terms of the GNU Lesser General Public License as published dnl by the Free Software Foundation; either version 3 of the License, or (at dnl your option) any later version. dnl The GNU MP Library is distributed in the hope that it will be useful, but dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public dnl License for more details. dnl You should have received a copy of the GNU Lesser General Public License dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. include(`../config.m4') C norm unorm frac C StrongARM ? C XScale ? C Cortex-A8 ? C Cortex-A9 13 14 13 C Cortex-A15 ? C TODO C * Optimise inner-loops better, they could likely run a cycle or two faster. C * Decrease register usage, streamline non-loop code. define(`qp_arg', `r0') define(`fn', `r1') define(`up_arg', `r2') define(`n_arg', `r3') define(`d_arg', `0') define(`dinv_arg',`4') define(`cnt_arg', `8') define(`n', `r9') define(`qp', `r5') define(`up', `r6') define(`cnt', `r7') define(`tnc', `r10') define(`dinv', `r0') define(`d', `r4') ASM_START() PROLOGUE(mpn_preinv_divrem_1) stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} ldr d, [sp, #9*4+d_arg] ldr cnt, [sp, #9*4+cnt_arg] str r1, [sp, #9*4+d_arg] C reuse d stack slot for fn sub n, r3, #1 add r3, r1, n cmp d, #0 add qp, qp_arg, r3, lsl #2 C put qp at Q[] end add up, up_arg, n, lsl #2 C put up at U[] end ldr dinv, [sp, #9*4+dinv_arg] blt L(nent) b L(uent) EPILOGUE() PROLOGUE(mpn_divrem_1) stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} sub n, r3, #1 ldr d, [sp, #9*4+d_arg] C d str r1, [sp, #9*4+d_arg] C reuse d stack slot for fn add r3, r1, n cmp d, #0 add qp, qp_arg, r3, lsl #2 C put qp at Q[] end add up, up_arg, n, lsl #2 C put up at U[] end blt L(normalised) L(unnorm): clz cnt, d mov r0, d, lsl cnt C pass d << cnt bl mpn_invert_limb L(uent): mov d, d, lsl cnt C d <<= cnt cmp n, #0 mov r1, #0 C r blt L(frac) ldr r11, [up, #0] rsb tnc, cnt, #32 mov r1, r11, lsr tnc mov r11, r11, lsl cnt beq L(uend) ldr r3, [up, #-4]! orr r2, r11, r3, lsr tnc b L(mid) L(utop): mls r1, d, r8, r11 mov r11, r3, lsl cnt ldr r3, [up, #-4]! cmp r1, r2 addhi r1, r1, d subhi r8, r8, #1 orr r2, r11, r3, lsr tnc cmp r1, d bcs L(ufx) L(uok): str r8, [qp], #-4 L(mid): add r8, r1, #1 mov r11, r2 umlal r2, r8, r1, dinv subs n, n, #1 bne L(utop) mls r1, d, r8, r11 mov r11, r3, lsl cnt cmp r1, r2 addhi r1, r1, d subhi r8, r8, #1 cmp r1, d rsbcs r1, d, r1 addcs r8, r8, #1 str r8, [qp], #-4 L(uend):add r8, r1, #1 mov r2, r11 umlal r2, r8, r1, dinv mls r1, d, r8, r11 cmp r1, r2 addhi r1, r1, d subhi r8, r8, #1 cmp r1, d rsbcs r1, d, r1 addcs r8, r8, #1 str r8, [qp], #-4 L(frac): ldr r2, [sp, #9*4+d_arg] C fn cmp r2, #0 beq L(fend) L(ftop):mov r6, #0 add r3, r1, #1 umlal r6, r3, r1, dinv mov r8, #0 mls r1, d, r3, r8 cmp r1, r6 addhi r1, r1, d subhi r3, r3, #1 subs r2, r2, #1 str r3, [qp], #-4 bne L(ftop) L(fend):mov r11, r1, lsr cnt L(rtn): mov r0, r11 ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} L(normalised): mov r0, d bl mpn_invert_limb L(nent): cmp n, #0 mov r11, #0 C r blt L(nend) ldr r11, [up, #0] cmp r11, d movlo r2, #0 C hi q limb movhs r2, #1 C hi q limb subhs r11, r11, d str r2, [qp], #-4 cmp n, #0 beq L(nend) L(ntop):ldr r1, [up, #-4]! add r12, r11, #1 umlal r1, r12, r11, dinv ldr r3, [up, #0] mls r11, d, r12, r3 cmp r11, r1 addhi r11, r11, d subhi r12, r12, #1 cmp d, r11 bls L(nfx) L(nok): str r12, [qp], #-4 subs n, n, #1 bne L(ntop) L(nend):mov r1, r11 C r mov cnt, #0 C shift cnt b L(frac) L(nfx): add r12, r12, #1 rsb r11, d, r11 b L(nok) L(ufx): rsb r1, d, r1 add r8, r8, #1 b L(uok) EPILOGUE() @