head	1.1;
branch	1.1.1;
access;
symbols
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desc
@@


1.1
log
@Initial revision
@
text
@dnl  ARM v6 mpn_sqr_basecase.

dnl  Contributed to the GNU project by Torbjorn Granlund.

dnl  Copyright 2012 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C Code structure:
C
C
C        m_2(0m4)        m_2(2m4)        m_2(1m4)        m_2(3m4)
C           |               |               |               |
C           |               |               |               |
C           |               |               |               |
C          \|/             \|/             \|/             \|/
C              ____________                   ____________
C             /            \                 /            \
C            \|/            \               \|/            \
C         am_2(3m4)       am_2(1m4)       am_2(0m4)       am_2(2m4)
C            \            /|\                \            /|\
C             \____________/                  \____________/
C                       \                        /
C                        \                      /
C                         \                    /
C                       tail(0m2)          tail(1m2)
C                            \              /
C                             \            /
C                            sqr_diag_addlsh1

C TODO
C  * Further tweak counter and updates in outer loops.  (This could save
C    perhaps 5n cycles).
C  * Try to use fewer register.  Perhaps coalesce r9 branch target and n_saved.
C    (This could save 2-3 cycles for n > 4.)
C  * Optimise sqr_diag_addlsh1 loop.  (This could save O(n) cycles.)
C  * Implement larger final corners (xit/tix).  Also stop loops earlier
C    suppressing writes of upper-most rp[] values.  (This could save 10-20
C    cycles for n > 4.)
C  * Is the branch really faster than discrete branches?

define(`rp',      r0)
define(`up',      r1)
define(`n',       r2)

define(`v0',      r3)
define(`v1',      r6)
define(`i',       r8)
define(`n_saved', r14)
define(`cya',     r11)
define(`cyb',     r12)
define(`u0',      r7)
define(`u1',      r9)

ASM_START()
PROLOGUE(mpn_sqr_basecase)
	and	r12, n, #3
	cmp	n, #4
	addgt	r12, r12, #4
	add	pc, pc, r12, lsl #2
	nop
	b	L(4)
	b	L(1)
	b	L(2)
	b	L(3)
	b	L(0m4)
	b	L(1m4)
	b	L(2m4)
	b	L(3m4)


L(1m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_2m4)-.-8
	ldm	up, {v0,v1,u0}
	sub	up, up, #4
	mov	cyb, #0
	mov	r5, #0
	umull	r4, cya, v1, v0
	str	r4, [rp], #-12
	mov	r4, #0
	b	L(ko0)

L(3m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_0m4)-.-8
	ldm	up, {v0,v1,u0}
	add	up, up, #4
	mov	cyb, #0
	mov	r5, #0
	umull	r4, cya, v1, v0
	str	r4, [rp], #-4
	mov	r4, #0
	b	L(ko2)

L(2m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_3m4)-.-8
	ldm	up, {v0,v1,u1}
	mov	cyb, #0
	mov	r4, #0
	umull	r5, cya, v1, v0
	str	r5, [rp], #-8
	mov	r5, #0
	b	L(ko1)

L(0m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_1m4)-.-8
	ldm	up, {v0,v1,u1}
	mov	cyb, #0
	mov	r4, #0
	add	up, up, #8
	umull	r5, cya, v1, v0
	str	r5, [rp, #0]
	mov	r5, #0

L(top):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	mov	r4, #0
	umaal	r5, cyb, u1, v1
L(ko2):	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	mov	r5, #0
	umaal	r4, cyb, u0, v1
L(ko1):	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	mov	r4, #0
	umaal	r5, cyb, u1, v1
L(ko0):	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	mov	r5, #0
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(top)
	bx	r10

L(evnloop):
	subs	i, n, #4
	sub	n, n, #2
	blt	L(tix)
	ldm	up, {v0,v1,u0}
	add	up, up, #4
	mov	cya, #0
	mov	cyb, #0
	ldm	rp, {r4,r5}
	sub	rp, rp, #4
	umaal	r4, cya, v1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	b	L(lo2)
L(ua2):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
L(lo2):	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua2)
L(am2_0m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	sub	i, n, #4
	sub	n, n, #2
	ldm	up, {v0,v1,u0}
	sub	up, up, #4
	mov	cya, #0
	mov	cyb, #0
	ldr	r4, [rp, #24]
	ldr	r5, [rp, #28]
	add	rp, rp, #12
	umaal	r4, cya, v1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	b	L(lo0)
L(ua0):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
L(lo0):	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua0)
L(am2_2m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	add	rp, rp, #24
	b	L(evnloop)


L(oddloop):
	subs	i, n, #4
	sub	n, n, #2
	blt	L(xit)
	ldm	up, {v0,v1,u1}
	mov	cya, #0
	mov	cyb, #0
	sub	rp, rp, #8
	ldr	r5, [rp, #8]
	ldr	r4, [rp, #12]
	umaal	r5, cya, v1, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	b	L(lo1)
L(ua1):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
L(lo1):	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua1)
L(am2_3m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	add	rp, rp, #24
	subs	i, n, #4
	sub	n, n, #2
	ldm	up, {v0,v1,u1}
	mov	cya, #0
	mov	cyb, #0
	ldr	r5, [rp, #0]
	ldr	r4, [rp, #4]
	add	up, up, #8
	umaal	r5, cya, v1, v0
	str	r5, [rp, #0]
	ldr	r5, [rp, #8]
	bls	L(e3)
L(ua3):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua3)
L(e3):
L(am2_1m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	add	rp, rp, #24
	b	L(oddloop)

L(xit):	ldm	up!, {v0,u0}
	ldr	cya, [rp], #12
	mov	cyb, #0
	umaal	cya, cyb, u0, v0
	b	L(sqr_diag_addlsh1)

L(tix):	ldm	up!, {v0,v1,u0}
	ldm	rp, {r4,r5}
	mov	cya, #0
	mov	cyb, #0
	umaal	r4, cya, v1, v0
	umaal	r5, cya, u0, v0
	stm	rp, {r4,r5}
	umaal	cya, cyb, u0, v1
	add	rp, rp, #20
C	b	L(sqr_diag_addlsh1)


define(`w0',  r6)
define(`w1',  r7)
define(`w2',  r8)
define(`rbx', r9)

L(sqr_diag_addlsh1):
	str	cya, [rp, #-12]
	str	cyb, [rp, #-8]
	sub	n, n_saved, #1
	sub	up, up, n_saved, lsl #2
	sub	rp, rp, n_saved, lsl #3
	ldr	r3, [up], #4
	umull	w1, r5, r3, r3
	mov	w2, #0
C	cmn	r0, #0			C clear cy (already clear by luck)
	b	L(lm)

L(tsd):	adds	w0, w0, rbx
	adcs	w1, w1, r4
	str	w0, [rp, #0]
L(lm):	ldr	w0, [rp, #4]
	str	w1, [rp, #4]
	ldr	w1, [rp, #8]!
	add	rbx, r5, w2
	adcs	w0, w0, w0
	ldr	r3, [up], #4
	adcs	w1, w1, w1
	mov	w2, #0
	adc	w2, w2, w2
	umull	r4, r5, r3, r3
	subs	n, n, #1
	bne	L(tsd)

	adds	w0, w0, rbx
	adcs	w1, w1, r4
	adc	w2, r5, w2
	stm	rp, {w0,w1,w2}

	pop	{r4-r10,r11,pc}


C Straight line code for n <= 4

L(1):	ldr	r3, [up, #0]
	umull	r1, r2, r3, r3
	stm	rp, {r1,r2}
	bx	r14

L(2):	push	{r4-r5}
	ldm	up, {r5,r12}
	umull	r1, r2, r5, r5
	umull	r3, r4, r12, r12
	umull	r5, r12, r5, r12
	adds	r5, r5, r5
	adcs	r12, r12, r12
	adc	r4, r4, #0
	adds	r2, r2, r5
	adcs	r3, r3, r12
	adc	r4, r4, #0
	stm	rp, {r1,r2,r3,r4}
	pop	{r4-r5}
	bx	r14

L(3):	push	{r4-r11}
	ldm	up, {r7,r8,r9}
	umull	r1, r2, r7, r7
	umull	r3, r4, r8, r8
	umull	r5, r6, r9, r9
	umull	r10, r11, r7, r8
	mov	r12, #0
	umlal	r11, r12, r7, r9
	mov	r7, #0
	umlal	r12, r7, r8, r9
	adds	r10, r10, r10
	adcs	r11, r11, r11
	adcs	r12, r12, r12
	adcs	r7, r7, r7
	adc	r6, r6, #0
	adds	r2, r2, r10
	adcs	r3, r3, r11
	adcs	r4, r4, r12
	adcs	r5, r5, r7
	adc	r6, r6, #0
	stm	rp, {r1,r2,r3,r4,r5,r6}
	pop	{r4-r11}
	bx	r14

L(4):	push	{r4-r11, r14}
	ldm	up, {r9,r10,r11,r12}
	umull	r1, r2, r9, r9
	umull	r3, r4, r10, r10
	umull	r5, r6, r11, r11
	umull	r7, r8, r12, r12
	stm	rp, {r1,r2,r3,r4,r5,r6,r7}
	umull	r1, r2, r9, r10
	mov	r3, #0
	umlal	r2, r3, r9, r11
	mov	r4, #0
	umlal	r3, r4, r9, r12
	mov	r5, #0
	umlal	r3, r5, r10, r11
	umaal	r4, r5, r10, r12
	mov	r6, #0
	umlal	r5, r6, r11, r12
	adds	r1, r1, r1
	adcs	r2, r2, r2
	adcs	r3, r3, r3
	adcs	r4, r4, r4
	adcs	r5, r5, r5
	adcs	r6, r6, r6
	adc	r7, r8, #0
	add	rp, rp, #4
	ldm	rp, {r8,r9,r10,r11,r12,r14}
	adds	r1, r1, r8
	adcs	r2, r2, r9
	adcs	r3, r3, r10
	adcs	r4, r4, r11
	adcs	r5, r5, r12
	adcs	r6, r6, r14
	adc	r7, r7, #0
	stm	rp, {r1,r2,r3,r4,r5,r6,r7}
	pop	{r4-r11, pc}
EPILOGUE()
@


1.1.1.1
log
@initial import GMP 5.1.3 sources.  changes include:

fixes for:
- mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec
- mpz_powm_ui
- AMD family 11h
- mpz_powm_sec and mpn_powm_sec
- ASSERT() fixes
- gcd, gcdext, and invert function fixes
- some PPC division operations
@
text
@@


1.1.1.2
log
@initial import of GMP 6.1.2.  main changes from 5.1.3 below.

notes:
 - support for thumb-less ARM chips was in our port of 5.1.3, but a
   similar method has been provided upstream now
 - someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

  FEATURES
  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
    on Skylake Pentiums).
  * Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

  BUGS FIXED
  * The public function mpn_com is now correctly declared in gmp.h.
  * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
    some obsolete CPUs.
  * Various problems related to precision for mpf have been fixed.
  * Fixed ABI incompatible stack alignment in calls from assembly code.
  * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
  SPEEDUPS
  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    new ADX instructions.
  * Square root is now faster when the remainder is not needed. Also the speed
    to compute the k-th root improved, for small sizes.
  FEATURES
  * New C++ functions gcd and lcm for mpz_class.
  * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
  * New public mpq_cmp_z function, to efficiently compare rationals with
    integers.
  * Support for more 32-bit arm processors.
  * Support for AVX-less modern x86 CPUs. (Such support might be missing either
    because the CPU vendor chose to disable AVX, or because the running kernel
    lacks AVX context switch support.)
  * Support for NetBSD under Xen; we switch off AVX unconditionally under
    NetBSD since a bug in NetBSD makes AVX fail under Xen.
  MISC
  * Tuned values for FFT multiplications are provided for larger number on
    many platforms.

Changes between GMP version 5.1.* and 6.0.0
  BUGS FIXED
  * The function mpz_invert now considers any number invertible in Z/1Z.
  * The mpn multiply code now handles operands of more than 2^31 limbs
    correctly.  (Note however that the mpz code is limited to 2^32 bits on
    32-bit hosts and 2^37 bits on 64-bit hosts.)
  SPEEDUPS
  * Plain division of large operands is faster and more monotonous in operand
    size.
  * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
    assembly.
  * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
    and vastly expanded assembly support.  Speedup also for the older Core 2
    and Nehalem.
  * Faster mixed arithmetic between mpq_class and double.
  FEATURES
  * Support for new Intel and AMD CPUs.
  * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
    silent multiplication and squaring.
  * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
    side-channel silent division.
  * New public functions mpn_cnd_add_n and mpn_cnd_sub_n.  Side-channel silent
    conditional addition and subtraction.
  * New public function mpn_sec_powm, implementing side-channel silent modexp.
  * New public function mpn_sec_invert, implementing side-channel silent
    modular inversion.
  * Better support for applications which use the mpz_t type, but nevertheless
    need to call some of the lower-level mpn functions.  See the documentation
    for mpz_limbs_read and related functions.
@
text
@d3 1
a3 1
dnl  Contributed to the GNU project by Torbjörn Granlund.
d5 1
a5 1
dnl  Copyright 2012, 2013, 2015 Free Software Foundation, Inc.
d8 1
a8 1
dnl
d10 4
a13 14
dnl  it under the terms of either:
dnl
dnl    * the GNU Lesser General Public License as published by the Free
dnl      Software Foundation; either version 3 of the License, or (at your
dnl      option) any later version.
dnl
dnl  or
dnl
dnl    * the GNU General Public License as published by the Free Software
dnl      Foundation; either version 2 of the License, or (at your option) any
dnl      later version.
dnl
dnl  or both in parallel, as here.
dnl
d16 5
a20 6
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
dnl  for more details.
dnl
dnl  You should have received copies of the GNU General Public License and the
dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
dnl  see https://www.gnu.org/licenses/.
d41 1
a41 1
C                         cor3             cor2
a46 1
C  * Align more labels.
a48 2
C  * Avoid sub-with-lsl in outer loops.  We could keep n up-shifted, then
C    initialise loop counter i with a right shift.
d51 5
a55 6
C  * Optimise sqr_diag_addlsh1 loop.  The current code uses old-style carry
C    propagation.
C  * Stop loops earlier suppressing writes of upper-most rp[] values.
C  * The addmul_2 loops here runs well on all cores, but mul_2 runs poorly
C    particularly on Cortex-A8.

d87 1
a87 1
L(1m4):	push	{r4-r11, r14}
d101 1
a101 1
L(3m4):	push	{r4-r11, r14}
d115 1
a115 1
L(2m4):	push	{r4-r11, r14}
d128 1
a128 1
L(0m4):	push	{r4-r11, r14}
a162 14

	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]

	add	up, up, #4
	sub	n, n, #1
	add	rp, rp, #8
d166 1
a166 1
	subs	i, n, #6
d168 3
a170 3
	blt	L(cor2)
	ldm	up, {v0,v1,u1}
	add	up, up, #8
d173 2
a174 1
	ldr	r4, [rp, #-4]
d176 4
a179 5
	str	r4, [rp, #-4]
	ldr	r4, [rp, #0]

	ALIGN(16)
L(ua2):	ldr	r5, [rp, #4]
d181 2
a182 1
	ldr	u0, [up, #4]
d184 1
a184 2
	str	r4, [rp, #0]
	ldr	r4, [rp, #8]
d186 2
a187 1
	ldr	u1, [up, #8]
d189 1
a189 2
	str	r5, [rp, #4]
	ldr	r5, [rp, #12]
d191 2
a192 1
	ldr	u0, [up, #12]
d194 1
a194 2
	str	r4, [rp, #8]
	ldr	r4, [rp, #16]!
d196 2
a197 1
	ldr	u1, [up, #16]!
a198 1
	str	r5, [rp, #-4]
d200 2
a201 2
	bhs	L(ua2)

d203 9
a211 5
	umaal	cya, cyb, u1, v1
	str	r4, [rp, #0]
	str	cya, [rp, #4]
	str	cyb, [rp, #8]
L(am2_0m4):
d213 1
a213 3
	sub	up, up, n, lsl #2
	add	rp, rp, #8

d216 2
a217 1
	ldm	up, {v0,v1,u1}
d220 3
a222 1
	ldr	r4, [rp, #4]
d224 2
a225 2
	str	r4, [rp, #4]
	ldr	r4, [rp, #8]
d227 1
a227 3

	ALIGN(16)
L(ua0):	ldr	r5, [rp, #4]
d229 2
a230 1
	ldr	u0, [up, #4]
d232 1
a232 2
	str	r4, [rp, #0]
	ldr	r4, [rp, #8]
d234 2
a235 1
	ldr	u1, [up, #8]
d237 1
a237 2
	str	r5, [rp, #4]
L(lo0):	ldr	r5, [rp, #12]
d239 2
a240 1
	ldr	u0, [up, #12]
d242 1
a242 2
	str	r4, [rp, #8]
	ldr	r4, [rp, #16]!
d244 2
a245 1
	ldr	u1, [up, #16]!
a246 1
	str	r5, [rp, #-4]
d248 2
a249 2
	bhs	L(ua0)

d251 9
a259 5
	umaal	cya, cyb, u1, v1
	str	r4, [rp, #0]
	str	cya, [rp, #4]
	str	cyb, [rp, #8]
L(am2_2m4):
d261 2
a262 2
	sub	up, up, n, lsl #2
	add	rp, rp, #16
d267 1
a267 1
	sub	i, n, #5
d269 2
a270 1
	ldm	up, {v0,v1,u0}
d273 3
a275 1
	ldr	r5, [rp, #0]
d277 2
a278 3
	str	r5, [rp, #0]
	ldr	r5, [rp, #4]
	add	up, up, #4
d280 1
a280 3

	ALIGN(16)
L(ua1):	ldr	r5, [rp, #4]
d282 2
a283 1
	ldr	u0, [up, #4]
d285 1
a285 2
	str	r4, [rp, #0]
L(lo1):	ldr	r4, [rp, #8]
d287 2
a288 1
	ldr	u1, [up, #8]
d290 1
a290 2
	str	r5, [rp, #4]
	ldr	r5, [rp, #12]
d292 2
a293 1
	ldr	u0, [up, #12]
d295 1
a295 2
	str	r4, [rp, #8]
	ldr	r4, [rp, #16]!
d297 2
a298 1
	ldr	u1, [up, #16]!
a299 1
	str	r5, [rp, #-4]
d301 2
a302 2
	bhs	L(ua1)

d304 9
a312 5
	umaal	cya, cyb, u1, v1
	str	r4, [rp, #0]
	str	cya, [rp, #4]
	str	cyb, [rp, #8]
L(am2_3m4):
d314 3
a316 5
	sub	up, up, n, lsl #2
	add	rp, rp, #4

	subs	i, n, #3
	beq	L(cor3)
d318 1
a318 1
	ldm	up, {v0,v1,u0}
d321 5
d327 2
a328 8
	sub	up, up, #4
	umaal	r5, cya, v1, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #12]
	b	L(lo3)

	ALIGN(16)
L(ua3):	ldr	r5, [rp, #4]
d330 2
a331 1
	ldr	u0, [up, #4]
d333 1
a333 2
	str	r4, [rp, #0]
	ldr	r4, [rp, #8]
d335 2
a336 1
	ldr	u1, [up, #8]
d338 1
a338 2
	str	r5, [rp, #4]
	ldr	r5, [rp, #12]
d340 2
a341 1
	ldr	u0, [up, #12]
d343 1
a343 2
	str	r4, [rp, #8]
L(lo3):	ldr	r4, [rp, #16]!
d345 2
a346 1
	ldr	u1, [up, #16]!
a347 1
	str	r5, [rp, #-4]
d349 3
a351 2
	bhs	L(ua3)

d353 9
a361 5
	umaal	cya, cyb, u1, v1
	str	r4, [rp, #0]
	str	cya, [rp, #4]
	str	cyb, [rp, #8]
L(am2_1m4):
d363 2
a364 2
	sub	up, up, n, lsl #2
	add	rp, rp, #12
d367 2
a368 4

L(cor3):ldm	up, {v0,v1,u0}
	ldr	r5, [rp, #8]
	mov	cya, #0
d370 1
a370 18
	umaal	r5, cya, v1, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #12]
	ldr	r4, [rp, #16]
	umaal	r5, cya, u0, v0
	ldr	u1, [up, #12]
	umaal	r4, cyb, u0, v1
	str	r5, [rp, #12]
	umaal	r4, cya, u1, v0
	umaal	cya, cyb, u1, v1
	str	r4, [rp, #16]
	str	cya, [rp, #20]
	str	cyb, [rp, #24]
	add	up, up, #16
	mov	cya, cyb
	adds	rp, rp, #36		C clear cy
	mov	cyb, #0
	umaal	cya, cyb, u1, u0
d373 2
a374 4
L(cor2):
	ldm	up!, {v0,v1,u0}
	mov	r4, cya
	mov	r5, cyb
d376 1
a377 1
	mov	cyb, #0
d379 1
a379 1
	strd	r4, r5, [rp, #-4]
d381 1
a381 1
	add	rp, rp, #16
d399 1
a399 2
	mov	r10, #0
C	cmn	r0, #0			C clear cy (already clear)
d412 2
a413 1
	adc	w2, r10, r10
d423 1
a423 1
	pop	{r4-r11, pc}
d495 1
a496 1
	adc	r7, r8, #0
@


1.1.1.1.8.1
log
@file sqr_basecase.asm was added on branch tls-maxphys on 2014-08-19 23:59:49 +0000
@
text
@d1 507
@


1.1.1.1.8.2
log
@Rebase to HEAD as of a few days ago.
@
text
@a0 507
dnl  ARM v6 mpn_sqr_basecase.

dnl  Contributed to the GNU project by Torbjorn Granlund.

dnl  Copyright 2012 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C Code structure:
C
C
C        m_2(0m4)        m_2(2m4)        m_2(1m4)        m_2(3m4)
C           |               |               |               |
C           |               |               |               |
C           |               |               |               |
C          \|/             \|/             \|/             \|/
C              ____________                   ____________
C             /            \                 /            \
C            \|/            \               \|/            \
C         am_2(3m4)       am_2(1m4)       am_2(0m4)       am_2(2m4)
C            \            /|\                \            /|\
C             \____________/                  \____________/
C                       \                        /
C                        \                      /
C                         \                    /
C                       tail(0m2)          tail(1m2)
C                            \              /
C                             \            /
C                            sqr_diag_addlsh1

C TODO
C  * Further tweak counter and updates in outer loops.  (This could save
C    perhaps 5n cycles).
C  * Try to use fewer register.  Perhaps coalesce r9 branch target and n_saved.
C    (This could save 2-3 cycles for n > 4.)
C  * Optimise sqr_diag_addlsh1 loop.  (This could save O(n) cycles.)
C  * Implement larger final corners (xit/tix).  Also stop loops earlier
C    suppressing writes of upper-most rp[] values.  (This could save 10-20
C    cycles for n > 4.)
C  * Is the branch really faster than discrete branches?

define(`rp',      r0)
define(`up',      r1)
define(`n',       r2)

define(`v0',      r3)
define(`v1',      r6)
define(`i',       r8)
define(`n_saved', r14)
define(`cya',     r11)
define(`cyb',     r12)
define(`u0',      r7)
define(`u1',      r9)

ASM_START()
PROLOGUE(mpn_sqr_basecase)
	and	r12, n, #3
	cmp	n, #4
	addgt	r12, r12, #4
	add	pc, pc, r12, lsl #2
	nop
	b	L(4)
	b	L(1)
	b	L(2)
	b	L(3)
	b	L(0m4)
	b	L(1m4)
	b	L(2m4)
	b	L(3m4)


L(1m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_2m4)-.-8
	ldm	up, {v0,v1,u0}
	sub	up, up, #4
	mov	cyb, #0
	mov	r5, #0
	umull	r4, cya, v1, v0
	str	r4, [rp], #-12
	mov	r4, #0
	b	L(ko0)

L(3m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_0m4)-.-8
	ldm	up, {v0,v1,u0}
	add	up, up, #4
	mov	cyb, #0
	mov	r5, #0
	umull	r4, cya, v1, v0
	str	r4, [rp], #-4
	mov	r4, #0
	b	L(ko2)

L(2m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_3m4)-.-8
	ldm	up, {v0,v1,u1}
	mov	cyb, #0
	mov	r4, #0
	umull	r5, cya, v1, v0
	str	r5, [rp], #-8
	mov	r5, #0
	b	L(ko1)

L(0m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_1m4)-.-8
	ldm	up, {v0,v1,u1}
	mov	cyb, #0
	mov	r4, #0
	add	up, up, #8
	umull	r5, cya, v1, v0
	str	r5, [rp, #0]
	mov	r5, #0

L(top):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	mov	r4, #0
	umaal	r5, cyb, u1, v1
L(ko2):	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	mov	r5, #0
	umaal	r4, cyb, u0, v1
L(ko1):	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	mov	r4, #0
	umaal	r5, cyb, u1, v1
L(ko0):	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	mov	r5, #0
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(top)
	bx	r10

L(evnloop):
	subs	i, n, #4
	sub	n, n, #2
	blt	L(tix)
	ldm	up, {v0,v1,u0}
	add	up, up, #4
	mov	cya, #0
	mov	cyb, #0
	ldm	rp, {r4,r5}
	sub	rp, rp, #4
	umaal	r4, cya, v1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	b	L(lo2)
L(ua2):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
L(lo2):	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua2)
L(am2_0m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	sub	i, n, #4
	sub	n, n, #2
	ldm	up, {v0,v1,u0}
	sub	up, up, #4
	mov	cya, #0
	mov	cyb, #0
	ldr	r4, [rp, #24]
	ldr	r5, [rp, #28]
	add	rp, rp, #12
	umaal	r4, cya, v1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	b	L(lo0)
L(ua0):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
L(lo0):	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua0)
L(am2_2m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	add	rp, rp, #24
	b	L(evnloop)


L(oddloop):
	subs	i, n, #4
	sub	n, n, #2
	blt	L(xit)
	ldm	up, {v0,v1,u1}
	mov	cya, #0
	mov	cyb, #0
	sub	rp, rp, #8
	ldr	r5, [rp, #8]
	ldr	r4, [rp, #12]
	umaal	r5, cya, v1, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	b	L(lo1)
L(ua1):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
L(lo1):	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua1)
L(am2_3m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	add	rp, rp, #24
	subs	i, n, #4
	sub	n, n, #2
	ldm	up, {v0,v1,u1}
	mov	cya, #0
	mov	cyb, #0
	ldr	r5, [rp, #0]
	ldr	r4, [rp, #4]
	add	up, up, #8
	umaal	r5, cya, v1, v0
	str	r5, [rp, #0]
	ldr	r5, [rp, #8]
	bls	L(e3)
L(ua3):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua3)
L(e3):
L(am2_1m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	add	rp, rp, #24
	b	L(oddloop)

L(xit):	ldm	up!, {v0,u0}
	ldr	cya, [rp], #12
	mov	cyb, #0
	umaal	cya, cyb, u0, v0
	b	L(sqr_diag_addlsh1)

L(tix):	ldm	up!, {v0,v1,u0}
	ldm	rp, {r4,r5}
	mov	cya, #0
	mov	cyb, #0
	umaal	r4, cya, v1, v0
	umaal	r5, cya, u0, v0
	stm	rp, {r4,r5}
	umaal	cya, cyb, u0, v1
	add	rp, rp, #20
C	b	L(sqr_diag_addlsh1)


define(`w0',  r6)
define(`w1',  r7)
define(`w2',  r8)
define(`rbx', r9)

L(sqr_diag_addlsh1):
	str	cya, [rp, #-12]
	str	cyb, [rp, #-8]
	sub	n, n_saved, #1
	sub	up, up, n_saved, lsl #2
	sub	rp, rp, n_saved, lsl #3
	ldr	r3, [up], #4
	umull	w1, r5, r3, r3
	mov	w2, #0
C	cmn	r0, #0			C clear cy (already clear by luck)
	b	L(lm)

L(tsd):	adds	w0, w0, rbx
	adcs	w1, w1, r4
	str	w0, [rp, #0]
L(lm):	ldr	w0, [rp, #4]
	str	w1, [rp, #4]
	ldr	w1, [rp, #8]!
	add	rbx, r5, w2
	adcs	w0, w0, w0
	ldr	r3, [up], #4
	adcs	w1, w1, w1
	mov	w2, #0
	adc	w2, w2, w2
	umull	r4, r5, r3, r3
	subs	n, n, #1
	bne	L(tsd)

	adds	w0, w0, rbx
	adcs	w1, w1, r4
	adc	w2, r5, w2
	stm	rp, {w0,w1,w2}

	pop	{r4-r10,r11,pc}


C Straight line code for n <= 4

L(1):	ldr	r3, [up, #0]
	umull	r1, r2, r3, r3
	stm	rp, {r1,r2}
	bx	r14

L(2):	push	{r4-r5}
	ldm	up, {r5,r12}
	umull	r1, r2, r5, r5
	umull	r3, r4, r12, r12
	umull	r5, r12, r5, r12
	adds	r5, r5, r5
	adcs	r12, r12, r12
	adc	r4, r4, #0
	adds	r2, r2, r5
	adcs	r3, r3, r12
	adc	r4, r4, #0
	stm	rp, {r1,r2,r3,r4}
	pop	{r4-r5}
	bx	r14

L(3):	push	{r4-r11}
	ldm	up, {r7,r8,r9}
	umull	r1, r2, r7, r7
	umull	r3, r4, r8, r8
	umull	r5, r6, r9, r9
	umull	r10, r11, r7, r8
	mov	r12, #0
	umlal	r11, r12, r7, r9
	mov	r7, #0
	umlal	r12, r7, r8, r9
	adds	r10, r10, r10
	adcs	r11, r11, r11
	adcs	r12, r12, r12
	adcs	r7, r7, r7
	adc	r6, r6, #0
	adds	r2, r2, r10
	adcs	r3, r3, r11
	adcs	r4, r4, r12
	adcs	r5, r5, r7
	adc	r6, r6, #0
	stm	rp, {r1,r2,r3,r4,r5,r6}
	pop	{r4-r11}
	bx	r14

L(4):	push	{r4-r11, r14}
	ldm	up, {r9,r10,r11,r12}
	umull	r1, r2, r9, r9
	umull	r3, r4, r10, r10
	umull	r5, r6, r11, r11
	umull	r7, r8, r12, r12
	stm	rp, {r1,r2,r3,r4,r5,r6,r7}
	umull	r1, r2, r9, r10
	mov	r3, #0
	umlal	r2, r3, r9, r11
	mov	r4, #0
	umlal	r3, r4, r9, r12
	mov	r5, #0
	umlal	r3, r5, r10, r11
	umaal	r4, r5, r10, r12
	mov	r6, #0
	umlal	r5, r6, r11, r12
	adds	r1, r1, r1
	adcs	r2, r2, r2
	adcs	r3, r3, r3
	adcs	r4, r4, r4
	adcs	r5, r5, r5
	adcs	r6, r6, r6
	adc	r7, r8, #0
	add	rp, rp, #4
	ldm	rp, {r8,r9,r10,r11,r12,r14}
	adds	r1, r1, r8
	adcs	r2, r2, r9
	adcs	r3, r3, r10
	adcs	r4, r4, r11
	adcs	r5, r5, r12
	adcs	r6, r6, r14
	adc	r7, r7, #0
	stm	rp, {r1,r2,r3,r4,r5,r6,r7}
	pop	{r4-r11, pc}
EPILOGUE()
@


1.1.1.1.4.1
log
@file sqr_basecase.asm was added on branch yamt-pagecache on 2014-05-22 14:09:00 +0000
@
text
@d1 507
@


1.1.1.1.4.2
log
@sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")
@
text
@a0 507
dnl  ARM v6 mpn_sqr_basecase.

dnl  Contributed to the GNU project by Torbjorn Granlund.

dnl  Copyright 2012 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C Code structure:
C
C
C        m_2(0m4)        m_2(2m4)        m_2(1m4)        m_2(3m4)
C           |               |               |               |
C           |               |               |               |
C           |               |               |               |
C          \|/             \|/             \|/             \|/
C              ____________                   ____________
C             /            \                 /            \
C            \|/            \               \|/            \
C         am_2(3m4)       am_2(1m4)       am_2(0m4)       am_2(2m4)
C            \            /|\                \            /|\
C             \____________/                  \____________/
C                       \                        /
C                        \                      /
C                         \                    /
C                       tail(0m2)          tail(1m2)
C                            \              /
C                             \            /
C                            sqr_diag_addlsh1

C TODO
C  * Further tweak counter and updates in outer loops.  (This could save
C    perhaps 5n cycles).
C  * Try to use fewer register.  Perhaps coalesce r9 branch target and n_saved.
C    (This could save 2-3 cycles for n > 4.)
C  * Optimise sqr_diag_addlsh1 loop.  (This could save O(n) cycles.)
C  * Implement larger final corners (xit/tix).  Also stop loops earlier
C    suppressing writes of upper-most rp[] values.  (This could save 10-20
C    cycles for n > 4.)
C  * Is the branch really faster than discrete branches?

define(`rp',      r0)
define(`up',      r1)
define(`n',       r2)

define(`v0',      r3)
define(`v1',      r6)
define(`i',       r8)
define(`n_saved', r14)
define(`cya',     r11)
define(`cyb',     r12)
define(`u0',      r7)
define(`u1',      r9)

ASM_START()
PROLOGUE(mpn_sqr_basecase)
	and	r12, n, #3
	cmp	n, #4
	addgt	r12, r12, #4
	add	pc, pc, r12, lsl #2
	nop
	b	L(4)
	b	L(1)
	b	L(2)
	b	L(3)
	b	L(0m4)
	b	L(1m4)
	b	L(2m4)
	b	L(3m4)


L(1m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_2m4)-.-8
	ldm	up, {v0,v1,u0}
	sub	up, up, #4
	mov	cyb, #0
	mov	r5, #0
	umull	r4, cya, v1, v0
	str	r4, [rp], #-12
	mov	r4, #0
	b	L(ko0)

L(3m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_0m4)-.-8
	ldm	up, {v0,v1,u0}
	add	up, up, #4
	mov	cyb, #0
	mov	r5, #0
	umull	r4, cya, v1, v0
	str	r4, [rp], #-4
	mov	r4, #0
	b	L(ko2)

L(2m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_3m4)-.-8
	ldm	up, {v0,v1,u1}
	mov	cyb, #0
	mov	r4, #0
	umull	r5, cya, v1, v0
	str	r5, [rp], #-8
	mov	r5, #0
	b	L(ko1)

L(0m4):	push	{r4-r10,r11,r14}
	mov	n_saved, n
	sub	i, n, #4
	sub	n, n, #2
	add	r10, pc, #L(am2_1m4)-.-8
	ldm	up, {v0,v1,u1}
	mov	cyb, #0
	mov	r4, #0
	add	up, up, #8
	umull	r5, cya, v1, v0
	str	r5, [rp, #0]
	mov	r5, #0

L(top):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	mov	r4, #0
	umaal	r5, cyb, u1, v1
L(ko2):	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	mov	r5, #0
	umaal	r4, cyb, u0, v1
L(ko1):	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	mov	r4, #0
	umaal	r5, cyb, u1, v1
L(ko0):	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	mov	r5, #0
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(top)
	bx	r10

L(evnloop):
	subs	i, n, #4
	sub	n, n, #2
	blt	L(tix)
	ldm	up, {v0,v1,u0}
	add	up, up, #4
	mov	cya, #0
	mov	cyb, #0
	ldm	rp, {r4,r5}
	sub	rp, rp, #4
	umaal	r4, cya, v1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	b	L(lo2)
L(ua2):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
L(lo2):	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua2)
L(am2_0m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	sub	i, n, #4
	sub	n, n, #2
	ldm	up, {v0,v1,u0}
	sub	up, up, #4
	mov	cya, #0
	mov	cyb, #0
	ldr	r4, [rp, #24]
	ldr	r5, [rp, #28]
	add	rp, rp, #12
	umaal	r4, cya, v1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	b	L(lo0)
L(ua0):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
L(lo0):	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua0)
L(am2_2m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	add	rp, rp, #24
	b	L(evnloop)


L(oddloop):
	subs	i, n, #4
	sub	n, n, #2
	blt	L(xit)
	ldm	up, {v0,v1,u1}
	mov	cya, #0
	mov	cyb, #0
	sub	rp, rp, #8
	ldr	r5, [rp, #8]
	ldr	r4, [rp, #12]
	umaal	r5, cya, v1, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	b	L(lo1)
L(ua1):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
L(lo1):	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua1)
L(am2_3m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	add	rp, rp, #24
	subs	i, n, #4
	sub	n, n, #2
	ldm	up, {v0,v1,u1}
	mov	cya, #0
	mov	cyb, #0
	ldr	r5, [rp, #0]
	ldr	r4, [rp, #4]
	add	up, up, #8
	umaal	r5, cya, v1, v0
	str	r5, [rp, #0]
	ldr	r5, [rp, #8]
	bls	L(e3)
L(ua3):	ldr	u0, [up, #4]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #4]
	ldr	r4, [rp, #12]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #8]
	umaal	r5, cya, u0, v0
	str	r5, [rp, #8]
	ldr	r5, [rp, #16]
	umaal	r4, cyb, u0, v1
	ldr	u0, [up, #12]
	umaal	r4, cya, u1, v0
	str	r4, [rp, #12]
	ldr	r4, [rp, #20]
	umaal	r5, cyb, u1, v1
	ldr	u1, [up, #16]!
	umaal	r5, cya, u0, v0
	str	r5, [rp, #16]!
	ldr	r5, [rp, #8]
	umaal	r4, cyb, u0, v1
	subs	i, i, #4
	bhi	L(ua3)
L(e3):
L(am2_1m4):
	umaal	r4, cya, u1, v0
	ldr	u0, [up, #4]
	umaal	r5, cyb, u1, v1
	str	r4, [rp, #4]
	umaal	r5, cya, u0, v0
	umaal	cya, cyb, u0, v1
	str	r5, [rp, #8]
	str	cya, [rp, #12]
	str	cyb, [rp, #16]
	sub	up, up, n, lsl #2
	sub	rp, rp, n, lsl #2
	add	up, up, #8
	add	rp, rp, #24
	b	L(oddloop)

L(xit):	ldm	up!, {v0,u0}
	ldr	cya, [rp], #12
	mov	cyb, #0
	umaal	cya, cyb, u0, v0
	b	L(sqr_diag_addlsh1)

L(tix):	ldm	up!, {v0,v1,u0}
	ldm	rp, {r4,r5}
	mov	cya, #0
	mov	cyb, #0
	umaal	r4, cya, v1, v0
	umaal	r5, cya, u0, v0
	stm	rp, {r4,r5}
	umaal	cya, cyb, u0, v1
	add	rp, rp, #20
C	b	L(sqr_diag_addlsh1)


define(`w0',  r6)
define(`w1',  r7)
define(`w2',  r8)
define(`rbx', r9)

L(sqr_diag_addlsh1):
	str	cya, [rp, #-12]
	str	cyb, [rp, #-8]
	sub	n, n_saved, #1
	sub	up, up, n_saved, lsl #2
	sub	rp, rp, n_saved, lsl #3
	ldr	r3, [up], #4
	umull	w1, r5, r3, r3
	mov	w2, #0
C	cmn	r0, #0			C clear cy (already clear by luck)
	b	L(lm)

L(tsd):	adds	w0, w0, rbx
	adcs	w1, w1, r4
	str	w0, [rp, #0]
L(lm):	ldr	w0, [rp, #4]
	str	w1, [rp, #4]
	ldr	w1, [rp, #8]!
	add	rbx, r5, w2
	adcs	w0, w0, w0
	ldr	r3, [up], #4
	adcs	w1, w1, w1
	mov	w2, #0
	adc	w2, w2, w2
	umull	r4, r5, r3, r3
	subs	n, n, #1
	bne	L(tsd)

	adds	w0, w0, rbx
	adcs	w1, w1, r4
	adc	w2, r5, w2
	stm	rp, {w0,w1,w2}

	pop	{r4-r10,r11,pc}


C Straight line code for n <= 4

L(1):	ldr	r3, [up, #0]
	umull	r1, r2, r3, r3
	stm	rp, {r1,r2}
	bx	r14

L(2):	push	{r4-r5}
	ldm	up, {r5,r12}
	umull	r1, r2, r5, r5
	umull	r3, r4, r12, r12
	umull	r5, r12, r5, r12
	adds	r5, r5, r5
	adcs	r12, r12, r12
	adc	r4, r4, #0
	adds	r2, r2, r5
	adcs	r3, r3, r12
	adc	r4, r4, #0
	stm	rp, {r1,r2,r3,r4}
	pop	{r4-r5}
	bx	r14

L(3):	push	{r4-r11}
	ldm	up, {r7,r8,r9}
	umull	r1, r2, r7, r7
	umull	r3, r4, r8, r8
	umull	r5, r6, r9, r9
	umull	r10, r11, r7, r8
	mov	r12, #0
	umlal	r11, r12, r7, r9
	mov	r7, #0
	umlal	r12, r7, r8, r9
	adds	r10, r10, r10
	adcs	r11, r11, r11
	adcs	r12, r12, r12
	adcs	r7, r7, r7
	adc	r6, r6, #0
	adds	r2, r2, r10
	adcs	r3, r3, r11
	adcs	r4, r4, r12
	adcs	r5, r5, r7
	adc	r6, r6, #0
	stm	rp, {r1,r2,r3,r4,r5,r6}
	pop	{r4-r11}
	bx	r14

L(4):	push	{r4-r11, r14}
	ldm	up, {r9,r10,r11,r12}
	umull	r1, r2, r9, r9
	umull	r3, r4, r10, r10
	umull	r5, r6, r11, r11
	umull	r7, r8, r12, r12
	stm	rp, {r1,r2,r3,r4,r5,r6,r7}
	umull	r1, r2, r9, r10
	mov	r3, #0
	umlal	r2, r3, r9, r11
	mov	r4, #0
	umlal	r3, r4, r9, r12
	mov	r5, #0
	umlal	r3, r5, r10, r11
	umaal	r4, r5, r10, r12
	mov	r6, #0
	umlal	r5, r6, r11, r12
	adds	r1, r1, r1
	adcs	r2, r2, r2
	adcs	r3, r3, r3
	adcs	r4, r4, r4
	adcs	r5, r5, r5
	adcs	r6, r6, r6
	adc	r7, r8, #0
	add	rp, rp, #4
	ldm	rp, {r8,r9,r10,r11,r12,r14}
	adds	r1, r1, r8
	adcs	r2, r2, r9
	adcs	r3, r3, r10
	adcs	r4, r4, r11
	adcs	r5, r5, r12
	adcs	r6, r6, r14
	adc	r7, r7, #0
	stm	rp, {r1,r2,r3,r4,r5,r6,r7}
	pop	{r4-r11, pc}
EPILOGUE()
@