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access;
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desc
@@


1.1
log
@Initial revision
@
text
@dnl Alpha mpn_mod_1s_4p

dnl  Contributed to the GNU project by Torbjorn Granlund.

dnl  Copyright 2009, 2010 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C TODO:
C  * Optimise.  2.75 c/l should be possible.
C  * Write a proper mpn_mod_1s_4p_cps.  The code below was compiler generated.
C  * Optimise feed-in code, starting the sw pipeline in switch code.
C  * Shorten software pipeline.  The mul instructions are scheduled too far
C    from their users.  Fixing this will allow us to use fewer registers.
C  * If we cannot reduce register usage, write perhaps small-n basecase.
C  * Does this work for PIC?

C      cycles/limb
C EV4:     ?
C EV5:    23
C EV6:     3

define(`ap',     `r16')
define(`n',      `r17')
define(`pl',     `r24')
define(`ph',     `r25')
define(`rl',     `r6')
define(`rh',     `r7')
define(`B1modb', `r1')
define(`B2modb', `r2')
define(`B3modb', `r3')
define(`B4modb', `r4')
define(`B5modb', `r5')

ASM_START()
PROLOGUE(mpn_mod_1s_4p)
	lda	r30, -64(r30)
	stq	r9, 8(r30)
	ldq	B1modb, 16(r19)
	stq	r10, 16(r30)
	ldq	B2modb, 24(r19)
	stq	r11, 24(r30)
	ldq	B3modb, 32(r19)
	stq	r12, 32(r30)
	ldq	B4modb, 40(r19)
	stq	r13, 40(r30)
	ldq	B5modb, 48(r19)
	s8addq	n, ap, ap		C point ap at vector end

	and	n, 3, r0
	lda	n, -4(n)
	beq	r0, L(b0)
	lda	r6, -2(r0)
	blt	r6, L(b1)
	beq	r6, L(b2)

L(b3):	ldq	r21, -16(ap)
	ldq	r22, -8(ap)
	ldq	r20, -24(ap)
	mulq	r21, B1modb, r8
	umulh	r21, B1modb, r12
	mulq	r22, B2modb, r9
	umulh	r22, B2modb, r13
	addq	r8, r20, pl
	cmpult	pl, r8, r0
	addq	r0, r12, ph
	addq	r9, pl, rl
	cmpult	rl, r9, r0
	addq	r13, ph, ph
	addq	r0, ph, rh
	lda	ap, -56(ap)
	br	L(com)

L(b0):	ldq	r21, -24(ap)
	ldq	r22, -16(ap)
	ldq	r23, -8(ap)
	ldq	r20, -32(ap)
	mulq	r21, B1modb, r8
	umulh	r21, B1modb, r12
	mulq	r22, B2modb, r9
	umulh	r22, B2modb, r13
	mulq	r23, B3modb, r10
	umulh	r23, B3modb, r27
	addq	r8, r20, pl
	cmpult	pl, r8, r0
	addq	r0, r12, ph
	addq	r9, pl, pl
	cmpult	pl, r9, r0
	addq	r13, ph, ph
	addq	r0, ph, ph
	addq	r10, pl, rl
	cmpult	rl, r10, r0
	addq	r27, ph, ph
	addq	r0, ph, rh
	lda	ap, -64(ap)
	br	L(com)

L(b1):	bis	r31, r31, rh
	ldq	rl, -8(ap)
	lda	ap, -40(ap)
	br	L(com)

L(b2):	ldq	rh, -8(ap)
	ldq	rl, -16(ap)
	lda	ap, -48(ap)

L(com):	ble	n, L(ed3)
	ldq	r21, 8(ap)
	ldq	r22, 16(ap)
	ldq	r23, 24(ap)
	ldq	r20, 0(ap)
	lda	n, -4(n)
	lda	ap, -32(ap)
	mulq	r21, B1modb, r8
	umulh	r21, B1modb, r12
	mulq	r22, B2modb, r9
	umulh	r22, B2modb, r13
	mulq	r23, B3modb, r10
	umulh	r23, B3modb, r27
	mulq	rl, B4modb, r11
	umulh	rl, B4modb, r28
	ble	n, L(ed2)

	ALIGN(16)
L(top):	ldq	r21, 8(ap)
	mulq	rh, B5modb, rl
	addq	r8, r20, pl
	ldq	r22, 16(ap)
	cmpult	pl, r8, r0
	umulh	rh, B5modb, rh
	ldq	r23, 24(ap)
	addq	r0, r12, ph
	addq	r9, pl, pl
	mulq	r21, B1modb, r8
	cmpult	pl, r9, r0
	addq	r13, ph, ph
	umulh	r21, B1modb, r12
	lda	ap, -32(ap)
	addq	r0, ph, ph
	addq	r10, pl, pl
	mulq	r22, B2modb, r9
	cmpult	pl, r10, r0
	addq	r27, ph, ph
	addq	r11, pl, pl
	umulh	r22, B2modb, r13
	addq	r0, ph, ph
	cmpult	pl, r11, r0
	addq	r28, ph, ph
	mulq	r23, B3modb, r10
	ldq	r20, 32(ap)
	addq	pl, rl, rl
	umulh	r23, B3modb, r27
	addq	r0, ph, ph
	cmpult	rl, pl, r0
	mulq	rl, B4modb, r11
	addq	ph, rh, rh
	umulh	rl, B4modb, r28
	addq	r0, rh, rh
	lda	n, -4(n)
	bgt	n, L(top)

L(ed2):	mulq	rh, B5modb, rl
	addq	r8, r20, pl
	umulh	rh, B5modb, rh
	cmpult	pl, r8, r0
	addq	r0, r12, ph
	addq	r9, pl, pl
	cmpult	pl, r9, r0
	addq	r13, ph, ph
	addq	r0, ph, ph
	addq	r10, pl, pl
	cmpult	pl, r10, r0
	addq	r27, ph, ph
	addq	r11, pl, pl
	addq	r0, ph, ph
	cmpult	pl, r11, r0
	addq	r28, ph, ph
	addq	pl, rl, rl
	addq	r0, ph, ph
	cmpult	rl, pl, r0
	addq	ph, rh, rh
	addq	r0, rh, rh

L(ed3):	mulq	rh, B1modb, r8
	umulh	rh, B1modb, rh
	addq	r8, rl, rl
	cmpult	rl, r8, r0
	addq	r0, rh, rh

	ldq	r24, 8(r19)		C cnt
	sll	rh, r24, rh
	subq	r31, r24, r25
	srl	rl, r25, r2
	sll	rl, r24, rl
	or	r2, rh, rh

	ldq	r23, 0(r19)		C bi
	mulq	rh, r23, r8
	umulh	rh, r23, r9
	addq	rh, 1, r7
	addq	r8, rl, r8		C ql
	cmpult	r8, rl, r0
	addq	r9, r7, r9
	addq	r0, r9, r9		C qh
	mulq	r9, r18, r21		C qh * b
	subq	rl, r21, rl
	cmpult	r8, rl, r0		C rl > ql
	negq	r0, r0
	and	r0, r18, r0
	addq	rl, r0, rl
	cmpule	r18, rl, r0		C rl >= b
	negq	r0, r0
	and	r0, r18, r0
	subq	rl, r0, rl

	srl	rl, r24, r0

	ldq	r9, 8(r30)
	ldq	r10, 16(r30)
	ldq	r11, 24(r30)
	ldq	r12, 32(r30)
	ldq	r13, 40(r30)
	lda	r30, 64(r30)
	ret	r31, (r26), 1
EPILOGUE()

PROLOGUE(mpn_mod_1s_4p_cps,gp)
	lda	r30, -32(r30)
	stq	r26, 0(r30)
	stq	r9, 8(r30)
	stq	r10, 16(r30)
	stq	r11, 24(r30)
	mov	r16, r11
	LEA(	r4, __clz_tab)
	lda	r10, 65(r31)
	cmpbge	r31, r17, r1
	srl	r1, 1, r1
	xor	r1, 127, r1
	addq	r1, r4, r1
	ldq_u	r2, 0(r1)
	extbl	r2, r1, r2
	s8subq	r2, 7, r2
	srl	r17, r2, r3
	subq	r10, r2, r10
	addq	r3, r4, r3
	ldq_u	r1, 0(r3)
	extbl	r1, r3, r1
	subq	r10, r1, r10
	sll	r17, r10, r9
	mov	r9, r16
	jsr	r26, mpn_invert_limb
	ldah	r29, 0(r26)
	subq	r31, r10, r2
	lda	r1, 1(r31)
	sll	r1, r10, r1
	subq	r31, r9, r3
	srl	r0, r2, r2
	ldq	r26, 0(r30)
	bis	r2, r1, r2
	lda	r29, 0(r29)
	stq	r0, 0(r11)
	stq	r10, 8(r11)
	mulq	r2, r3, r2
	srl	r2, r10, r3
	umulh	r2, r0, r1
	stq	r3, 16(r11)
	mulq	r2, r0, r3
	ornot	r31, r1, r1
	subq	r1, r2, r1
	mulq	r1, r9, r1
	addq	r1, r9, r2
	cmpule	r1, r3, r3
	cmoveq	r3, r2, r1
	srl	r1, r10, r3
	umulh	r1, r0, r2
	stq	r3, 24(r11)
	mulq	r1, r0, r3
	ornot	r31, r2, r2
	subq	r2, r1, r2
	mulq	r2, r9, r2
	addq	r2, r9, r1
	cmpule	r2, r3, r3
	cmoveq	r3, r1, r2
	srl	r2, r10, r1
	umulh	r2, r0, r3
	stq	r1, 32(r11)
	mulq	r2, r0, r1
	ornot	r31, r3, r3
	subq	r3, r2, r3
	mulq	r3, r9, r3
	addq	r3, r9, r2
	cmpule	r3, r1, r1
	cmoveq	r1, r2, r3
	srl	r3, r10, r2
	umulh	r3, r0, r1
	stq	r2, 40(r11)
	mulq	r3, r0, r0
	ornot	r31, r1, r1
	subq	r1, r3, r1
	mulq	r1, r9, r1
	addq	r1, r9, r9
	cmpule	r1, r0, r0
	cmoveq	r0, r9, r1
	ldq	r9, 8(r30)
	srl	r1, r10, r1
	ldq	r10, 16(r30)
	stq	r1, 48(r11)
	ldq	r11, 24(r30)
	lda	r30, 32(r30)
	ret	r31, (r26), 1
EPILOGUE()
@


1.1.1.1
log
@initial import GMP 5.1.3 sources.  changes include:

fixes for:
- mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec
- mpz_powm_ui
- AMD family 11h
- mpz_powm_sec and mpn_powm_sec
- ASSERT() fixes
- gcd, gcdext, and invert function fixes
- some PPC division operations
@
text
@@


1.1.1.2
log
@initial import of GMP 6.1.2.  main changes from 5.1.3 below.

notes:
 - support for thumb-less ARM chips was in our port of 5.1.3, but a
   similar method has been provided upstream now
 - someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

  FEATURES
  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
    on Skylake Pentiums).
  * Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

  BUGS FIXED
  * The public function mpn_com is now correctly declared in gmp.h.
  * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
    some obsolete CPUs.
  * Various problems related to precision for mpf have been fixed.
  * Fixed ABI incompatible stack alignment in calls from assembly code.
  * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
  SPEEDUPS
  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    new ADX instructions.
  * Square root is now faster when the remainder is not needed. Also the speed
    to compute the k-th root improved, for small sizes.
  FEATURES
  * New C++ functions gcd and lcm for mpz_class.
  * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
  * New public mpq_cmp_z function, to efficiently compare rationals with
    integers.
  * Support for more 32-bit arm processors.
  * Support for AVX-less modern x86 CPUs. (Such support might be missing either
    because the CPU vendor chose to disable AVX, or because the running kernel
    lacks AVX context switch support.)
  * Support for NetBSD under Xen; we switch off AVX unconditionally under
    NetBSD since a bug in NetBSD makes AVX fail under Xen.
  MISC
  * Tuned values for FFT multiplications are provided for larger number on
    many platforms.

Changes between GMP version 5.1.* and 6.0.0
  BUGS FIXED
  * The function mpz_invert now considers any number invertible in Z/1Z.
  * The mpn multiply code now handles operands of more than 2^31 limbs
    correctly.  (Note however that the mpz code is limited to 2^32 bits on
    32-bit hosts and 2^37 bits on 64-bit hosts.)
  SPEEDUPS
  * Plain division of large operands is faster and more monotonous in operand
    size.
  * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
    assembly.
  * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
    and vastly expanded assembly support.  Speedup also for the older Core 2
    and Nehalem.
  * Faster mixed arithmetic between mpq_class and double.
  FEATURES
  * Support for new Intel and AMD CPUs.
  * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
    silent multiplication and squaring.
  * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
    side-channel silent division.
  * New public functions mpn_cnd_add_n and mpn_cnd_sub_n.  Side-channel silent
    conditional addition and subtraction.
  * New public function mpn_sec_powm, implementing side-channel silent modexp.
  * New public function mpn_sec_invert, implementing side-channel silent
    modular inversion.
  * Better support for applications which use the mpz_t type, but nevertheless
    need to call some of the lower-level mpn functions.  See the documentation
    for mpz_limbs_read and related functions.
@
text
@d8 1
a8 1
dnl
d10 4
a13 14
dnl  it under the terms of either:
dnl
dnl    * the GNU Lesser General Public License as published by the Free
dnl      Software Foundation; either version 3 of the License, or (at your
dnl      option) any later version.
dnl
dnl  or
dnl
dnl    * the GNU General Public License as published by the Free Software
dnl      Foundation; either version 2 of the License, or (at your option) any
dnl      later version.
dnl
dnl  or both in parallel, as here.
dnl
d16 5
a20 6
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
dnl  for more details.
dnl
dnl  You should have received copies of the GNU General Public License and the
dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
dnl  see https://www.gnu.org/licenses/.
d267 1
a267 1
	LDGP(	r29, 0(r26))
d275 1
@


1.1.1.1.8.1
log
@file mod_1_4.asm was added on branch tls-maxphys on 2014-08-19 23:59:49 +0000
@
text
@d1 326
@


1.1.1.1.8.2
log
@Rebase to HEAD as of a few days ago.
@
text
@a0 326
dnl Alpha mpn_mod_1s_4p

dnl  Contributed to the GNU project by Torbjorn Granlund.

dnl  Copyright 2009, 2010 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C TODO:
C  * Optimise.  2.75 c/l should be possible.
C  * Write a proper mpn_mod_1s_4p_cps.  The code below was compiler generated.
C  * Optimise feed-in code, starting the sw pipeline in switch code.
C  * Shorten software pipeline.  The mul instructions are scheduled too far
C    from their users.  Fixing this will allow us to use fewer registers.
C  * If we cannot reduce register usage, write perhaps small-n basecase.
C  * Does this work for PIC?

C      cycles/limb
C EV4:     ?
C EV5:    23
C EV6:     3

define(`ap',     `r16')
define(`n',      `r17')
define(`pl',     `r24')
define(`ph',     `r25')
define(`rl',     `r6')
define(`rh',     `r7')
define(`B1modb', `r1')
define(`B2modb', `r2')
define(`B3modb', `r3')
define(`B4modb', `r4')
define(`B5modb', `r5')

ASM_START()
PROLOGUE(mpn_mod_1s_4p)
	lda	r30, -64(r30)
	stq	r9, 8(r30)
	ldq	B1modb, 16(r19)
	stq	r10, 16(r30)
	ldq	B2modb, 24(r19)
	stq	r11, 24(r30)
	ldq	B3modb, 32(r19)
	stq	r12, 32(r30)
	ldq	B4modb, 40(r19)
	stq	r13, 40(r30)
	ldq	B5modb, 48(r19)
	s8addq	n, ap, ap		C point ap at vector end

	and	n, 3, r0
	lda	n, -4(n)
	beq	r0, L(b0)
	lda	r6, -2(r0)
	blt	r6, L(b1)
	beq	r6, L(b2)

L(b3):	ldq	r21, -16(ap)
	ldq	r22, -8(ap)
	ldq	r20, -24(ap)
	mulq	r21, B1modb, r8
	umulh	r21, B1modb, r12
	mulq	r22, B2modb, r9
	umulh	r22, B2modb, r13
	addq	r8, r20, pl
	cmpult	pl, r8, r0
	addq	r0, r12, ph
	addq	r9, pl, rl
	cmpult	rl, r9, r0
	addq	r13, ph, ph
	addq	r0, ph, rh
	lda	ap, -56(ap)
	br	L(com)

L(b0):	ldq	r21, -24(ap)
	ldq	r22, -16(ap)
	ldq	r23, -8(ap)
	ldq	r20, -32(ap)
	mulq	r21, B1modb, r8
	umulh	r21, B1modb, r12
	mulq	r22, B2modb, r9
	umulh	r22, B2modb, r13
	mulq	r23, B3modb, r10
	umulh	r23, B3modb, r27
	addq	r8, r20, pl
	cmpult	pl, r8, r0
	addq	r0, r12, ph
	addq	r9, pl, pl
	cmpult	pl, r9, r0
	addq	r13, ph, ph
	addq	r0, ph, ph
	addq	r10, pl, rl
	cmpult	rl, r10, r0
	addq	r27, ph, ph
	addq	r0, ph, rh
	lda	ap, -64(ap)
	br	L(com)

L(b1):	bis	r31, r31, rh
	ldq	rl, -8(ap)
	lda	ap, -40(ap)
	br	L(com)

L(b2):	ldq	rh, -8(ap)
	ldq	rl, -16(ap)
	lda	ap, -48(ap)

L(com):	ble	n, L(ed3)
	ldq	r21, 8(ap)
	ldq	r22, 16(ap)
	ldq	r23, 24(ap)
	ldq	r20, 0(ap)
	lda	n, -4(n)
	lda	ap, -32(ap)
	mulq	r21, B1modb, r8
	umulh	r21, B1modb, r12
	mulq	r22, B2modb, r9
	umulh	r22, B2modb, r13
	mulq	r23, B3modb, r10
	umulh	r23, B3modb, r27
	mulq	rl, B4modb, r11
	umulh	rl, B4modb, r28
	ble	n, L(ed2)

	ALIGN(16)
L(top):	ldq	r21, 8(ap)
	mulq	rh, B5modb, rl
	addq	r8, r20, pl
	ldq	r22, 16(ap)
	cmpult	pl, r8, r0
	umulh	rh, B5modb, rh
	ldq	r23, 24(ap)
	addq	r0, r12, ph
	addq	r9, pl, pl
	mulq	r21, B1modb, r8
	cmpult	pl, r9, r0
	addq	r13, ph, ph
	umulh	r21, B1modb, r12
	lda	ap, -32(ap)
	addq	r0, ph, ph
	addq	r10, pl, pl
	mulq	r22, B2modb, r9
	cmpult	pl, r10, r0
	addq	r27, ph, ph
	addq	r11, pl, pl
	umulh	r22, B2modb, r13
	addq	r0, ph, ph
	cmpult	pl, r11, r0
	addq	r28, ph, ph
	mulq	r23, B3modb, r10
	ldq	r20, 32(ap)
	addq	pl, rl, rl
	umulh	r23, B3modb, r27
	addq	r0, ph, ph
	cmpult	rl, pl, r0
	mulq	rl, B4modb, r11
	addq	ph, rh, rh
	umulh	rl, B4modb, r28
	addq	r0, rh, rh
	lda	n, -4(n)
	bgt	n, L(top)

L(ed2):	mulq	rh, B5modb, rl
	addq	r8, r20, pl
	umulh	rh, B5modb, rh
	cmpult	pl, r8, r0
	addq	r0, r12, ph
	addq	r9, pl, pl
	cmpult	pl, r9, r0
	addq	r13, ph, ph
	addq	r0, ph, ph
	addq	r10, pl, pl
	cmpult	pl, r10, r0
	addq	r27, ph, ph
	addq	r11, pl, pl
	addq	r0, ph, ph
	cmpult	pl, r11, r0
	addq	r28, ph, ph
	addq	pl, rl, rl
	addq	r0, ph, ph
	cmpult	rl, pl, r0
	addq	ph, rh, rh
	addq	r0, rh, rh

L(ed3):	mulq	rh, B1modb, r8
	umulh	rh, B1modb, rh
	addq	r8, rl, rl
	cmpult	rl, r8, r0
	addq	r0, rh, rh

	ldq	r24, 8(r19)		C cnt
	sll	rh, r24, rh
	subq	r31, r24, r25
	srl	rl, r25, r2
	sll	rl, r24, rl
	or	r2, rh, rh

	ldq	r23, 0(r19)		C bi
	mulq	rh, r23, r8
	umulh	rh, r23, r9
	addq	rh, 1, r7
	addq	r8, rl, r8		C ql
	cmpult	r8, rl, r0
	addq	r9, r7, r9
	addq	r0, r9, r9		C qh
	mulq	r9, r18, r21		C qh * b
	subq	rl, r21, rl
	cmpult	r8, rl, r0		C rl > ql
	negq	r0, r0
	and	r0, r18, r0
	addq	rl, r0, rl
	cmpule	r18, rl, r0		C rl >= b
	negq	r0, r0
	and	r0, r18, r0
	subq	rl, r0, rl

	srl	rl, r24, r0

	ldq	r9, 8(r30)
	ldq	r10, 16(r30)
	ldq	r11, 24(r30)
	ldq	r12, 32(r30)
	ldq	r13, 40(r30)
	lda	r30, 64(r30)
	ret	r31, (r26), 1
EPILOGUE()

PROLOGUE(mpn_mod_1s_4p_cps,gp)
	lda	r30, -32(r30)
	stq	r26, 0(r30)
	stq	r9, 8(r30)
	stq	r10, 16(r30)
	stq	r11, 24(r30)
	mov	r16, r11
	LEA(	r4, __clz_tab)
	lda	r10, 65(r31)
	cmpbge	r31, r17, r1
	srl	r1, 1, r1
	xor	r1, 127, r1
	addq	r1, r4, r1
	ldq_u	r2, 0(r1)
	extbl	r2, r1, r2
	s8subq	r2, 7, r2
	srl	r17, r2, r3
	subq	r10, r2, r10
	addq	r3, r4, r3
	ldq_u	r1, 0(r3)
	extbl	r1, r3, r1
	subq	r10, r1, r10
	sll	r17, r10, r9
	mov	r9, r16
	jsr	r26, mpn_invert_limb
	ldah	r29, 0(r26)
	subq	r31, r10, r2
	lda	r1, 1(r31)
	sll	r1, r10, r1
	subq	r31, r9, r3
	srl	r0, r2, r2
	ldq	r26, 0(r30)
	bis	r2, r1, r2
	lda	r29, 0(r29)
	stq	r0, 0(r11)
	stq	r10, 8(r11)
	mulq	r2, r3, r2
	srl	r2, r10, r3
	umulh	r2, r0, r1
	stq	r3, 16(r11)
	mulq	r2, r0, r3
	ornot	r31, r1, r1
	subq	r1, r2, r1
	mulq	r1, r9, r1
	addq	r1, r9, r2
	cmpule	r1, r3, r3
	cmoveq	r3, r2, r1
	srl	r1, r10, r3
	umulh	r1, r0, r2
	stq	r3, 24(r11)
	mulq	r1, r0, r3
	ornot	r31, r2, r2
	subq	r2, r1, r2
	mulq	r2, r9, r2
	addq	r2, r9, r1
	cmpule	r2, r3, r3
	cmoveq	r3, r1, r2
	srl	r2, r10, r1
	umulh	r2, r0, r3
	stq	r1, 32(r11)
	mulq	r2, r0, r1
	ornot	r31, r3, r3
	subq	r3, r2, r3
	mulq	r3, r9, r3
	addq	r3, r9, r2
	cmpule	r3, r1, r1
	cmoveq	r1, r2, r3
	srl	r3, r10, r2
	umulh	r3, r0, r1
	stq	r2, 40(r11)
	mulq	r3, r0, r0
	ornot	r31, r1, r1
	subq	r1, r3, r1
	mulq	r1, r9, r1
	addq	r1, r9, r9
	cmpule	r1, r0, r0
	cmoveq	r0, r9, r1
	ldq	r9, 8(r30)
	srl	r1, r10, r1
	ldq	r10, 16(r30)
	stq	r1, 48(r11)
	ldq	r11, 24(r30)
	lda	r30, 32(r30)
	ret	r31, (r26), 1
EPILOGUE()
@


1.1.1.1.4.1
log
@file mod_1_4.asm was added on branch yamt-pagecache on 2014-05-22 14:08:59 +0000
@
text
@d1 326
@


1.1.1.1.4.2
log
@sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")
@
text
@a0 326
dnl Alpha mpn_mod_1s_4p

dnl  Contributed to the GNU project by Torbjorn Granlund.

dnl  Copyright 2009, 2010 Free Software Foundation, Inc.

dnl  This file is part of the GNU MP Library.

dnl  The GNU MP Library is free software; you can redistribute it and/or modify
dnl  it under the terms of the GNU Lesser General Public License as published
dnl  by the Free Software Foundation; either version 3 of the License, or (at
dnl  your option) any later version.

dnl  The GNU MP Library is distributed in the hope that it will be useful, but
dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
dnl  License for more details.

dnl  You should have received a copy of the GNU Lesser General Public License
dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.

include(`../config.m4')

C TODO:
C  * Optimise.  2.75 c/l should be possible.
C  * Write a proper mpn_mod_1s_4p_cps.  The code below was compiler generated.
C  * Optimise feed-in code, starting the sw pipeline in switch code.
C  * Shorten software pipeline.  The mul instructions are scheduled too far
C    from their users.  Fixing this will allow us to use fewer registers.
C  * If we cannot reduce register usage, write perhaps small-n basecase.
C  * Does this work for PIC?

C      cycles/limb
C EV4:     ?
C EV5:    23
C EV6:     3

define(`ap',     `r16')
define(`n',      `r17')
define(`pl',     `r24')
define(`ph',     `r25')
define(`rl',     `r6')
define(`rh',     `r7')
define(`B1modb', `r1')
define(`B2modb', `r2')
define(`B3modb', `r3')
define(`B4modb', `r4')
define(`B5modb', `r5')

ASM_START()
PROLOGUE(mpn_mod_1s_4p)
	lda	r30, -64(r30)
	stq	r9, 8(r30)
	ldq	B1modb, 16(r19)
	stq	r10, 16(r30)
	ldq	B2modb, 24(r19)
	stq	r11, 24(r30)
	ldq	B3modb, 32(r19)
	stq	r12, 32(r30)
	ldq	B4modb, 40(r19)
	stq	r13, 40(r30)
	ldq	B5modb, 48(r19)
	s8addq	n, ap, ap		C point ap at vector end

	and	n, 3, r0
	lda	n, -4(n)
	beq	r0, L(b0)
	lda	r6, -2(r0)
	blt	r6, L(b1)
	beq	r6, L(b2)

L(b3):	ldq	r21, -16(ap)
	ldq	r22, -8(ap)
	ldq	r20, -24(ap)
	mulq	r21, B1modb, r8
	umulh	r21, B1modb, r12
	mulq	r22, B2modb, r9
	umulh	r22, B2modb, r13
	addq	r8, r20, pl
	cmpult	pl, r8, r0
	addq	r0, r12, ph
	addq	r9, pl, rl
	cmpult	rl, r9, r0
	addq	r13, ph, ph
	addq	r0, ph, rh
	lda	ap, -56(ap)
	br	L(com)

L(b0):	ldq	r21, -24(ap)
	ldq	r22, -16(ap)
	ldq	r23, -8(ap)
	ldq	r20, -32(ap)
	mulq	r21, B1modb, r8
	umulh	r21, B1modb, r12
	mulq	r22, B2modb, r9
	umulh	r22, B2modb, r13
	mulq	r23, B3modb, r10
	umulh	r23, B3modb, r27
	addq	r8, r20, pl
	cmpult	pl, r8, r0
	addq	r0, r12, ph
	addq	r9, pl, pl
	cmpult	pl, r9, r0
	addq	r13, ph, ph
	addq	r0, ph, ph
	addq	r10, pl, rl
	cmpult	rl, r10, r0
	addq	r27, ph, ph
	addq	r0, ph, rh
	lda	ap, -64(ap)
	br	L(com)

L(b1):	bis	r31, r31, rh
	ldq	rl, -8(ap)
	lda	ap, -40(ap)
	br	L(com)

L(b2):	ldq	rh, -8(ap)
	ldq	rl, -16(ap)
	lda	ap, -48(ap)

L(com):	ble	n, L(ed3)
	ldq	r21, 8(ap)
	ldq	r22, 16(ap)
	ldq	r23, 24(ap)
	ldq	r20, 0(ap)
	lda	n, -4(n)
	lda	ap, -32(ap)
	mulq	r21, B1modb, r8
	umulh	r21, B1modb, r12
	mulq	r22, B2modb, r9
	umulh	r22, B2modb, r13
	mulq	r23, B3modb, r10
	umulh	r23, B3modb, r27
	mulq	rl, B4modb, r11
	umulh	rl, B4modb, r28
	ble	n, L(ed2)

	ALIGN(16)
L(top):	ldq	r21, 8(ap)
	mulq	rh, B5modb, rl
	addq	r8, r20, pl
	ldq	r22, 16(ap)
	cmpult	pl, r8, r0
	umulh	rh, B5modb, rh
	ldq	r23, 24(ap)
	addq	r0, r12, ph
	addq	r9, pl, pl
	mulq	r21, B1modb, r8
	cmpult	pl, r9, r0
	addq	r13, ph, ph
	umulh	r21, B1modb, r12
	lda	ap, -32(ap)
	addq	r0, ph, ph
	addq	r10, pl, pl
	mulq	r22, B2modb, r9
	cmpult	pl, r10, r0
	addq	r27, ph, ph
	addq	r11, pl, pl
	umulh	r22, B2modb, r13
	addq	r0, ph, ph
	cmpult	pl, r11, r0
	addq	r28, ph, ph
	mulq	r23, B3modb, r10
	ldq	r20, 32(ap)
	addq	pl, rl, rl
	umulh	r23, B3modb, r27
	addq	r0, ph, ph
	cmpult	rl, pl, r0
	mulq	rl, B4modb, r11
	addq	ph, rh, rh
	umulh	rl, B4modb, r28
	addq	r0, rh, rh
	lda	n, -4(n)
	bgt	n, L(top)

L(ed2):	mulq	rh, B5modb, rl
	addq	r8, r20, pl
	umulh	rh, B5modb, rh
	cmpult	pl, r8, r0
	addq	r0, r12, ph
	addq	r9, pl, pl
	cmpult	pl, r9, r0
	addq	r13, ph, ph
	addq	r0, ph, ph
	addq	r10, pl, pl
	cmpult	pl, r10, r0
	addq	r27, ph, ph
	addq	r11, pl, pl
	addq	r0, ph, ph
	cmpult	pl, r11, r0
	addq	r28, ph, ph
	addq	pl, rl, rl
	addq	r0, ph, ph
	cmpult	rl, pl, r0
	addq	ph, rh, rh
	addq	r0, rh, rh

L(ed3):	mulq	rh, B1modb, r8
	umulh	rh, B1modb, rh
	addq	r8, rl, rl
	cmpult	rl, r8, r0
	addq	r0, rh, rh

	ldq	r24, 8(r19)		C cnt
	sll	rh, r24, rh
	subq	r31, r24, r25
	srl	rl, r25, r2
	sll	rl, r24, rl
	or	r2, rh, rh

	ldq	r23, 0(r19)		C bi
	mulq	rh, r23, r8
	umulh	rh, r23, r9
	addq	rh, 1, r7
	addq	r8, rl, r8		C ql
	cmpult	r8, rl, r0
	addq	r9, r7, r9
	addq	r0, r9, r9		C qh
	mulq	r9, r18, r21		C qh * b
	subq	rl, r21, rl
	cmpult	r8, rl, r0		C rl > ql
	negq	r0, r0
	and	r0, r18, r0
	addq	rl, r0, rl
	cmpule	r18, rl, r0		C rl >= b
	negq	r0, r0
	and	r0, r18, r0
	subq	rl, r0, rl

	srl	rl, r24, r0

	ldq	r9, 8(r30)
	ldq	r10, 16(r30)
	ldq	r11, 24(r30)
	ldq	r12, 32(r30)
	ldq	r13, 40(r30)
	lda	r30, 64(r30)
	ret	r31, (r26), 1
EPILOGUE()

PROLOGUE(mpn_mod_1s_4p_cps,gp)
	lda	r30, -32(r30)
	stq	r26, 0(r30)
	stq	r9, 8(r30)
	stq	r10, 16(r30)
	stq	r11, 24(r30)
	mov	r16, r11
	LEA(	r4, __clz_tab)
	lda	r10, 65(r31)
	cmpbge	r31, r17, r1
	srl	r1, 1, r1
	xor	r1, 127, r1
	addq	r1, r4, r1
	ldq_u	r2, 0(r1)
	extbl	r2, r1, r2
	s8subq	r2, 7, r2
	srl	r17, r2, r3
	subq	r10, r2, r10
	addq	r3, r4, r3
	ldq_u	r1, 0(r3)
	extbl	r1, r3, r1
	subq	r10, r1, r10
	sll	r17, r10, r9
	mov	r9, r16
	jsr	r26, mpn_invert_limb
	ldah	r29, 0(r26)
	subq	r31, r10, r2
	lda	r1, 1(r31)
	sll	r1, r10, r1
	subq	r31, r9, r3
	srl	r0, r2, r2
	ldq	r26, 0(r30)
	bis	r2, r1, r2
	lda	r29, 0(r29)
	stq	r0, 0(r11)
	stq	r10, 8(r11)
	mulq	r2, r3, r2
	srl	r2, r10, r3
	umulh	r2, r0, r1
	stq	r3, 16(r11)
	mulq	r2, r0, r3
	ornot	r31, r1, r1
	subq	r1, r2, r1
	mulq	r1, r9, r1
	addq	r1, r9, r2
	cmpule	r1, r3, r3
	cmoveq	r3, r2, r1
	srl	r1, r10, r3
	umulh	r1, r0, r2
	stq	r3, 24(r11)
	mulq	r1, r0, r3
	ornot	r31, r2, r2
	subq	r2, r1, r2
	mulq	r2, r9, r2
	addq	r2, r9, r1
	cmpule	r2, r3, r3
	cmoveq	r3, r1, r2
	srl	r2, r10, r1
	umulh	r2, r0, r3
	stq	r1, 32(r11)
	mulq	r2, r0, r1
	ornot	r31, r3, r3
	subq	r3, r2, r3
	mulq	r3, r9, r3
	addq	r3, r9, r2
	cmpule	r3, r1, r1
	cmoveq	r1, r2, r3
	srl	r3, r10, r2
	umulh	r3, r0, r1
	stq	r2, 40(r11)
	mulq	r3, r0, r0
	ornot	r31, r1, r1
	subq	r1, r3, r1
	mulq	r1, r9, r1
	addq	r1, r9, r9
	cmpule	r1, r0, r0
	cmoveq	r0, r9, r1
	ldq	r9, 8(r30)
	srl	r1, r10, r1
	ldq	r10, 16(r30)
	stq	r1, 48(r11)
	ldq	r11, 24(r30)
	lda	r30, 32(r30)
	ret	r31, (r26), 1
EPILOGUE()
@