head	1.29;
access;
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	netbsd-9-5-RELEASE:1.29
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	netbsd-10-1-RELEASE:1.29
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	perseant-exfatfs:1.29.0.36
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	netbsd-8-3-RELEASE:1.29
	netbsd-9-4-RELEASE:1.29
	netbsd-10-0-RELEASE:1.29
	netbsd-10-0-RC6:1.29
	netbsd-10-0-RC5:1.29
	netbsd-10-0-RC4:1.29
	netbsd-10-0-RC3:1.29
	netbsd-10-0-RC2:1.29
	thorpej-ifq:1.29.0.34
	thorpej-ifq-base:1.29
	thorpej-altq-separation:1.29.0.32
	thorpej-altq-separation-base:1.29
	netbsd-10-0-RC1:1.29
	netbsd-10:1.29.0.30
	netbsd-10-base:1.29
	netbsd-9-3-RELEASE:1.29
	cjep_sun2x-base1:1.29
	cjep_sun2x:1.29.0.28
	cjep_sun2x-base:1.29
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	netbsd-9-1-RELEASE:1.29
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	netbsd-8-2-RELEASE:1.29
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	netbsd-9-0-RC1:1.29
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	netbsd-9:1.29.0.18
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	netbsd-8-1-RELEASE:1.29
	netbsd-8-1-RC1:1.29
	pgoyette-compat-merge-20190127:1.29
	pgoyette-compat-20190127:1.29
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	perseant-stdc-iso10646:1.29.0.10
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	netbsd-8:1.29.0.8
	netbsd-8-base:1.29
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	netbsd-7-1-RELEASE:1.23.2.1
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	netbsd-7-nhusb-base-20170116:1.23.2.1
	bouyer-socketcan:1.29.0.4
	bouyer-socketcan-base:1.29
	pgoyette-localcount-20170107:1.29
	netbsd-7-1-RC1:1.23.2.1
	pgoyette-localcount-20161104:1.29
	netbsd-7-0-2-RELEASE:1.23.2.1
	localcount-20160914:1.29
	netbsd-7-nhusb:1.23.2.1.0.4
	netbsd-7-nhusb-base:1.23.2.1
	pgoyette-localcount-20160806:1.29
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	pgoyette-localcount:1.29.0.2
	pgoyette-localcount-base:1.29
	netbsd-7-0-1-RELEASE:1.23.2.1
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	netbsd-7-0-RELEASE:1.23.2.1
	netbsd-7-0-RC3:1.23.2.1
	netbsd-7-0-RC2:1.23.2.1
	netbsd-7-0-RC1:1.23.2.1
	netbsd-5-2-3-RELEASE:1.7
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	netbsd-6-0-6-RELEASE:1.8
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	netbsd-7:1.23.0.2
	netbsd-7-base:1.23
	yamt-pagecache-base9:1.22
	yamt-pagecache-tag8:1.8.8.1
	netbsd-6-1-4-RELEASE:1.8
	netbsd-6-0-5-RELEASE:1.8
	tls-earlyentropy:1.22.0.2
	tls-earlyentropy-base:1.23
	riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.22
	riastradh-drm2-base3:1.22
	netbsd-6-1-3-RELEASE:1.8
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	rmind-smpnet-nbase:1.13
	netbsd-6-1-1-RELEASE:1.8
	riastradh-drm2-base2:1.10
	riastradh-drm2-base1:1.10
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	riastradh-drm2-base:1.10
	rmind-smpnet-base:1.13
	netbsd-6-1:1.8.0.16
	netbsd-6-0-2-RELEASE:1.8
	netbsd-6-1-RELEASE:1.8
	khorben-n900:1.10.0.8
	netbsd-6-1-RC4:1.8
	netbsd-6-1-RC3:1.8
	agc-symver:1.10.0.6
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	yamt-pagecache-base8:1.10
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	jymxensuspend-base:1.8
	yamt-nfs-mp-base6:1.8
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	jym-xensuspend-nbase:1.8
	yamt-nfs-mp-base3:1.8
	netbsd-5-0:1.7.0.6
	netbsd-5-0-RELEASE:1.7
	netbsd-5-0-RC4:1.7
	netbsd-5-0-RC3:1.7
	netbsd-5-0-RC2:1.7
	jym-xensuspend:1.8.0.2
	jym-xensuspend-base:1.8
	netbsd-5-0-RC1:1.7
	netbsd-5:1.7.0.4
	netbsd-5-base:1.7
	matt-mips64-base2:1.7
	wrstuden-revivesa-base-3:1.6
	wrstuden-revivesa-base-2:1.6
	wrstuden-revivesa-base-1:1.6
	yamt-pf42-base4:1.6
	yamt-pf42-base3:1.6
	hpcarm-cleanup-nbase:1.6
	yamt-pf42-baseX:1.5
	yamt-pf42-base2:1.6
	yamt-nfs-mp-base2:1.6
	wrstuden-revivesa:1.6.0.2
	wrstuden-revivesa-base:1.6
	yamt-nfs-mp-base:1.5
	yamt-pf42:1.5.0.4
	yamt-pf42-base:1.5
	yamt-lazymbuf-base15:1.5
	yamt-lazymbuf-base14:1.5
	keiichi-mipv6:1.5.0.2
	keiichi-mipv6-base:1.5
	matt-armv6-base:1.3
	matt-armv6:1.3.0.4
	matt-armv6-nbase:1.5
	yamt-kmem-base3:1.3
	cube-autoconf:1.3.0.2
	cube-autoconf-base:1.3
	yamt-kmem-base2:1.3
	yamt-kmem-base:1.3
	reinoud-bufcleanup-nbase:1.3
	reinoud-bufcleanup-base:1.3
	yamt-x86pmap-base4:1.1
	yamt-x86pmap-base3:1.1
	yamt-x86pmap-base2:1.1
	yamt-x86pmap-base:1.1
	hpcarm-cleanup:1.1.0.4
	hpcarm-cleanup-base:1.5
	yamt-idlelwp-base8:1.1
	thorpej-atomic:1.1.0.2;
locks; strict;
comment	@# @;


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desc
@@


1.29
log
@Back out last change; fixed in the correct place.
@
text
@#	$NetBSD: Makefile.inc,v 1.28 2015/06/07 11:46:56 joerg Exp $

.ifnmake obj
.include "${NETBSDSRCDIR}/common/lib/libc/arch/arm/features.mk"
.endif

.if defined(LIB) && (${LIB} == "kern" || ${LIB} == "c" || ${LIB} == "pthread" \
	|| ${LIB} == "rump")

.if "${FEAT_LDREX}" == "no"
SRCS.atomic+=	atomic_add_32_cas.c atomic_add_32_nv_cas.c \
		atomic_and_32_cas.c atomic_and_32_nv_cas.c \
		atomic_dec_32_cas.c atomic_dec_32_nv_cas.c \
		atomic_inc_32_cas.c atomic_inc_32_nv_cas.c \
		atomic_or_32_cas.c atomic_or_32_nv_cas.c \
		atomic_swap_32_cas.c membar_ops_nop.c

.if ${LIB} == "c"
SRCS.atomic+=	atomic_xor_32_cas.c atomic_xor_16_cas.c atomic_xor_8_cas.c \
		atomic_sub_32_cas.c atomic_sub_16_cas.c atomic_sub_8_cas.c \
		atomic_nand_32_cas.c atomic_nand_16_cas.c atomic_nand_8_cas.c \
		atomic_or_16_cas.c atomic_or_8_cas.c \
		atomic_and_16_cas.c atomic_and_8_cas.c \
		atomic_add_16_cas.c atomic_add_8_cas.c \
		atomic_swap_16_cas.c atomic_swap_8_cas.c \
		atomic_cas_32_cas.c atomic_cas_16_cas.c atomic_cas_8_cas.c \
		atomic_load.c atomic_store.c \
		atomic_and_16_nv_cas.c atomic_and_8_nv_cas.c	\
		atomic_c11_compare_exchange_cas_32.c	\
		atomic_c11_compare_exchange_cas_16.c	\
		atomic_c11_compare_exchange_cas_8.c
.endif

.else
.for op in add and cas nand or xor
.for sz in 8 16 32 64
SRCS.atomic+=	atomic_${op}_${sz}.S
.endfor
.endfor
SRCS.atomic+=	atomic_dec_32.S atomic_dec_64.S
SRCS.atomic+=	atomic_inc_32.S atomic_inc_64.S
SRCS.atomic+=	atomic_sub_64.S
SRCS.atomic+=	atomic_swap.S atomic_swap_16.S atomic_swap_64.S
SRCS.atomic+=	membar_ops.S
.if defined(LIB) && ${LIB} != "kern" && ${LIB} != "rump"
.for op in add and nand or sub xor
SRCS.atomic+=	sync_fetch_and_${op}_8.S
.endfor
.for sz in 1 2 4 8
SRCS.atomic+=	sync_bool_compare_and_swap_${sz}.S
.endfor
.endif
.endif

.endif

.if defined(LIB) && (${LIB} == "c" || ${LIB} == "pthread" || ${LIB} == "rump")

SRCS.atomic+=	atomic_simplelock.c
.if "${FEAT_THUMB2}" == "no"
CPUFLAGS.atomic_simplelock.c+=	-marm
.endif

.endif

.if defined(LIB) && (${LIB} == "c" || ${LIB} == "pthread")

.if "${FEAT_LDREX}" == "no"
SRCS.atomic+=	atomic_init_testset.c
SRCS.atomic+=	atomic_cas_up.S
CPPFLAGS+= -D__HAVE_ASM_ATOMIC_CAS_UP
CPPFLAGS+= -D__HAVE_ASM_ATOMIC_CAS_16_UP
CPPFLAGS+= -D__HAVE_ASM_ATOMIC_CAS_8_UP
.if "${FEAT_EABI}" == "yes" && "${FEAT_LDRD}" == "yes"
CPPFLAGS+= -D__HAVE_ATOMIC_CAS_64_UP -D__HAVE_ASM_ATOMIC_CAS_64_UP
.endif
.else
SRCS.atomic+=	atomic_init_cas.c
.endif #FEAT_LDREX

.endif #LIB

.if "${FEAT_THUMB2}" == "no"
.for f in ${SRCS.atomic:M*.S}
CPUFLAGS.$f+=	-marm
.endfor
.endif

SRCS+=	${SRCS.atomic}
@


1.29.16.1
log
@Sync with HEAD
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.29 2015/06/07 15:06:24 matt Exp $
@


1.29.16.2
log
@Ooops, restore accidently removed files from merge mishap
@
text
@@


1.28
log
@Require ARMv5TE to assemble.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.27 2015/05/17 22:08:24 justin Exp $
a70 1
AFLAGS.atomic_cas_up.S+=	-march=armv5te
@


1.27
log
@Move arm sync_* changes to Makefile.inc
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.26 2014/10/14 07:25:05 martin Exp $
d71 1
@


1.26
log
@Provide C++ 2011 <atomic> support functions for hppa and arm.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.25 2014/10/13 12:49:59 martin Exp $
d45 1
a45 1
.if defined(LIB) && ${LIB} != "kern"
@


1.25
log
@Move the and_{16,8}_nv sources into the right (libc only) block.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.24 2014/10/13 07:31:12 martin Exp $
d28 4
a31 1
		atomic_and_16_nv_cas.c atomic_and_8_nv_cas.c
@


1.24
log
@Provide __sync_and_and_fetch_2 and __sync_and_and_fetch_1 for pre-ARMv6,
they are needed for the C++ 2011 <atomic> stuff.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.23 2014/07/05 20:44:46 joerg Exp $
d16 1
a16 2
		atomic_swap_32_cas.c membar_ops_nop.c \
		atomic_and_16_nv_cas.c atomic_and_8_nv_cas.c
d27 2
a28 1
		atomic_load.c atomic_store.c
@


1.23
log
@Provide a basic implementation of __atomic_load_* and __atomic_store_*,
used by GCC and LLVM as backing for C11/C++11 atomics, if the hardware
is not known to have corresponding features. Include it on ARM as LLVM
and libc++ hit it when compiled for ARMv4.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.22 2014/03/04 16:15:28 matt Exp $
d16 2
a17 1
		atomic_swap_32_cas.c membar_ops_nop.c
@


1.23.2.1
log
@Pull up following revision(s) (requested by martin in ticket #218):
	common/lib/libc/arch/arm/atomic/Makefile.inc: revision 1.24-1.26
	common/lib/libc/arch/hppa/atomic/Makefile.inc: revision 1.13
	common/lib/libc/arch/mips/atomic/Makefile.inc: revision 1.13
	common/lib/libc/arch/sh3/atomic/Makefile.inc: revision 1.7
	common/lib/libc/arch/sparc/atomic/Makefile.inc: revision 1.18
	common/lib/libc/arch/vax/atomic/Makefile.inc: revision 1.7
	common/lib/libc/atomic/atomic_and_16_nv_cas.c: revision 1.2
	common/lib/libc/atomic/atomic_and_8_nv_cas.c: revision 1.2
	common/lib/libc/atomic/atomic_c11_compare_exchange_cas_16.c: revision 1.1-1.2
	common/lib/libc/atomic/atomic_c11_compare_exchange_cas_32.c: revision 1.1-1.2
	common/lib/libc/atomic/atomic_c11_compare_exchange_cas_8.c: revision 1.1-1.2
	common/lib/libc/atomic/atomic_cas_by_cas32.c: revision 1.4
	common/lib/libc/atomic/atomic_op_namespace.h: revision 1.7
Add __sync_val_compare_and_swap_{1,2} aliases for _atomic_cas_{8,16}
--
Provide __atomic_compare_exchange_N (as needed for the C11 2011 <atomic>
ops) via the corresponding CAS.
--
Hook __atomic_compare_exchange_N into vax libc.
--
Provide __sync_and_and_fetch_2 and __sync_and_and_fetch_1 for pre-ARMv6,
they are needed for the C++ 2011 <atomic> stuff.
--
Add C++ 2011 <atomic> support functions.
--
Move the and_{16,8}_nv sources into the right (libc only) block.
--
Provide <atomic> C++ 2011 support functions for mips and sh3.
--
Provide C++ 2011 <atomic> support functions for hppa and arm.
--
Provide prototypes to fix build with clang.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.23 2014/07/05 20:44:46 joerg Exp $
d27 1
a27 5
		atomic_load.c atomic_store.c \
		atomic_and_16_nv_cas.c atomic_and_8_nv_cas.c	\
		atomic_c11_compare_exchange_cas_32.c	\
		atomic_c11_compare_exchange_cas_16.c	\
		atomic_c11_compare_exchange_cas_8.c
@


1.22
log
@Don't export __sync* if _KERNEL || _STANDALONE are defined.
(except if _RUMPKERNEL is defined)
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.21 2014/03/04 06:36:41 matt Exp $
d26 2
a27 1
		atomic_cas_32_cas.c atomic_cas_16_cas.c atomic_cas_8_cas.c
@


1.22.2.1
log
@Rebase.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.23 2014/07/05 20:44:46 joerg Exp $
d26 1
a26 2
		atomic_cas_32_cas.c atomic_cas_16_cas.c atomic_cas_8_cas.c \
		atomic_load.c atomic_store.c
@


1.21
log
@fix typo.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.20 2014/03/04 03:49:07 matt Exp $
d40 1
d48 1
@


1.20
log
@Add atomic_sub_64.S
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.19 2014/02/27 09:39:00 matt Exp $
d37 1
a37 1
SRCS.atomic+=	atomic_sub_32.S
@


1.19
log
@Add atomic_cas_64 support for ARM EABI on V5TE and V5TEJ cpus.
(strd is atomic).
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.18 2014/02/22 17:16:12 martin Exp $
d37 1
@


1.18
log
@Missed one __sync_* op (or gcc4.8 does inline it, while 4.5 does not?)
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.17 2014/02/22 08:08:56 martin Exp $
d3 2
a4 11
ARMV6= ${CPUFLAGS:M-march=armv6*} ${CPUFLAGS:M-mcpu=arm11*}
ARMV6+= ${CFLAGS:M-march=armv6*:} ${CFLAGS:M-mcpu=arm11*}
ARMV6+= ${CPPFLAGS:M-march=armv6*:} ${CPPFLAGS:M-mcpu=arm11*}
ARMV7= ${CPUFLAGS:M-march=armv7*} ${CPUFLAGS:M-mcpu=cortex*}
ARMV7+= ${CFLAGS:M-march=armv7*:} ${CFLAGS:M-mcpu=cortex*}
ARMV7+= ${CPPFLAGS:M-march=armv7*:} ${CPPFLAGS:M-mcpu=cortex*}
.if empty(CFLAGS:M-march=*) && empty(CFLAGS:M-mcpu=*) \
    && empty(CPPFLAGS:M-march=*) && empty(CPPFLAGS:M-mcpu=*) \
    && empty(CPUFLAGS:M-march=*) && empty(CPUFLAGS:M-mcpu=*)
ARMV6+= ${MACHINE_ARCH:Mearmv6*}
ARMV7+= ${MACHINE_ARCH:Mearmv7*}
d10 1
a10 1
.if empty(ARMV6) && empty(ARMV7)
d52 1
a52 1
.if empty(ARMV7)
d60 1
a60 1
.if empty(ARMV6) && empty(ARMV7)
d66 3
d71 1
a71 1
.endif
d73 1
a73 1
.endif
d75 1
a75 1
.if !empty(ARMV6)
@


1.17
log
@Move the __sync_* ops added in the previous change to a libc-only section
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.16 2014/02/21 21:54:38 martin Exp $
d34 2
a35 1
		atomic_swap_16_cas.c atomic_swap_8_cas.c
@


1.16
log
@Provide the missing __sync_* ops for earlier arm versions
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.15 2014/01/27 18:05:24 matt Exp $
d25 4
a28 2
		atomic_swap_32_cas.c membar_ops_nop.c \
		atomic_xor_32_cas.c atomic_xor_16_cas.c atomic_xor_8_cas.c \
d35 2
@


1.15
log
@Add _atomic_cas_16_up and _atomic_cas_8_up
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.14 2013/11/08 22:42:52 matt Exp $
d25 8
a32 1
		atomic_swap_32_cas.c membar_ops_nop.c
@


1.14
log
@Add support for the gcc __sync builtins.
Note that these need earmv6 or later to get the ldrex/strex instructions
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.13 2013/08/19 03:55:12 matt Exp $
d61 2
@


1.13
log
@Rework to allow thumb armv7 compilation.
Add atomic_simplelock.c for thumb
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.12 2013/08/06 20:49:15 matt Exp $
d9 1
a9 2
.if empty(CPPFLAGS:M-D_STANDALONE) \
    && empty(CFLAGS:M-march=*) && empty(CFLAGS:M-mcpu=*) \
d27 15
a41 6
SRCS.atomic+=	atomic_add_32.S atomic_and_32.S atomic_cas_32.S
SRCS.atomic+=	atomic_dec_32.S atomic_inc_32.S atomic_or_32.S
SRCS.atomic+=	atomic_swap.S membar_ops.S
SRCS.atomic+=	atomic_add_64.S atomic_and_64.S atomic_cas_64.S
SRCS.atomic+=	atomic_dec_64.S atomic_inc_64.S atomic_or_64.S
SRCS.atomic+=	atomic_swap_64.S
@


1.12
log
@Only use MACHINE_ARCH if !_STANDALONE and CPPFLAGS/CFLAGS/CPUFLAGS don't
contain -mcpu or -march
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.11 2013/08/06 20:37:22 matt Exp $
d3 1
a3 3
ARMV6= ${CPUFLAGS:M-march=armv7*} ${CPUFLAGS:M-mcpu=cortex*}
ARMV6+= ${CPUFLAGS:M-march=armv6*} ${CPUFLAGS:M-mcpu=arm11*}
ARMV6+= ${CFLAGS:M-march=armv7*:} ${CFLAGS:M-mcpu=cortex*}
a4 1
ARMV6+= ${CPPFLAGS:M-march=armv7*:} ${CPPFLAGS:M-mcpu=cortex*}
d6 3
d13 2
a14 1
ARMV6+= ${MACHINE_ARCH:Mearmv[67]*}
d20 1
a20 1
.if empty(ARMV6)
d38 9
d49 1
a49 1
.if empty(ARMV6)
d59 6
@


1.11
log
@Select ldrex/strex if ${MACHINE_ARCH:Mearmv[67]*}
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.10 2012/09/11 20:51:25 matt Exp $
d9 4
d14 1
@


1.10
log
@Add 64bit atomic ops for ARMv6+ (using ldrexd/strexd).
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.9 2012/08/16 16:49:10 matt Exp $
d9 1
@


1.10.2.1
log
@Rebase to HEAD as of a few days ago.
@
text
@d1 1
a1 1
#	$NetBSD$
d3 6
a8 3
.ifnmake obj
.include "${NETBSDSRCDIR}/common/lib/libc/arch/arm/features.mk"
.endif
d13 1
a13 1
.if "${FEAT_LDREX}" == "no"
a19 13

.if ${LIB} == "c"
SRCS.atomic+=	atomic_xor_32_cas.c atomic_xor_16_cas.c atomic_xor_8_cas.c \
		atomic_sub_32_cas.c atomic_sub_16_cas.c atomic_sub_8_cas.c \
		atomic_nand_32_cas.c atomic_nand_16_cas.c atomic_nand_8_cas.c \
		atomic_or_16_cas.c atomic_or_8_cas.c \
		atomic_and_16_cas.c atomic_and_8_cas.c \
		atomic_add_16_cas.c atomic_add_8_cas.c \
		atomic_swap_16_cas.c atomic_swap_8_cas.c \
		atomic_cas_32_cas.c atomic_cas_16_cas.c atomic_cas_8_cas.c \
		atomic_load.c atomic_store.c
.endif

d21 6
a26 27
.for op in add and cas nand or xor
.for sz in 8 16 32 64
SRCS.atomic+=	atomic_${op}_${sz}.S
.endfor
.endfor
SRCS.atomic+=	atomic_dec_32.S atomic_dec_64.S
SRCS.atomic+=	atomic_inc_32.S atomic_inc_64.S
SRCS.atomic+=	atomic_sub_64.S
SRCS.atomic+=	atomic_swap.S atomic_swap_16.S atomic_swap_64.S
SRCS.atomic+=	membar_ops.S
.if defined(LIB) && ${LIB} != "kern"
.for op in add and nand or sub xor
SRCS.atomic+=	sync_fetch_and_${op}_8.S
.endfor
.for sz in 1 2 4 8
SRCS.atomic+=	sync_bool_compare_and_swap_${sz}.S
.endfor
.endif
.endif

.endif

.if defined(LIB) && (${LIB} == "c" || ${LIB} == "pthread" || ${LIB} == "rump")

SRCS.atomic+=	atomic_simplelock.c
.if "${FEAT_THUMB2}" == "no"
CPUFLAGS.atomic_simplelock.c+=	-marm
d33 1
a33 1
.if "${FEAT_LDREX}" == "no"
a36 5
CPPFLAGS+= -D__HAVE_ASM_ATOMIC_CAS_16_UP
CPPFLAGS+= -D__HAVE_ASM_ATOMIC_CAS_8_UP
.if "${FEAT_EABI}" == "yes" && "${FEAT_LDRD}" == "yes"
CPPFLAGS+= -D__HAVE_ATOMIC_CAS_64_UP -D__HAVE_ASM_ATOMIC_CAS_64_UP
.endif
d39 1
a39 3
.endif #FEAT_LDREX

.endif #LIB
a40 4
.if "${FEAT_THUMB2}" == "no"
.for f in ${SRCS.atomic:M*.S}
CPUFLAGS.$f+=	-marm
.endfor
@


1.9
log
@Actually use the assembly version of the atomic function if compiling
for armv6 or armv7 cpus.  Use atomic_cas_ptr instead of _lock_cas so
we pick up the assembly version when it's used.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.8 2009/01/04 17:54:29 pooka Exp $
d21 6
a26 3
SRCS.atomic+=	atomic_add_32.S atomic_and_32.S atomic_cas_32.S \
		atomic_dec_32.S atomic_inc_32.S atomic_or_32.S \
		atomic_swap.S membar_ops.S
@


1.8
log
@allow inclusion of atomic ops in librump
@
text
@d1 8
a8 1
#	$NetBSD: Makefile.inc,v 1.7 2008/09/29 08:43:00 ad Exp $
d13 12
a24 4
SRCS+=	atomic_add_32_cas.c atomic_add_32_nv_cas.c atomic_and_32_cas.c \
	atomic_and_32_nv_cas.c atomic_dec_32_cas.c atomic_dec_32_nv_cas.c \
	atomic_inc_32_cas.c atomic_inc_32_nv_cas.c atomic_or_32_cas.c \
	atomic_or_32_nv_cas.c atomic_swap_32_cas.c membar_ops_nop.c
d30 3
a32 2
SRCS+=	atomic_init_testset.c
SRCS+=	atomic_cas_up.S
d34 3
d39 2
@


1.8.12.1
log
@Pull atomic ops from HEAD.
@
text
@d1 1
a1 8
#	$NetBSD: Makefile.inc,v 1.10 2012/09/11 20:51:25 matt Exp $

ARMV6= ${CPUFLAGS:M-march=armv7*} ${CPUFLAGS:M-mcpu=cortex*}
ARMV6+= ${CPUFLAGS:M-march=armv6*} ${CPUFLAGS:M-mcpu=arm11*}
ARMV6+= ${CFLAGS:M-march=armv7*:} ${CFLAGS:M-mcpu=cortex*}
ARMV6+= ${CFLAGS:M-march=armv6*:} ${CFLAGS:M-mcpu=arm11*}
ARMV6+= ${CPPFLAGS:M-march=armv7*:} ${CPPFLAGS:M-mcpu=cortex*}
ARMV6+= ${CPPFLAGS:M-march=armv6*:} ${CPPFLAGS:M-mcpu=arm11*}
d6 4
a9 15
.if empty(ARMV6)
SRCS.atomic+=	atomic_add_32_cas.c atomic_add_32_nv_cas.c \
		atomic_and_32_cas.c atomic_and_32_nv_cas.c \
		atomic_dec_32_cas.c atomic_dec_32_nv_cas.c \
		atomic_inc_32_cas.c atomic_inc_32_nv_cas.c \
		atomic_or_32_cas.c atomic_or_32_nv_cas.c \
		atomic_swap_32_cas.c membar_ops_nop.c
.else
SRCS.atomic+=	atomic_add_32.S atomic_and_32.S atomic_cas_32.S
SRCS.atomic+=	atomic_dec_32.S atomic_inc_32.S atomic_or_32.S
SRCS.atomic+=	atomic_swap.S membar_ops.S
SRCS.atomic+=	atomic_add_64.S atomic_and_64.S atomic_cas_64.S
SRCS.atomic+=	atomic_dec_64.S atomic_inc_64.S atomic_or_64.S
SRCS.atomic+=	atomic_swap_64.S
.endif
d15 2
a16 3
.if empty(ARMV6)
SRCS.atomic+=	atomic_init_testset.c
SRCS.atomic+=	atomic_cas_up.S
a17 3
.else
SRCS.atomic+=	atomic_init_cas.c
.endif
a19 2

SRCS+=	${SRCS.atomic}
@


1.8.8.1
log
@sync with head
@
text
@d1 1
a1 8
#	$NetBSD: Makefile.inc,v 1.8 2009/01/04 17:54:29 pooka Exp $

ARMV6= ${CPUFLAGS:M-march=armv7*} ${CPUFLAGS:M-mcpu=cortex*}
ARMV6+= ${CPUFLAGS:M-march=armv6*} ${CPUFLAGS:M-mcpu=arm11*}
ARMV6+= ${CFLAGS:M-march=armv7*:} ${CFLAGS:M-mcpu=cortex*}
ARMV6+= ${CFLAGS:M-march=armv6*:} ${CFLAGS:M-mcpu=arm11*}
ARMV6+= ${CPPFLAGS:M-march=armv7*:} ${CPPFLAGS:M-mcpu=cortex*}
ARMV6+= ${CPPFLAGS:M-march=armv6*:} ${CPPFLAGS:M-mcpu=arm11*}
d6 4
a9 15
.if empty(ARMV6)
SRCS.atomic+=	atomic_add_32_cas.c atomic_add_32_nv_cas.c \
		atomic_and_32_cas.c atomic_and_32_nv_cas.c \
		atomic_dec_32_cas.c atomic_dec_32_nv_cas.c \
		atomic_inc_32_cas.c atomic_inc_32_nv_cas.c \
		atomic_or_32_cas.c atomic_or_32_nv_cas.c \
		atomic_swap_32_cas.c membar_ops_nop.c
.else
SRCS.atomic+=	atomic_add_32.S atomic_and_32.S atomic_cas_32.S
SRCS.atomic+=	atomic_dec_32.S atomic_inc_32.S atomic_or_32.S
SRCS.atomic+=	atomic_swap.S membar_ops.S
SRCS.atomic+=	atomic_add_64.S atomic_and_64.S atomic_cas_64.S
SRCS.atomic+=	atomic_dec_64.S atomic_inc_64.S atomic_or_64.S
SRCS.atomic+=	atomic_swap_64.S
.endif
d15 2
a16 3
.if empty(ARMV6)
SRCS.atomic+=	atomic_init_testset.c
SRCS.atomic+=	atomic_cas_up.S
a17 3
.else
SRCS.atomic+=	atomic_init_cas.c
.endif
a19 2

SRCS+=	${SRCS.atomic}
@


1.8.8.2
log
@sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.8.8.1 2012/10/30 18:46:09 yamt Exp $
d3 6
a8 3
.ifnmake obj
.include "${NETBSDSRCDIR}/common/lib/libc/arch/arm/features.mk"
.endif
d13 1
a13 1
.if "${FEAT_LDREX}" == "no"
a19 12

.if ${LIB} == "c"
SRCS.atomic+=	atomic_xor_32_cas.c atomic_xor_16_cas.c atomic_xor_8_cas.c \
		atomic_sub_32_cas.c atomic_sub_16_cas.c atomic_sub_8_cas.c \
		atomic_nand_32_cas.c atomic_nand_16_cas.c atomic_nand_8_cas.c \
		atomic_or_16_cas.c atomic_or_8_cas.c \
		atomic_and_16_cas.c atomic_and_8_cas.c \
		atomic_add_16_cas.c atomic_add_8_cas.c \
		atomic_swap_16_cas.c atomic_swap_8_cas.c \
		atomic_cas_32_cas.c atomic_cas_16_cas.c atomic_cas_8_cas.c
.endif

d21 6
a26 27
.for op in add and cas nand or xor
.for sz in 8 16 32 64
SRCS.atomic+=	atomic_${op}_${sz}.S
.endfor
.endfor
SRCS.atomic+=	atomic_dec_32.S atomic_dec_64.S
SRCS.atomic+=	atomic_inc_32.S atomic_inc_64.S
SRCS.atomic+=	atomic_sub_64.S
SRCS.atomic+=	atomic_swap.S atomic_swap_16.S atomic_swap_64.S
SRCS.atomic+=	membar_ops.S
.if defined(LIB) && ${LIB} != "kern"
.for op in add and nand or sub xor
SRCS.atomic+=	sync_fetch_and_${op}_8.S
.endfor
.for sz in 1 2 4 8
SRCS.atomic+=	sync_bool_compare_and_swap_${sz}.S
.endfor
.endif
.endif

.endif

.if defined(LIB) && (${LIB} == "c" || ${LIB} == "pthread" || ${LIB} == "rump")

SRCS.atomic+=	atomic_simplelock.c
.if "${FEAT_THUMB2}" == "no"
CPUFLAGS.atomic_simplelock.c+=	-marm
d33 1
a33 1
.if "${FEAT_LDREX}" == "no"
a36 5
CPPFLAGS+= -D__HAVE_ASM_ATOMIC_CAS_16_UP
CPPFLAGS+= -D__HAVE_ASM_ATOMIC_CAS_8_UP
.if "${FEAT_EABI}" == "yes" && "${FEAT_LDRD}" == "yes"
CPPFLAGS+= -D__HAVE_ATOMIC_CAS_64_UP -D__HAVE_ASM_ATOMIC_CAS_64_UP
.endif
d39 1
a39 3
.endif #FEAT_LDREX

.endif #LIB
a40 4
.if "${FEAT_THUMB2}" == "no"
.for f in ${SRCS.atomic:M*.S}
CPUFLAGS.$f+=	-marm
.endfor
@


1.7
log
@Allow atomic ops to be built as part of libpthread.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.6 2008/04/29 20:57:50 scw Exp $
d3 2
a4 1
.if defined(LIB) && (${LIB} == "kern" || ${LIB} == "c" || ${LIB} == "pthread")
@


1.7.8.1
log
@Enable ldrex/strex based atomic ops on armv6/armv7
@
text
@d1 1
a1 9
#	$NetBSD: Makefile.inc,v 1.7 2008/09/29 08:43:00 ad Exp $

ARMV6= ${CPUFLAGS:M-march=armv7*} ${CPUFLAGS:M-mcpu=cortex*}
ARMV6+= ${CPUFLAGS:M-march=armv6*} ${CPUFLAGS:M-mcpu=arm11*}
ARMV6+= ${CFLAGS:M-march=armv7*:} ${CFLAGS:M-mcpu=cortex*}
ARMV6+= ${CFLAGS:M-march=armv6*:} ${CFLAGS:M-mcpu=arm11*}
ARMV6+= ${CPPFLAGS:M-march=armv7*:} ${CPPFLAGS:M-mcpu=cortex*}
ARMV6+= ${CPPFLAGS:M-march=armv6*:} ${CPPFLAGS:M-mcpu=arm11*}

a3 1
.if ${MACHINE_ARCH:Marmv7*} == "" && empty(ARMV6)
a9 5
.else
SRCS+=	atomic_add_32.S atomic_and_32.S atomic_cas_32.S
SRCS+=	atomic_dec_32.S atomic_inc_32.S atomic_or_32.S
SRCS+=	atomic_swap.S membar_ops.S
.endif
a13 1
.if ${MACHINE_ARCH:Marmv7*} == "" && empty(ARMV6)
a16 4
.else
SRCS+=	atomic_init_cas.c

.endif
@


1.7.8.2
log
@Add 64-bit atomic ops if ARMv6+
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.7.8.1 2013/12/19 01:12:39 matt Exp $
a21 2
SRCS+=	atomic_add_64.S atomic_and_64.S atomic_cas_64.S
SRCS+=	atomic_dec_64.S atomic_inc_64.S atomic_or_64.S
@


1.6
log
@Implement _atomic_cas_up() in assembly code as the compiler cannot be
trusted to generate fully restartable code sequences.

Addresses lib/38482 for ARM and m68000.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.5 2008/02/11 14:21:12 ad Exp $
d3 1
a3 1
.if defined(LIB) && (${LIB} == "kern" || ${LIB} == "c")
d12 1
a12 1
.if defined(LIB) && (${LIB} == "c")
@


1.5
log
@Only build atomic ops for libkern/libc.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.4 2008/02/10 18:45:40 ad Exp $
d15 2
@


1.5.4.1
log
@sync with head.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.5 2008/02/11 14:21:12 ad Exp $
a14 2
SRCS+=	atomic_cas_up.S
CPPFLAGS+= -D__HAVE_ASM_ATOMIC_CAS_UP
@


1.4
log
@Enable the atomic ops in userspace.
@
text
@d1 3
a3 1
#	$NetBSD: Makefile.inc,v 1.3 2007/11/29 15:29:46 ad Exp $
d10 2
@


1.3
log
@Use the CAS-based inc/dec variants, since these CPUs don't have atomic
add in hardware (does arm?).
@
text
@d1 1
a1 3
#	$NetBSD: Makefile.inc,v 1.2 2007/11/29 15:19:54 ad Exp $

.if defined(LIB) && (${LIB} == "kern")
d8 4
@


1.3.4.1
log
@file Makefile.inc was added on branch matt-armv6 on 2008-01-09 01:20:51 +0000
@
text
@d1 10
@


1.3.4.2
log
@sync with HEAD
@
text
@a0 10
#	$NetBSD$

.if defined(LIB) && (${LIB} == "kern")

SRCS+=	atomic_add_32_cas.c atomic_add_32_nv_cas.c atomic_and_32_cas.c \
	atomic_and_32_nv_cas.c atomic_dec_32_cas.c atomic_dec_32_nv_cas.c \
	atomic_inc_32_cas.c atomic_inc_32_nv_cas.c atomic_or_32_cas.c \
	atomic_or_32_nv_cas.c atomic_swap_32_cas.c membar_ops_nop.c

.endif
@


1.3.4.3
log
@sync with HEAD
@
text
@d1 1
a1 1
#	Makefile.inc,v 1.3.4.2 2008/01/09 01:20:51 matt Exp
d3 1
a3 1
.if defined(LIB) && (${LIB} == "kern" || ${LIB} == "c")
a10 6

.if defined(LIB) && (${LIB} == "c")

SRCS+=	atomic_init_testset.c

.endif
@


1.2
log
@Atomic ops for arm.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.2 2007/11/29 01:04:57 ad Exp $
d6 2
a7 2
	atomic_and_32_nv_cas.c atomic_dec_32_add.c atomic_dec_32_nv_add.c \
	atomic_inc_32_add.c atomic_inc_32_nv_add.c atomic_or_32_cas.c \
@


1.1
log
@file Makefile.inc was initially added on branch thorpej-atomic.
@
text
@d1 10
@


1.1.2.1
log
@Atomic ops implementation for ARM.  Everything is built on top of
atomic_cas_32(), which is itself a restartable atomic sequence.
@
text
@a0 32
#	$NetBSD: Makefile.inc,v 1.1.2.1 2007/04/17 05:53:52 thorpej Exp $

.if defined(LIB) && (${LIB} == "kern")

SRCS+=	atomic_add_8_cas.c atomic_add_8_nv_cas.c \
	atomic_add_16_cas.c atomic_add_16_nv_cas.c \
	atomic_add_32_cas.c atomic_add_32_nv_cas.c

SRCS+=	atomic_and_8_cas.c atomic_and_8_nv_cas.c \
	atomic_and_16_cas.c atomic_and_16_nv_cas.c \
	atomic_and_32_cas.c atomic_and_32_nv_cas.c

SRCS+=	atomic_cas_32.S
SRCS+=	atomic_cas_8_cas.c atomic_cas_16_cas.c

SRCS+=	atomic_dec_8_add.c atomic_dec_8_nv_add.c \
	atomic_dec_16_add.c atomic_dec_16_nv_add.c \
	atomic_dec_32_add.c atomic_dec_32_nv_add.c

SRCS+=	atomic_inc_8_add.c atomic_inc_8_nv_add.c \
	atomic_inc_16_add.c atomic_inc_16_nv_add.c \
	atomic_inc_32_add.c atomic_inc_32_nv_add.c

SRCS+=	atomic_or_8_cas.c atomic_or_8_nv_cas.c \
	atomic_or_16_cas.c atomic_or_16_nv_cas.c \
	atomic_or_32_cas.c atomic_or_32_nv_cas.c

SRCS+=	atomic_swap_8_cas.c atomic_swap_16_cas.c atomic_swap_32_cas.c

SRCS+=	membar_ops_nop.c

.endif
@


1.1.2.2
log
@Add armv6 variants of atomic ops which use ldrex/strex.
Add atomic_swap (all arm architectures) which uses swp and swpb.
Add membar_ops which uses armv6 data {sync, memory} barrier.
XXX let thorpej figure out the Makefile magic.
@
text
@d1 1
a1 1
#	$NetBSD: Makefile.inc,v 1.1.2.1 2007/04/18 07:32:30 thorpej Exp $
d28 1
a28 1
SRCS+=	atomic_swap.S atomic_swap_16_cas.c
@