head 1.4; access; symbols pkgsrc-2013Q2:1.4.0.54 pkgsrc-2013Q2-base:1.4 pkgsrc-2012Q4:1.4.0.52 pkgsrc-2012Q4-base:1.4 pkgsrc-2011Q4:1.4.0.50 pkgsrc-2011Q4-base:1.4 pkgsrc-2011Q2:1.4.0.48 pkgsrc-2011Q2-base:1.4 pkgsrc-2009Q4:1.4.0.46 pkgsrc-2009Q4-base:1.4 pkgsrc-2008Q4:1.4.0.44 pkgsrc-2008Q4-base:1.4 pkgsrc-2008Q3:1.4.0.42 pkgsrc-2008Q3-base:1.4 cube-native-xorg:1.4.0.40 cube-native-xorg-base:1.4 pkgsrc-2008Q2:1.4.0.38 pkgsrc-2008Q2-base:1.4 pkgsrc-2008Q1:1.4.0.36 pkgsrc-2008Q1-base:1.4 pkgsrc-2007Q4:1.4.0.34 pkgsrc-2007Q4-base:1.4 pkgsrc-2007Q3:1.4.0.32 pkgsrc-2007Q3-base:1.4 pkgsrc-2007Q2:1.4.0.30 pkgsrc-2007Q2-base:1.4 pkgsrc-2007Q1:1.4.0.28 pkgsrc-2007Q1-base:1.4 pkgsrc-2006Q4:1.4.0.26 pkgsrc-2006Q4-base:1.4 pkgsrc-2006Q3:1.4.0.24 pkgsrc-2006Q3-base:1.4 pkgsrc-2006Q2:1.4.0.22 pkgsrc-2006Q2-base:1.4 pkgsrc-2006Q1:1.4.0.20 pkgsrc-2006Q1-base:1.4 pkgsrc-2005Q4:1.4.0.18 pkgsrc-2005Q4-base:1.4 pkgsrc-2005Q3:1.4.0.16 pkgsrc-2005Q3-base:1.4 pkgsrc-2005Q2:1.4.0.14 pkgsrc-2005Q2-base:1.4 pkgsrc-2005Q1:1.4.0.12 pkgsrc-2005Q1-base:1.4 pkgsrc-2004Q4:1.4.0.10 pkgsrc-2004Q4-base:1.4 pkgsrc-2004Q3:1.4.0.8 pkgsrc-2004Q3-base:1.4 pkgsrc-2004Q2:1.4.0.6 pkgsrc-2004Q2-base:1.4 pkgsrc-2004Q1:1.4.0.4 pkgsrc-2004Q1-base:1.4 pkgsrc-2003Q4:1.4.0.2 pkgsrc-2003Q4-base:1.4 pkgviews:1.3.0.4 pkgviews-base:1.3 buildlink2:1.3.0.2 buildlink2-base:1.3 netbsd-1-5-PATCH003:1.3 netbsd-1-5-PATCH001:1.1; locks; strict; comment @# @; 1.4 date 2002.08.12.01.53.59; author dmcmahill; state dead; branches; next 1.3; 1.3 date 2002.03.28.10.11.53; author jmc; state Exp; branches; next 1.2; 1.2 date 2002.01.03.20.40.43; author tron; state Exp; branches; next 1.1; 1.1 date 2001.04.27.10.45.23; author skrll; state Exp; branches; next ; desc @@ 1.4 log @pull in most recent patches to gcc-2.95.3 from the netbsd-1-6 branch. Includes fixes for sparc, alpha, and others. Should help in keeping pkgsrc running on 1.5.* systems. The patches which mirror those in the main netbsd source tree have been all put into a single distribution patch file. This makes it much easier to maintain and easier to easily see which patches are specific to pkgsrc. @ text @$NetBSD: patch-aw,v 1.3 2002/03/28 10:11:53 jmc Exp $ --- ../gcc-2.95.3/gcc/config/sparc/sparc.c.orig 2001/04/23 12:00:42 1.1.1.2 +++ ../gcc-2.95.3/gcc/config/sparc/sparc.c 2002/03/28 08:14:56 1.5 @@@@ -142,6 +142,8 @@@@ int sparc_align_jumps; int sparc_align_funcs; +char sparc_hard_reg_printed[8]; + struct sparc_cpu_select sparc_select[] = { /* switch name, tune arch */ @@@@ -213,8 +215,11 @@@@ /* TEMIC sparclet */ { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, - /* TI ultrasparc */ - { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 }, + /* TI ultrasparc I, II, IIi */ + { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 + /* Although insns using %y are deprecated, it is a clear win on current + ultrasparcs. */ + |MASK_DEPRECATED_V8_INSNS }, { 0, 0, 0, 0 } }; struct cpu_table *cpu; @@@@ -368,7 +373,7 @@@@ sparc_init_modes (); if ((profile_flag || profile_block_flag) - && sparc_cmodel != CM_MEDLOW) + && sparc_cmodel != CM_32 && sparc_cmodel != CM_MEDLOW) { error ("profiling does not support code models other than medlow"); } @@@@ -3108,6 +3113,32 @@@@ } } +/* Output any necessary .register pseudo-ops. */ +void +sparc_output_scratch_registers (file) + FILE *file; +{ +#ifdef HAVE_AS_REGISTER_PSEUDO_OP + int i; + + if (TARGET_ARCH32) + return; + + /* Check if %g[2367] were used without + .register being printed for them already. */ + for (i = 2; i < 8; i++) + { + if (regs_ever_live [i] + && ! sparc_hard_reg_printed [i]) + { + sparc_hard_reg_printed [i] = 1; + fprintf (file, "\t.register\t%%g%d, #scratch\n", i); + } + if (i == 3) i = 5; + } +#endif +} + /* Output code for the function prologue. */ void @@@@ -3116,6 +3147,8 @@@@ int size; int leaf_function; { + sparc_output_scratch_registers (file); + /* Need to use actual_fsize, since we are also allocating space for our callee (and our own register save area). */ actual_fsize = compute_frame_size (size, leaf_function); @@@@ -3753,6 +3786,14 @@@@ while (intslots > 0); } +/* A subroutine of function_arg_record_value. Traverse the structure + recusively and determine how many registers will be required. */ + +/* A subroutine of function_arg_record_value. Traverse the structure + recursively and assign bits to floating point registers. Track which + bits in between need integer registers; invoke function_arg_record_value_3 + to make that happen. */ + static void function_arg_record_value_2 (type, startbitpos, parms) tree type; @@@@ -3812,6 +3853,9 @@@@ } } +/* Used by function_arg and function_value to implement the complex + Sparc64 structure calling conventions. */ + static rtx function_arg_record_value (type, mode, slotno, named, regbase) tree type; @@@@ -3834,10 +3878,12 @@@@ if (parms.intoffset != -1) { + unsigned int startbit, endbit; int intslots, this_slotno; - intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1) - / BITS_PER_WORD; + startbit = parms.intoffset & -BITS_PER_WORD; + endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; + intslots = (endbit - startbit) / BITS_PER_WORD; this_slotno = slotno + parms.intoffset / BITS_PER_WORD; intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); @@@@ -4532,6 +4578,152 @@@@ return string; } +/* Emit a library call comparison between floating point X and Y. + COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). + TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode + values as arguments instead of the TFmode registers themselves, + that's why we cannot call emit_float_lib_cmp. */ +void +sparc_emit_float_lib_cmp (x, y, comparison) + rtx x, y; + enum rtx_code comparison; +{ + char *qpfunc; + rtx slot0, slot1, result, tem, tem2; + enum machine_mode mode; + + switch (comparison) + { + case EQ: + qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; + break; + + case NE: + qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; + break; + + case GT: + qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; + break; + + case GE: + qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; + break; + + case LT: + qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; + break; + + case LE: + qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; + break; + + /* case UNORDERED: + case UNGT: + case UNLT: + case UNEQ: + case UNGE: + case UNLE: + case LTGT: + qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; + break; + */ + default: + abort(); + break; + } + + if (TARGET_ARCH64) + { + if (GET_CODE (x) != MEM) + { + slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); + emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); + } + else + slot0 = x; + + if (GET_CODE (y) != MEM) + { + slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); + emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); + } + else + slot1 = y; + + emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1, + DImode, 2, + XEXP (slot0, 0), Pmode, + XEXP (slot1, 0), Pmode); + + mode = DImode; + } + else + { + emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1, + SImode, 2, + x, TFmode, y, TFmode); + + mode = SImode; + } + + + /* Immediately move the result of the libcall into a pseudo + register so reload doesn't clobber the value if it needs + the return register for a spill reg. */ + result = gen_reg_rtx (mode); + emit_move_insn (result, hard_libcall_value (mode)); + + switch (comparison) + { + default: + emit_cmp_insn (result, const0_rtx, NE, + NULL_RTX, mode, 0, 0); + break; + /* case ORDERED: + case UNORDERED: + emit_cmp_insn (result, GEN_INT(3), + (comparison == UNORDERED) ? EQ : NE, + NULL_RTX, mode, 0, 0); + break; + case UNGT: + case UNGE: + emit_cmp_insn (result, const1_rtx, + (comparison == UNGT) ? GT : NE, + NULL_RTX, mode, 0, 0); + break; + case UNLE: + emit_cmp_insn (result, const2_rtx, NE, + NULL_RTX, mode, 0, 0); + break; + case UNLT: + tem = gen_reg_rtx (mode); + if (TARGET_ARCH32) + emit_insn (gen_andsi3 (tem, result, const1_rtx)); + else + emit_insn (gen_anddi3 (tem, result, const1_rtx)); + emit_cmp_insn (tem, const0_rtx, NE, + NULL_RTX, mode, 0, 0); + break; + case UNEQ: + case LTGT: + tem = gen_reg_rtx (mode); + if (TARGET_ARCH32) + emit_insn (gen_addsi3 (tem, result, const1_rtx)); + else + emit_insn (gen_adddi3 (tem, result, const1_rtx)); + tem2 = gen_reg_rtx (mode); + if (TARGET_ARCH32) + emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); + else + emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); + emit_cmp_insn (tem2, const0_rtx, + (comparison == UNEQ) ? EQ : NE, + NULL_RTX, mode, 0, 0); + break;*/ + } +} + /* Return the string to output a conditional branch to LABEL, testing register REG. LABEL is the operand number of the label; REG is the operand number of the reg. OP is the conditional expression. The mode @@@@ -5850,6 +6042,8 @@@@ { char *sp_str = reg_names[STACK_POINTER_REGNUM]; unsigned long gmask = current_frame_info.gmask; + + sparc_output_scratch_registers (file); /* This is only for the human reader. */ fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); @ 1.3 log @Update patch set against a sync of source from gnusrc/dist/toolchain. Not very many overall changes. Main ones include 1. Support for powerpc, arm32 and vax 2. Makefile.gcc can now be included by anything which depends on gcc versions. If the version installed isn't 2.95.3 it'll add itself as a BUILD_DEPENDS. (XXX: any of the makefile's in pkgsrc should be checked and change to use this) 3. Remove special PLIST.NetBSD-sparc as it's no longer needed 4. Change post-extract loop to pick up any arch files from FILESDIR without having to hardcode all the archs 5. Remove arch restrictions as this should work on any arch supported by the main source tree as of 03/28/02 6. Add PKGREVISION as this clearly isn't stock 2.95.3 (it doesn't change gcc --version so version checks won't care). @ text @d1 1 a1 1 $NetBSD$ @ 1.2 log @Update "gcc" package to version 2.95.3. This is a bug fix release of version 2.95.2. This package includes all changes to "gcc" from the new toolchain in NetBSD-current. The only tested (and enabled) platform is "NetBSD-*-i386" so far. @ text @d3 2 a4 2 --- ../gcc-2.95.3/gcc/config/sparc/sparc.c.orig Thu Jan 25 15:03:37 2001 +++ ../gcc-2.95.3/gcc/config/sparc/sparc.c Thu Jan 3 20:37:53 2002 d119 154 a272 1 @@@@ -5850,6 +5896,8 @@@@ @ 1.1 log @Make sure that sjlj exceptions are used everywhere and be consistent with the defines. While I'm here pull across a fix for LIB_SPEC that prevents libc from being linked in when linking a shared library. Fixes pkg/12620 from Takuya SHIOZAKI @ text @d3 5 a7 8 --- ../gcc-2.95.2/gcc/config/arm/netbsd.h.orig Mon Jan 11 13:33:58 1999 +++ ../gcc-2.95.2/gcc/config/arm/netbsd.h @@@@ -48,7 +48,7 @@@@ /* Until they use ELF or something that handles dwarf2 unwinds and initialization stuff better. */ -#undef DWARF2_UNWIND_INFO +#define DWARF2_UNWIND_INFO 0 d9 119 a127 2 /* Some defines for CPP. arm32 is the NetBSD port name, so we always define arm32 and __arm32__. */ @