head 1.34; access; symbols pkgsrc-2016Q3:1.33.0.8 pkgsrc-2016Q3-base:1.33 pkgsrc-2016Q2:1.33.0.6 pkgsrc-2016Q2-base:1.33 pkgsrc-2016Q1:1.33.0.4 pkgsrc-2016Q1-base:1.33 pkgsrc-2015Q4:1.33.0.2 pkgsrc-2015Q4-base:1.33 pkgsrc-2015Q3:1.32.0.20 pkgsrc-2015Q3-base:1.32 pkgsrc-2015Q2:1.32.0.18 pkgsrc-2015Q2-base:1.32 pkgsrc-2015Q1:1.32.0.16 pkgsrc-2015Q1-base:1.32 pkgsrc-2014Q4:1.32.0.14 pkgsrc-2014Q4-base:1.32 pkgsrc-2014Q3:1.32.0.12 pkgsrc-2014Q3-base:1.32 pkgsrc-2014Q2:1.32.0.10 pkgsrc-2014Q2-base:1.32 pkgsrc-2014Q1:1.32.0.8 pkgsrc-2014Q1-base:1.32 pkgsrc-2013Q4:1.32.0.6 pkgsrc-2013Q4-base:1.32 pkgsrc-2013Q3:1.32.0.4 pkgsrc-2013Q3-base:1.32 pkgsrc-2013Q2:1.32.0.2 pkgsrc-2013Q2-base:1.32 pkgsrc-2013Q1:1.31.0.12 pkgsrc-2013Q1-base:1.31 pkgsrc-2012Q4:1.31.0.10 pkgsrc-2012Q4-base:1.31 pkgsrc-2012Q3:1.31.0.8 pkgsrc-2012Q3-base:1.31 pkgsrc-2012Q2:1.31.0.6 pkgsrc-2012Q2-base:1.31 pkgsrc-2012Q1:1.31.0.4 pkgsrc-2012Q1-base:1.31 pkgsrc-2011Q4:1.31.0.2 pkgsrc-2011Q4-base:1.31 pkgsrc-2011Q3:1.30.0.14 pkgsrc-2011Q3-base:1.30 pkgsrc-2011Q2:1.30.0.12 pkgsrc-2011Q2-base:1.30 pkgsrc-2011Q1:1.30.0.10 pkgsrc-2011Q1-base:1.30 pkgsrc-2010Q4:1.30.0.8 pkgsrc-2010Q4-base:1.30 pkgsrc-2010Q3:1.30.0.6 pkgsrc-2010Q3-base:1.30 pkgsrc-2010Q2:1.30.0.4 pkgsrc-2010Q2-base:1.30 pkgsrc-2010Q1:1.30.0.2 pkgsrc-2010Q1-base:1.30 pkgsrc-2009Q4:1.29.0.28 pkgsrc-2009Q4-base:1.29 pkgsrc-2009Q3:1.29.0.26 pkgsrc-2009Q3-base:1.29 pkgsrc-2009Q2:1.29.0.24 pkgsrc-2009Q2-base:1.29 pkgsrc-2009Q1:1.29.0.22 pkgsrc-2009Q1-base:1.29 pkgsrc-2008Q4:1.29.0.20 pkgsrc-2008Q4-base:1.29 pkgsrc-2008Q3:1.29.0.18 pkgsrc-2008Q3-base:1.29 cube-native-xorg:1.29.0.16 cube-native-xorg-base:1.29 pkgsrc-2008Q2:1.29.0.14 pkgsrc-2008Q2-base:1.29 cwrapper:1.29.0.12 pkgsrc-2008Q1:1.29.0.10 pkgsrc-2008Q1-base:1.29 pkgsrc-2007Q4:1.29.0.8 pkgsrc-2007Q4-base:1.29 pkgsrc-2007Q3:1.29.0.6 pkgsrc-2007Q3-base:1.29 pkgsrc-2007Q2:1.29.0.4 pkgsrc-2007Q2-base:1.29 pkgsrc-2007Q1:1.29.0.2 pkgsrc-2007Q1-base:1.29 pkgsrc-2006Q4:1.27.0.2 pkgsrc-2006Q4-base:1.27 pkgsrc-2006Q3:1.26.0.2 pkgsrc-2006Q3-base:1.26 pkgsrc-2006Q2:1.25.0.4 pkgsrc-2006Q2-base:1.25 pkgsrc-2006Q1:1.25.0.2 pkgsrc-2006Q1-base:1.25 pkgsrc-2005Q4:1.24.0.8 pkgsrc-2005Q4-base:1.24 pkgsrc-2005Q3:1.24.0.6 pkgsrc-2005Q3-base:1.24 pkgsrc-2005Q2:1.24.0.4 pkgsrc-2005Q2-base:1.24 pkgsrc-2005Q1:1.24.0.2 pkgsrc-2005Q1-base:1.24 pkgsrc-2004Q4:1.23.0.2 pkgsrc-2004Q4-base:1.23 pkgsrc-2004Q3:1.21.0.2 pkgsrc-2004Q3-base:1.21 pkgsrc-2004Q2:1.20.0.2 pkgsrc-2004Q2-base:1.20 pkgsrc-2004Q1:1.19.0.2 pkgsrc-2004Q1-base:1.19 pkgsrc-2003Q4:1.18.0.2 pkgsrc-2003Q4-base:1.18 netbsd-1-6-1:1.16.0.2 netbsd-1-6-1-base:1.16 netbsd-1-6:1.10.0.8 netbsd-1-6-RELEASE-base:1.10 pkgviews:1.10.0.4 pkgviews-base:1.10 buildlink2:1.10.0.2 buildlink2-base:1.10 netbsd-1-5-PATCH003:1.9 netbsd-1-5-PATCH001:1.3; locks; strict; comment @# @; 1.34 date 2016.10.08.14.21.12; author kamil; state dead; branches; next 1.33; commitid 7ggP0x06TpGRFlpz; 1.33 date 2015.11.03.00.21.20; author agc; state Exp; branches; next 1.32; commitid U9LdmD9Br2eCXzHy; 1.32 date 2013.05.23.15.00.00; author joerg; state Exp; branches; next 1.31; commitid eXdWuzD6BnF9zLQw; 1.31 date 2011.11.26.17.10.24; author joerg; state Exp; branches; next 1.30; 1.30 date 2010.02.28.15.59.19; author dmcmahill; state Exp; branches; next 1.29; 1.29 date 2007.03.01.01.03.45; author dmcmahill; state Exp; branches; next 1.28; 1.28 date 2007.02.21.23.18.44; author dmcmahill; state Exp; branches; next 1.27; 1.27 date 2006.10.10.00.19.49; author dmcmahill; state Exp; branches; next 1.26; 1.26 date 2006.08.11.13.28.08; author dmcmahill; state Exp; branches; next 1.25; 1.25 date 2006.01.25.12.11.01; author dmcmahill; state Exp; branches; next 1.24; 1.24 date 2005.02.23.14.59.25; author agc; state Exp; branches; next 1.23; 1.23 date 2004.11.27.02.50.09; author dmcmahill; state Exp; branches; next 1.22; 1.22 date 2004.09.21.02.23.19; author dmcmahill; state Exp; branches; next 1.21; 1.21 date 2004.09.02.01.55.47; author dmcmahill; state Exp; branches; next 1.20; 1.20 date 2004.06.07.01.09.50; author dmcmahill; state Exp; branches; next 1.19; 1.19 date 2004.03.02.15.34.07; author drochner; state Exp; branches; next 1.18; 1.18 date 2003.08.25.11.21.50; author drochner; state Exp; branches; next 1.17; 1.17 date 2003.07.14.09.51.48; author drochner; state Exp; branches; next 1.16; 1.16 date 2003.02.04.00.46.07; author dmcmahill; state Exp; branches; next 1.15; 1.15 date 2002.10.22.02.52.18; author dmcmahill; state Exp; branches; next 1.14; 1.14 date 2002.10.17.01.38.43; author dmcmahill; state Exp; branches; next 1.13; 1.13 date 2002.10.13.23.01.27; author dmcmahill; state Exp; branches; next 1.12; 1.12 date 2002.08.29.11.15.57; author dmcmahill; state Exp; branches; next 1.11; 1.11 date 2002.08.24.04.36.45; author dmcmahill; state Exp; branches; next 1.10; 1.10 date 2002.05.07.00.11.20; author dmcmahill; state Exp; branches; next 1.9; 1.9 date 2002.03.28.03.07.29; author dmcmahill; state Exp; branches; next 1.8; 1.8 date 2002.01.16.19.33.18; author dmcmahill; state Exp; branches; next 1.7; 1.7 date 2001.12.15.18.43.37; author dmcmahill; state Exp; branches; next 1.6; 1.6 date 2001.10.24.12.27.11; author dmcmahill; state Exp; branches; next 1.5; 1.5 date 2001.07.03.18.23.46; author dmcmahill; state Exp; branches; next 1.4; 1.4 date 2001.05.21.22.25.19; author dmcmahill; state Exp; branches; next 1.3; 1.3 date 2001.04.28.03.45.05; author dmcmahill; state Exp; branches; next 1.2; 1.2 date 2001.04.19.16.27.02; author agc; state Exp; branches; next 1.1; 1.1 date 2001.04.17.10.30.26; author agc; state Exp; branches; next ; desc @@ 1.34 log @Remove verilog-current It used to track icarus verilog but there is no update since 20090923. No objections from @ text @$NetBSD: distinfo,v 1.33 2015/11/03 00:21:20 agc Exp $ SHA1 (verilog-20090923.tar.gz) = 1836ebc4ef78341fb1a077e807c8d5b195ebb253 RMD160 (verilog-20090923.tar.gz) = 32a009d1390e71721d3a72a1940b655ed1853ba5 SHA512 (verilog-20090923.tar.gz) = b873ddc7e300f504ded0ba0e71527f1a24ba469d7aa8603b8e83f32cb29da2219b6e0c68060a1d1a32450024640e0b47d8284d52f0733c396651c2cfef3e6b7d Size (verilog-20090923.tar.gz) = 1121376 bytes SHA1 (patch-ad) = 9492af75153405c49076f2dcd11d2dc338640514 SHA1 (patch-net__scope.cc) = 97cf7d099b30b3549ad6262022ca32e8790b5d66 SHA1 (patch-pform__disciplines.cc) = 113365b68723462791728e6f998685a4ebca3547 @ 1.33 log @Add SHA512 digests for distfiles for cad category Problems found with existing distfile for eagle: distfiles/eagle-lin32-7.4.0.run No changes made to eagle/distinfo file. Otherwise, existing SHA1 digests verified and found to be the same on the machine holding the existing distfiles (morden). All existing SHA1 digests retained for now as an audit trail. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.32 2013/05/23 15:00:00 joerg Exp $ @ 1.32 log @Casting 0 to an iterator is not portable. Just use end() in that case. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.31 2011/11/26 17:10:24 joerg Exp $ d5 1 @ 1.31 log @Fix C++ @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.30 2010/02/28 15:59:19 dmcmahill Exp $ d7 1 @ 1.30 log @Update to the 20090923 snapshot. It has been a long time since the last update to this snapshot package. Besides the various upstream changes, also - add LICENSE - add DESTDIR support (partially enabled by upstream fixes) Release Notes for Snapshot 20090923 This is the first snapshot after the split from the 0.9 release. Mostly, this snapshot is loaded with 7 months worth of bug fixes. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.29 2007/03/01 01:03:45 dmcmahill Exp $ d7 1 @ 1.29 log @update to verilog-current-20070227 Release Notes for Icarus Verilog Snapshot 20070227 * Fix some problems with specify block parsing. Detect some cases that are parsed but not properly implemented yet and issue warnings or errors. Also fixed a few problems with inertial delay model timing. * Detect is some cases Verilog source errors that can be better reported to users. This includes more specific error messages for certain syntax errors. * Fix problems with overridden continuous assignments. * Hide bool types from logic type as far as VPI is concerned, for the sake of compatibility. * Fix a variety of code generator expression lifetime bugs that caused obscure (and wrong) output results in behavioral code. * iverilog-vpi uses the compiler selected at build time. * Rework handling of strings to handle escape sequences properly. * Fix some handling of real values in some expression types. * Get padding of sized, unsigned numbers when x or z are involved. * Many, many more misc. bug fixes. * Add an assert mechinism that improves usefulness of bug reports by reporting source file line numbers when available. * Compile fixes, using inttypes.h instead of stdint for portability. * Various spelling fixes. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.28 2007/02/21 23:18:44 dmcmahill Exp $ d3 3 a5 3 SHA1 (verilog-20070227.tar.gz) = eb6f26393946505617b7a7e2405e760b92eefbf0 RMD160 (verilog-20070227.tar.gz) = c9add1099fb07b50df3a5d232b3307d64bb235c9 Size (verilog-20070227.tar.gz) = 1583940 bytes @ 1.28 log @Update to verilog-current-20070123 Release Note for Icarus Verilog Snapshot 20070123 Handling of arrays has been rewritten to allow support for net arrays. This caused ivl_target API changes, as well as elaboration and vvp run time changes. There may be bits of the old method lingering in the source code. Improve support for constant power (**) expressions, and other constant exppressions that are passed to functions/tasks. Improve elaboration of for-loop increment expressions. There were some bugs there that are not fixed. Fix argument width calculations for shift operations. Constant ector expressions can have real constants. Handle this at run time where needed. Fix some bad lookaside optimizations for assignments to l-value part selects. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.27 2006/10/10 00:19:49 dmcmahill Exp $ d3 3 a5 3 SHA1 (verilog-20070123.tar.gz) = 6b737279fe876e039322a6c31457372073366ec1 RMD160 (verilog-20070123.tar.gz) = 351ef57933d03064666f0b209448e76bb943c5fa Size (verilog-20070123.tar.gz) = 1577268 bytes @ 1.27 log @update to verilog-current-20061009 * Release Notes for Icarus Verilog Snapshot 20061009 The Big news is support for delay path timing is specify blocks. This includes delay paths and specparams. Back annotation of specify path timings are not yet implemented. The "-g" flag has been made a bit more general so that individual compiler features can be turned on/off. This for example allows for turning off specify block support and Icarus Verilog extensions, as well as select language generation. A variety of bug fixes have been included. - Missing symbols on Windows fixed. - mingw build instructions reworked. - Fix internal handling of -D__ICARUS__ define - Fix crash of driver when -M flag is used. - Fix configure detection of host in some subdirectories. - Handle non-constant delays of index non-blocking assignments. - $scanf support for real values. - Fix scheduling of RWsync vs. ROSync callbacks. - Fix vpi_put_userdata return value. The iverilog-vpi command now allows .cpp files to stand for C++ source. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.26 2006/08/11 13:28:08 dmcmahill Exp $ d3 3 a5 3 SHA1 (verilog-20061009.tar.gz) = 0dbb5385d7e332eadcaeb589ea1d2d31980eb237 RMD160 (verilog-20061009.tar.gz) = de4501f311b09b89b649570cfcb6b95603f22cc4 Size (verilog-20061009.tar.gz) = 1604430 bytes @ 1.26 log @Update to 20060809 snapshot. There have been several changes since the last packaged snapshot. Those are: -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060215 -------------------------------------------------- * Part select of memory words should now work according to Verilog-2001. This also led to some cleanup of the handling of types internally, as well as some infrastructure for general arrays. * Minor fix to parsing of (* *) attributes. * Fix rounding of reals to integers. * Clean up some of the vvp engine related to memories. Remove some dead instructions. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060409 -------------------------------------------------- the most substantial difference in this snapshot the first signs of generate support. The compiler now supports generate loops and has been tested with examples that include wires and gates within the generate scheme. The regression test suite has very few generate tests, so any concise self-testing test programs that use generate would be helpful. Also, instance arrays that use overridden parameters now work properly. Task arguments are a bit more flexible in order to support vendor (notably Xilinx) models that use more interesting task arguments. Runtime support for bi-directional ports had some bugs fixed, along with some other minor run-time bugs. Also, the runtime gains support for typed parameters. And also, there are some new runtime callbacks for events and memories. Parameters had a few types related bugs fixed. They are a bit more flexible now. And various minor compilation errors have been fixed. This includes C/C++ compilation errors fixes, and some configure/Makefile tweaks. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060618 -------------------------------------------------- Add support for system functions in continuous assignments. Allow concatenations as arguments to inout ports. This comes with a small variety of internal part select and concatenation bug fixes. Fix some bugs in constant propagation through ternary expressions. Fix broken subtraction if small constants in certain cases. Fix a few datatype mismatch errors. Make $readmem give warning when input is inadequate for requested range. Fix runtime of nand in continuous assignments. Fix synchronous user defined primiteves to only follow edges. Fix a runtime error in some thread delays processing. Improve limited genvar expression handling. Start a rework of expression elaboration. Make elaboration aware of the expression context width when appropriate in order to better handle expression width and padding. Fix the make rules for parse.cc to reflect that they come from the same source. Fix the autoconf.sh to configure the stub target. Fix portability of the lexor source files on Windows systems. Get rid of the isatty references. Make a stub lround when the system version is missing. -------------------------------------------------- * Release Notes for Snapshot 20060809 -------------------------------------------------- Some handling of real values is improved. Real valued literals are handled in net contexts (continuous assignment, etc.). Also, modulus of real operands now works. (This is an extension to the Verilog standard.) The power operator (**) now works. Signed right shift works properly now. The $sscanf and $fscanf are introduced, and work at least for basic numeric values. The release function now works to undo general force statements, and not just contant force statements. Delay constants up to 64 bits are supported. This at first doesn't seem like an issue, but when precisions are mixed, it becomes surprisingly easy to overflow 32bit delays. The driver is reworked to pass many preprocessor details through a temporary file instead of on the command line of a system(3) call. This prevents confusing and incorrect shell processing of complex strings passed as values to -D flags. Various other little fixes. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.25 2006/01/25 12:11:01 dmcmahill Exp $ d3 3 a5 3 SHA1 (verilog-20060809.tar.gz) = a24c822230472df69c646366f5a6a8ff79386965 RMD160 (verilog-20060809.tar.gz) = b34fe487677aaf4f417649b7cad7e7bf994d16be Size (verilog-20060809.tar.gz) = 1584583 bytes @ 1.25 log @update to 20060124 snapshot. A few new features have been added to allow proper simulation with newer Xilinx UNISIM models. (They are starting to use Verilog 2001 features.) And also various bug fixes in this release. -- Primitive and continuous assign delays can now be non-constant. This needed some new run-time support, so vvp had a slight format change, and certain new optimizations follow as a result. -- Bug handling certain constant sub-expressions in concatenation expressions. Also, allow concat expressions in constant contexts. -- Support for wide divide expressions. -- Fixes for stubborn compilers. -- Fix bugs in padding of signed expressions. -- More fixes for following the data types of expressions. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.24 2005/02/23 14:59:25 agc Exp $ d3 4 a6 4 SHA1 (verilog-20060124.tar.gz) = 4b3784aeb5b91c0672522cd420dd96e73bd4e33c RMD160 (verilog-20060124.tar.gz) = de536f3d9c811dbbeea36bb64007aa26355dddcb Size (verilog-20060124.tar.gz) = 1507887 bytes SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a @ 1.24 log @Add RMD160 digests in addition to SHA1 ones. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.23 2004/11/27 02:50:09 dmcmahill Exp $ d3 3 a5 3 SHA1 (verilog-20041004.tar.gz) = 820763bbf1f5e3f001f73e195d274be76b8ae0a4 RMD160 (verilog-20041004.tar.gz) = a8cf81f67b86d930f055e276d41589cbef71c003 Size (verilog-20041004.tar.gz) = 1371537 bytes @ 1.23 log @update to verilog-current 20041004. Release Notes for Icarus Verilog Snapshot 20041004 Some minor Makefile bugs have been fixed, and source file text formatting has in some cases been normalized for release. Also, configure scripts have been factored for a more consistent build. Fixed continuous assignments to carry strength when needed for correct behavior. This bug led to subtly incorrect reset behavior, but could have caused strength modeling errors in a variety of situations. Fixed some <= vs >= behaviors to be consistent. The results of these comparisons, when sized values are involved, are more standard now. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.22 2004/09/21 02:23:19 dmcmahill Exp $ d4 1 @ 1.22 log @update to verilog-current-20040915. Changes in this snapshot: The big news is that module instance arrays now work. Gate and UDP instance arrays have worked for a while, but module instance arrays were more tricky because of the scope arrys they create. The issues have been dealt with, and module instance arrays are now supported. An interesting but subtle set of bugs in the evaluation of ternary expressions has been fixed. The problems expressed themselves when the condition expression was constant. Degenerate wait statements now work properly. The @@* syntax apparently missed sensitivities in l-value expressions of assignment statements. This led to subtle bugs in carefully crafted bits of code. Verilog attributes are properly parsed in a few more contexts. Also, some specify syntax cases have been fixed. Some minor spelling and documentation errors have been fixed, along with assorted compiler warnings. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.21 2004/09/02 01:55:47 dmcmahill Exp $ d3 2 a4 2 SHA1 (verilog-20040915.tar.gz) = 44bf7d444fa2dac6b598d133c3e86557662679c4 Size (verilog-20040915.tar.gz) = 1371319 bytes @ 1.21 log @update to verilog-current-20040828 changes include: Added support for the `default_nettype directine, including the default net type of "none", which turns off implicit net declarations. Signed /, % and >>> in nets should now work properly. Also, various operators of all sorts applied to constants have been improved. Ranges now work on localparams. Added the system tasks $unsigned, $is_signed, $mti_random and $mti-dist_uniform. See the make README.txt for a description of these system functions. Also, flesh out the standard random number generators to match the sequences generated by other compilers. There is now an "sft" file that describes to the compiler the return value of system functions. This allows user supplied system functions to have interesting return types. See "SYSTEM FUNCTIO TABLE FILES" in the iverilog man page. Include a sft file for the system functions, and move the system functions over to that mechinism. Fix the behavior of $fgets in tight fitting result buffers. A variety of compilation environment fixes have been added. These involve configure scripts and Makefiles. And of course a variety of other bug fixes, and so on and so forth. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.20 2004/06/07 01:09:50 dmcmahill Exp $ d3 2 a4 2 SHA1 (verilog-20040828.tar.gz) = b6e44dc0556247687d068c913bcd4080edfc0285 Size (verilog-20040828.tar.gz) = 1368773 bytes @ 1.20 log @update to verilog-current-20040606 * Release Notes for Icarus Verilog Snapshot 20040606 Ports of primitives can bind by name as well as by position. Also support Verilog 2001 style port declarations for primitives. System function return types can now be specified by system function table files. System Function Table Files are described in the iverilog man page. Also include better system function return types in VPI. Non-blocking assign of real values to real variables now works. Properly handle nul strings ("") as 8bit values. This is a weirdness legacy of XL. Fix some synthesis problems for logical OR and logical AND. Bitwise OR and AND were fine. These fixes affected simulation as well. Handle wait statements with all sorts of constant values. These are sometimes weird, bug legal. Handle Negative value reals, and a few other bugs related to real numbers. Change internal use of identifiers to perm_strings for better performance. Functions returning unsupported types now generate error messages. Previously, they would quietly generate bad code. Infrastructure is also added to eventually support arbitrary function return types. Better compile-time support for Cygwin vs mingw32. The ipal target is removed from this source. (ipal is now an add-on package that is compiled seperately.) @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.19 2004/03/02 15:34:07 drochner Exp $ d3 2 a4 2 SHA1 (verilog-20040606.tar.gz) = f91dc4c6e93eef13fab6dbc80144ed48c633d1eb Size (verilog-20040606.tar.gz) = 1361219 bytes @ 1.19 log @update to the 20040220 snapshot changes: bugfixes, VPI extensions @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.18 2003/08/25 11:21:50 drochner Exp $ d3 2 a4 2 SHA1 (verilog-20040220.tar.gz) = 22b09fced8cbc5cc0665574d03595aa367ccdb3b Size (verilog-20040220.tar.gz) = 1354505 bytes @ 1.18 log @update to the 20030815 shapshot changes are basically bugfixes, and improvements in the FPGA synthesis area @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.17 2003/07/14 09:51:48 drochner Exp $ d3 2 a4 2 SHA1 (verilog-20030815.tar.gz) = 64ee9ca573882fd2a414fc62ee17302fc0bca26e Size (verilog-20030815.tar.gz) = 1246700 bytes @ 1.17 log @update to snapshot "20030705". There was a couple of snapshots since february; besides bugfixes the major highligths might be: -handling of real values at various places -support for library modules (esp cadence PLI1) -better FPGA support (esp Virtex II) -"vvp" interactive mode added Also converted to buildlink2, and dependencies to libz, libbz2 and readline added. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.16 2003/02/04 00:46:07 dmcmahill Exp $ d3 2 a4 2 SHA1 (verilog-20030705.tar.gz) = 1f6d0284b8efa63441e8b2650d11df434a48f374 Size (verilog-20030705.tar.gz) = 910118 bytes @ 1.16 log @update to verilog-current-20030202. This is the first packaged (in pkgsrc) snapshot after the verilog-0.7 release. This snapshot adds preliminary support for real variables to the language to the features already found in verilog-0.7. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.15 2002/10/22 02:52:18 dmcmahill Exp $ d3 3 a5 3 SHA1 (verilog-20030202.tar.gz) = 9bf846546bde334d251c0c5c7f191b3d76fa159c Size (verilog-20030202.tar.gz) = 829887 bytes SHA1 (patch-ad) = dbf85e203f91d0df3a8aed12494a6de83b3f6c40 @ 1.15 log @update to verilog-current-20021019 Release Notes for Icarus Verilog Snapshot 20021019 The synthesizer now detects asynchronous set/reset inputs to DFF devices. The fpga and vvp code generators have been updated to support these signals. The vvp code generator also gained some register management code that improves the thread register usage. This redoces code size for certain common cases, and thus improves simulation performance. The requirements on `ifdef and related compiler directives has been relaxed, to correspond to more common behavior. The parameter range support crashed if the range expressions had parameters in them. This is fixed, and some signed-ness bugs fixed along with it. Rearrange some of the configure script tests to assure better compatibility accross platforms. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.14 2002/10/17 01:38:43 dmcmahill Exp $ d3 3 a5 3 SHA1 (verilog-20021019.tar.gz) = 9e92190d3f6f081ba07a25f3bab05fb3e39693d8 Size (verilog-20021019.tar.gz) = 825125 bytes SHA1 (patch-ad) = 610a4b597b056f4e951cb75bdb13a9370efec300 @ 1.14 log @fix the iverilog-vpi shell script (bash-isms) @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.13 2002/10/13 23:01:27 dmcmahill Exp $ d3 2 a4 3 SHA1 (verilog-20020921.tar.gz) = 8bd1461ad676194b37c7ba74d3a714eaacf264c9 Size (verilog-20020921.tar.gz) = 822496 bytes SHA1 (patch-aa) = 15a15c8c85739bacbd0a85504596be023e9d97c5 @ 1.13 log @update to verilog-current-20020921 snapshot. Many improvemnts in the synthesis code and bug fixes in the simulation code since the last packaged snapshot. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.12 2002/08/29 11:15:57 dmcmahill Exp $ d5 1 @ 1.12 log @update to verilog-current-20020828 Release Notes for Snapshot 20020828 This snapshot adds support for parameter and localparam bit ranges. This is a IEEE1364-2001 feature, although some -1995 compilers have supported it in the past. Fixed a *nasty* and slippery bug with the evaluation of bit select of nets. (Bit select of variables was unaffected.) The symptoms did not clearly point to the problem, so bugs related to it were often mis- reported. Gate delays were lost when constants were propagated to their inputs. This is fixed for the known broken cases. Also, mux output delays have been fixed. Also, release statements that apply to elided nets are turned into no-ops. The r-values of non-blocking assignments are now precalculated at compile time, if possible, as is done with blocking assignments. This speeds up constant propagation, and is more thorough. Also optimize subtraction of small constants from vectors, with the new %subi instruction in vvp. This saves some in code size and thread footprint. Handling of x in r-value bit selects and memory word selects did the wrong thing. Now they do the right thing. Also, x in the selector of ?: ternary operators does the right (and complicated) thing now. In the process, a fork-join code generator bug was fixed. Several bugs with time formatting have been fixed. Temporaries in sequential blocks are detected by the synthesizer, and converted into wires when needed. This expands support for combinational logic synthesis. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.11 2002/08/24 04:36:45 dmcmahill Exp $ d3 2 a4 2 SHA1 (verilog-20020828.tar.gz) = 19fb0e1e9f22b9819d2369aca370fb806381bb3d Size (verilog-20020828.tar.gz) = 815247 bytes @ 1.11 log @update to verilog-current-20020817. Many many changes and bug fixes since the last packaged snapshot. Better language coverage, better performance, improved synthesis, fixed bugs. Too much to list here. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.10 2002/05/07 00:11:20 dmcmahill Exp $ d3 2 a4 2 SHA1 (verilog-20020817.tar.gz) = 61170d811c5c7eafbe7f05007ac4010a51c81f68 Size (verilog-20020817.tar.gz) = 809419 bytes @ 1.10 log @update to verilog-current-20020505 many improvements and bug fixes since the last packaged snapshot including: -added the $sizeof system function as a builtin -In VPI, the simulator event callbacks now work -Concatenation expressions in parameters were broken are broken -added the vpiModule iterator to VPI scope handles @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.9 2002/03/28 03:07:29 dmcmahill Exp $ d3 2 a4 2 SHA1 (verilog-20020505.tar.gz) = 61740400906b74764926a314eb262bcf959ca2d7 Size (verilog-20020505.tar.gz) = 771413 bytes @ 1.9 log @update to verilog-current-20020317 Release Notes for snapshot 20020317 The first difference in this snapshot from the 0.6 release is that vvm is no longer compiled by default. If you want to compile vvm, you must enable it at configure time (--enable-vvm) and rebuild from scratch. Eventually, vvm will disappear from the release altogether. The next major difference is new support for user defined functions. It is new support, so it is bound to be buggy, but it should be somewhat complete. The major problem has been solved, so all that remains are bugs around the edges. The vvp run-time scheduler has been changed slightly. The run time behavior is getting increasingly precise and picky, as larger designs are thrown at the compiler. The change introduced in this snapshot fixes logic gates to not propagate zero-time pulses, and thus fixes some weird bugs in large designs. I've also added initial support for the Verilog 200x pragma comment, which are (* *) pairs. For now, the compiler ignores them as comments. This is what a compiler is supposed to do with anything that is not specifically recognized. Also, Tony (Anthony Bybell) has added LXT dump support. The LXT output file is a waveform output format that is much more compact then VCD. The gtkwave waveform viewer supports the LXT format, and should operate a bit faster when viewing LXT files. For now, there are separate system tasks for managing LXT output ($lxt_dumpvars, etc) but eventually the dump format will be selectable by environment variable or command line switch. This snapshot also includes various random bug fixes and improved error messages for incorrect code. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.8 2002/01/16 19:33:18 dmcmahill Exp $ d3 3 a5 3 SHA1 (verilog-20020317.tar.gz) = ed654587e73d6a6c9a987784e5905b3c7c52d974 Size (verilog-20020317.tar.gz) = 744554 bytes SHA1 (patch-ad) = 3c035d32d011d81520e428e3dd9adae435fc63e7 @ 1.8 log @update to verilog-current-20020112 many many changes since the last packaged snapshot. A brief sampling of the changes (which include many bug fixes and enhancements) is: A variety of little problems with $display format strings have been fixed. The % operand should now simulate properly. Also, the * operator is a little bit more optimized, and works in constant expressions. Several bugs in strength modeling have been fixed. This includes drive strengths on continuous assignments, which in the past generated code without the strengths. Also, vvp gained some missing support for constants with strength. I think that strength modeling is now complete. vpi_get_vlog_info support has been added to the vvp run-time. This is a PLI function that allows access to run-time command flags. Also, vpi access to root modules now works properly. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.7 2001/12/15 18:43:37 dmcmahill Exp $ d3 2 a4 2 SHA1 (verilog-20020112.tar.gz) = 0e07f73cf7514a2d669a63b5990562a41dd0d85a Size (verilog-20020112.tar.gz) = 719621 bytes @ 1.7 log @update to verilog-current-20011209 snapshot. Many changes since the last packaged snapshot. A sampling of these are: Support for hierarchical names has been largely rewritten. The major consequence of this is that escaped names now have much better support. By now, most any combination of escaped and hierarchical name should work properly, for nets, parameters, and anything else. Output delays for primitive gates, including user defined primitivies, should now work properly. Delays on nets still do not work, although the parser now parses them and prints a "sorry" message. Bugs in support for division(/) and modulus (%) have been fixed. Bugs in l-values of synthesized DFF devices have been fixed. These bugs were related to part selects of vectors in l-values. A few XNF code generator bugs and limitations were fixed. And as usual, a variety of miscellaneous bugs have been fixed in this snapshot. The bit size of the results of some unary redunction operators is now properly handled. Also, similar problems with logical functions have been fixed. force/release now works for variables, though not yet for nets. Assign/deassign already work. many other bugfixes @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.6 2001/10/24 12:27:11 dmcmahill Exp $ d3 2 a4 2 SHA1 (verilog-20011209.tar.gz) = 51e41d85b45c919274df7e107653cf7dbec8fe5a Size (verilog-20011209.tar.gz) = 710175 bytes @ 1.6 log @update to verilog-current-20011020. changes since last snapshot include: - addition of a fpga target for synthesis. outputs edif, optimized for xilinx virtex parts. - fixed bug with synthesis of != - fixed bug in hex constant parsing - fixed vvp bug with subtracting very wide words - much improved VCD output - many other bug fixes and robustness improvements. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.5 2001/07/03 18:23:46 dmcmahill Exp $ d3 2 a4 2 SHA1 (verilog-20011020.tar.gz) = 34588003e98fb4764ef2168803b3cd4482691c42 Size (verilog-20011020.tar.gz) = 691955 bytes @ 1.5 log @update to 20010630 snapshot. changes are: ----------- RELEASE NOTE FOR ICARUS VERILOG 20010630 I've done some cleanup of the mingw port of Icarus Verilog. I've also added instructions for how to build Icarus Verilog under mingw. I'm working on making that the preferred way to support Windows, and when I make the 0.5 release I will make Windows binaries this way. Anyhow, feedback on the build instructions and the build results using the instructions in mingw.txt are welcome. I've make "vvp" the default target type. The older vvm behavior is available with the "-tvvm" flag to iverilog, but I would rather be told about (and fix) bugs in the vvp code generator and run time. I've added support for the (unsigned) right shift operator. The left shift has been working for a while now, but right shift somehow slipped through the cracks. The shift operators still don't quite work in structural contexts, but they should show up sometime next week. I've finally got VCD output working properly with vvp. It may even be better then with vvm, although some internal symbols are still generated. A few odd bugs have been fixed, including a code generation error for xnf, and error checking of user defined function parameters. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.4 2001/05/21 22:25:19 dmcmahill Exp $ d3 2 a4 2 SHA1 (verilog-20010630.tar.gz) = ec59c07980134670b5ad69bb1b170618d0f3ef4c Size (verilog-20010630.tar.gz) = 613776 bytes @ 1.4 log @update to verilog-current-20010520. many changes since the last snapshot. Mostly they involve expanded VVP support. The VVP target now passes >200 of the tests from the test suite. While not as complete as the VVM target, VVP is getting closer and its _much_ _much_ faster. @ text @d1 1 a1 1 $NetBSD: distinfo,v 1.3 2001/04/28 03:45:05 dmcmahill Exp $ d3 2 a4 4 SHA1 (verilog-20010520.tar.gz) = a14f17991680daf767d09e35014ecaa30eafd7ab Size (verilog-20010520.tar.gz) = 588928 bytes SHA1 (patch-aa) = 536ba689041fde309cac493fa28fd631a1ced9e2 SHA1 (patch-ab) = f051b29bf0e5cbc1be5b4aba9e82549db861d07d @ 1.3 log @update missing distinfo file from update. Thanks to Thomas Klausner for catching this one. @ text @d1 1 a1 1 $NetBSD$ d3 5 a7 4 SHA1 (verilog-20010422.tar.gz) = ef939b239062b602f60360ab61b5617bcf78b28a Size (verilog-20010422.tar.gz) = 550909 bytes SHA1 (patch-aa) = 375c8896af276cb1f66f8bf4ca9ff641181d8bc6 SHA1 (patch-ad) = ebd01d8ffbc55d8cd98682e07c22d2e30218d285 @ 1.2 log @Move to sha1 digests, and add distfile sizes. @ text @d3 2 a4 2 SHA1 (verilog-20010407.tar.gz) = 2659fe99a6faa6e838399b1213cad3b044625e93 Size (verilog-20010407.tar.gz) = 544475 bytes @ 1.1 log @+ move the distfile digest/checksum value from files/md5 to distinfo + move the patch digest/checksum values from files/patch-sum to distinfo @ text @d1 1 a1 1 $NetBSD: md5,v 1.13 2001/04/14 14:47:31 dmcmahill Exp $ d4 1 @