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locks; strict;
comment	@# @;


1.2
date	2011.09.12.11.15.33;	author dholland;	state dead;
branches;
next	1.1;

1.1
date	2008.04.05.14.09.18;	author chris;	state Exp;
branches;
next	;


desc
@@


1.2
log
@Add a distfile patch from yours truly, which may become, or may become
part of, a new upstream version, but I need to talk to some people first.
(I'm keeping this separate from the previous update in case it breaks stuff.)

Changes:
	roll in parts of patch-aa and patch-aq;
	roll in all of patch-ar and patch-src_memsize_c;
	make the ARM-only adjustment from patch-ar universal;
	add enough volatile to make 'mhz' work more or less properly again;
	fix the loop calibration to bail out instead of spinning forever
	  if things go too fast (e.g. because the compiler's optimized out
	  the benchmark loop);
	various hacking and modernization to get sort of a clean compile;
	fix some non-stdc stringifying macros;
	hopefully advance the clang build a bit further.
@
text
@$NetBSD: patch-ar,v 1.1 2008/04/05 14:09:18 chris Exp $

--- src/mhz.c.orig	2008-04-05 14:34:31.000000000 +0100
+++ src/mhz.c	2008-04-05 14:33:40.000000000 +0100
@@@@ -118,6 +118,8 @@@@ main(ac, av)
  */
 #ifdef sparc
 #	define	FOUR	a >>= 1; a >>= 1; a >>= 1; a >>= 1;
+#elif defined(__arm__)
+#	define	FOUR	a++; a >>= 1; a++; a >>= 1;
 #else
 #	ifdef _AIX	/* really for the rs6000 only */
 #		define	FOUR	a++; a++;
@


1.1
log
@Fiz mhz calculation for arm.  It seems gcc has become intelligent enough
to optimize away the loop used for timing.  Do something in the loop for
arm that can't be optimized away, and will also meet the 1,000
instructions in the loop requirement.

This allows mhz to calculate sensible Mhz on a StrongArm (228Mhz rather
than 56Mhz)

Other hardware probably also need fixing, as gcc probably applies the same
optimizations on them.

Also bump PKGREVISION.
@
text
@d1 1
a1 1
$NetBSD:$
@